rename_impl.hh revision 2329
12SN/A/* 29448SAndreas.Sandberg@ARM.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 39920Syasuko.eckert@amd.com * All rights reserved. 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67338SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77338SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97338SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117338SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127338SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137338SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 147338SAli.Saidi@ARM.com * this software without specific prior written permission. 151762SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282SN/A 292SN/A#include <list> 302SN/A 312SN/A#include "config/full_system.hh" 322SN/A#include "cpu/o3/rename.hh" 332SN/A 342SN/Ausing namespace std; 352SN/A 362SN/Atemplate <class Impl> 372SN/ADefaultRename<Impl>::DefaultRename(Params *params) 382SN/A : iewToRenameDelay(params->iewToRenameDelay), 392SN/A decodeToRenameDelay(params->decodeToRenameDelay), 402665Ssaidi@eecs.umich.edu commitToRenameDelay(params->commitToRenameDelay), 412665Ssaidi@eecs.umich.edu renameWidth(params->renameWidth), 422SN/A commitWidth(params->commitWidth), 432SN/A numThreads(params->numberOfThreads) 448779Sgblack@eecs.umich.edu{ 458779Sgblack@eecs.umich.edu _status = Inactive; 468779Sgblack@eecs.umich.edu 472439SN/A for (int i=0; i< numThreads; i++) { 488779Sgblack@eecs.umich.edu renameStatus[i] = Idle; 498229Snate@binkert.org 506216Snate@binkert.org freeEntries[i].iqEntries = 0; 51146SN/A freeEntries[i].lsqEntries = 0; 52146SN/A freeEntries[i].robEntries = 0; 53146SN/A 54146SN/A stalls[i].iew = false; 55146SN/A stalls[i].commit = false; 566216Snate@binkert.org serializeInst[i] = NULL; 576658Snate@binkert.org 588229Snate@binkert.org instsInProgress[i] = 0; 591717SN/A 608887Sgeoffrey.blake@arm.com emptyROB[i] = true; 618887Sgeoffrey.blake@arm.com 62146SN/A serializeOnNextInst[i] = false; 6310061Sandreas@sandberg.pp.se } 641977SN/A 652683Sktlim@umich.edu // @todo: Make into a parameter. 661717SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 67146SN/A} 682683Sktlim@umich.edu 698232Snate@binkert.orgtemplate <class Impl> 708232Snate@binkert.orgstd::string 718232Snate@binkert.orgDefaultRename<Impl>::name() const 728779Sgblack@eecs.umich.edu{ 733348Sbinkertn@umich.edu return cpu->name() + ".rename"; 746105Ssteve.reinhardt@amd.com} 756216Snate@binkert.org 762036SN/Atemplate <class Impl> 77146SN/Avoid 788817Sgblack@eecs.umich.eduDefaultRename<Impl>::regStats() 798793Sgblack@eecs.umich.edu{ 8056SN/A renameSquashCycles 8156SN/A .name(name() + ".RENAME:SquashCycles") 82695SN/A .desc("Number of cycles rename is squashing") 832901Ssaidi@eecs.umich.edu .prereq(renameSquashCycles); 842SN/A renameIdleCycles 852SN/A .name(name() + ".RENAME:IdleCycles") 862449SN/A .desc("Number of cycles rename is idle") 871355SN/A .prereq(renameIdleCycles); 885529Snate@binkert.org renameBlockCycles 8910061Sandreas@sandberg.pp.se .name(name() + ".RENAME:BlockCycles") 9010061Sandreas@sandberg.pp.se .desc("Number of cycles rename is blocking") 9110537Sandreas.hansson@arm.com .prereq(renameBlockCycles); 9210537Sandreas.hansson@arm.com renameSerializeStallCycles 93224SN/A .name(name() + ".RENAME:serializeStallCycles") 948793Sgblack@eecs.umich.edu .desc("count of cycles rename stalled for serializing inst") 959384SAndreas.Sandberg@arm.com .flags(Stats::total); 969384SAndreas.Sandberg@arm.com renameRunCycles 978793Sgblack@eecs.umich.edu .name(name() + ".RENAME:RunCycles") 988820Sgblack@eecs.umich.edu .desc("Number of cycles rename is running") 999384SAndreas.Sandberg@arm.com .prereq(renameIdleCycles); 1002SN/A renameUnblockCycles 1016029Ssteve.reinhardt@amd.com .name(name() + ".RENAME:UnblockCycles") 1022672Sktlim@umich.edu .desc("Number of cycles rename is unblocking") 1032683Sktlim@umich.edu .prereq(renameUnblockCycles); 1042SN/A renameRenamedInsts 1058733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:RenamedInsts") 1068733Sgeoffrey.blake@arm.com .desc("Number of instructions processed by rename") 1078733Sgeoffrey.blake@arm.com .prereq(renameRenamedInsts); 1088733Sgeoffrey.blake@arm.com renameSquashedInsts 1098733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:SquashedInsts") 1108733Sgeoffrey.blake@arm.com .desc("Number of squashed instructions processed by rename") 1118733Sgeoffrey.blake@arm.com .prereq(renameSquashedInsts); 1128733Sgeoffrey.blake@arm.com renameROBFullEvents 1138733Sgeoffrey.blake@arm.com .name(name() + ".RENAME:ROBFullEvents") 1148733Sgeoffrey.blake@arm.com .desc("Number of times rename has blocked due to ROB full") 1158733Sgeoffrey.blake@arm.com .prereq(renameROBFullEvents); 1162SN/A renameIQFullEvents 117334SN/A .name(name() + ".RENAME:IQFullEvents") 1188834Satgutier@umich.edu .desc("Number of times rename has blocked due to IQ full") 1198834Satgutier@umich.edu .prereq(renameIQFullEvents); 120140SN/A renameLSQFullEvents 121334SN/A .name(name() + ".RENAME:LSQFullEvents") 1222SN/A .desc("Number of times rename has blocked due to LSQ full") 1232SN/A .prereq(renameLSQFullEvents); 1242SN/A renameFullRegistersEvents 1252680Sktlim@umich.edu .name(name() + ".RENAME:FullRegisterEvents") 1264377Sgblack@eecs.umich.edu .desc("Number of times there has been no free registers") 1275169Ssaidi@eecs.umich.edu .prereq(renameFullRegistersEvents); 1284377Sgblack@eecs.umich.edu renameRenamedOperands 1294377Sgblack@eecs.umich.edu .name(name() + ".RENAME:RenamedOperands") 1302SN/A .desc("Number of destination operands rename has renamed") 1312SN/A .prereq(renameRenamedOperands); 1322623SN/A renameRenameLookups 1332SN/A .name(name() + ".RENAME:RenameLookups") 1342SN/A .desc("Number of register rename lookups that rename has made") 1352SN/A .prereq(renameRenameLookups); 136180SN/A renameCommittedMaps 1378737Skoansin.tan@gmail.com .name(name() + ".RENAME:CommittedMaps") 138393SN/A .desc("Number of HB maps that are committed") 139393SN/A .prereq(renameCommittedMaps); 140393SN/A renameUndoneMaps 141393SN/A .name(name() + ".RENAME:UndoneMaps") 142384SN/A .desc("Number of HB maps that are undone due to squashing") 143189SN/A .prereq(renameUndoneMaps); 144189SN/A renamedSerializing 1452623SN/A .name(name() + ".RENAME:serializingInsts") 1462SN/A .desc("count of serializing insts renamed") 147729SN/A .flags(Stats::total) 148334SN/A ; 1492SN/A renamedTempSerializing 1502SN/A .name(name() + ".RENAME:tempSerializingInsts") 1512SN/A .desc("count of temporary serializing insts renamed") 1528834Satgutier@umich.edu .flags(Stats::total) 1538834Satgutier@umich.edu ; 1548834Satgutier@umich.edu renameSkidInsts 1558834Satgutier@umich.edu .name(name() + ".RENAME:skidInsts") 1568834Satgutier@umich.edu .desc("count of insts added to the skid buffer") 1578834Satgutier@umich.edu .flags(Stats::total) 1588834Satgutier@umich.edu ; 1592SN/A} 1602SN/A 1617897Shestness@cs.utexas.edutemplate <class Impl> 1627897Shestness@cs.utexas.eduvoid 1637897Shestness@cs.utexas.eduDefaultRename<Impl>::setCPU(FullCPU *cpu_ptr) 1647897Shestness@cs.utexas.edu{ 1657897Shestness@cs.utexas.edu DPRINTF(Rename, "Setting CPU pointer.\n"); 1667897Shestness@cs.utexas.edu cpu = cpu_ptr; 1677897Shestness@cs.utexas.edu} 1687897Shestness@cs.utexas.edu 1697897Shestness@cs.utexas.edutemplate <class Impl> 1707897Shestness@cs.utexas.eduvoid 1717897Shestness@cs.utexas.eduDefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1727897Shestness@cs.utexas.edu{ 1737897Shestness@cs.utexas.edu DPRINTF(Rename, "Setting time buffer pointer.\n"); 1747897Shestness@cs.utexas.edu timeBuffer = tb_ptr; 1757897Shestness@cs.utexas.edu 1767897Shestness@cs.utexas.edu // Setup wire to read information from time buffer, from IEW stage. 1777897Shestness@cs.utexas.edu fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1787897Shestness@cs.utexas.edu 1797897Shestness@cs.utexas.edu // Setup wire to read infromation from time buffer, from commit stage. 1807897Shestness@cs.utexas.edu fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1817897Shestness@cs.utexas.edu 1827897Shestness@cs.utexas.edu // Setup wire to write information to previous stages. 1837897Shestness@cs.utexas.edu toDecode = timeBuffer->getWire(0); 1847897Shestness@cs.utexas.edu} 1857897Shestness@cs.utexas.edu 1867897Shestness@cs.utexas.edutemplate <class Impl> 1877897Shestness@cs.utexas.eduvoid 1887897Shestness@cs.utexas.eduDefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1897897Shestness@cs.utexas.edu{ 1907897Shestness@cs.utexas.edu DPRINTF(Rename, "Setting rename queue pointer.\n"); 1917897Shestness@cs.utexas.edu renameQueue = rq_ptr; 1927897Shestness@cs.utexas.edu 1937897Shestness@cs.utexas.edu // Setup wire to write information to future stages. 1947897Shestness@cs.utexas.edu toIEW = renameQueue->getWire(0); 1957897Shestness@cs.utexas.edu} 1967897Shestness@cs.utexas.edu 1977897Shestness@cs.utexas.edutemplate <class Impl> 1987897Shestness@cs.utexas.eduvoid 1997897Shestness@cs.utexas.eduDefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2007897Shestness@cs.utexas.edu{ 2017897Shestness@cs.utexas.edu DPRINTF(Rename, "Setting decode queue pointer.\n"); 2027897Shestness@cs.utexas.edu decodeQueue = dq_ptr; 2037897Shestness@cs.utexas.edu 2047897Shestness@cs.utexas.edu // Setup wire to get information from decode. 2057897Shestness@cs.utexas.edu fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2067897Shestness@cs.utexas.edu} 2077897Shestness@cs.utexas.edu 2087897Shestness@cs.utexas.edutemplate <class Impl> 2097897Shestness@cs.utexas.eduvoid 2107897Shestness@cs.utexas.eduDefaultRename<Impl>::initStage() 2119920Syasuko.eckert@amd.com{ 2129920Syasuko.eckert@amd.com // Grab the number of free entries directly from the stages. 2139920Syasuko.eckert@amd.com for (int tid=0; tid < numThreads; tid++) { 2149920Syasuko.eckert@amd.com freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2159920Syasuko.eckert@amd.com freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2169920Syasuko.eckert@amd.com freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2179920Syasuko.eckert@amd.com emptyROB[tid] = true; 2189920Syasuko.eckert@amd.com } 2199920Syasuko.eckert@amd.com} 2209920Syasuko.eckert@amd.com 2219920Syasuko.eckert@amd.comtemplate<class Impl> 2229920Syasuko.eckert@amd.comvoid 2232SN/ADefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr) 2247897Shestness@cs.utexas.edu{ 2257897Shestness@cs.utexas.edu DPRINTF(Rename, "Setting active threads list pointer.\n"); 2267897Shestness@cs.utexas.edu activeThreads = at_ptr; 2277897Shestness@cs.utexas.edu} 2287897Shestness@cs.utexas.edu 2297897Shestness@cs.utexas.edu 2307897Shestness@cs.utexas.edutemplate <class Impl> 2317897Shestness@cs.utexas.eduvoid 2327897Shestness@cs.utexas.eduDefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2337897Shestness@cs.utexas.edu{ 2347897Shestness@cs.utexas.edu DPRINTF(Rename, "Setting rename map pointers.\n"); 2357897Shestness@cs.utexas.edu 2362SN/A for (int i=0; i<numThreads; i++) { 2372SN/A renameMap[i] = &rm_ptr[i]; 2381001SN/A } 2391001SN/A} 2401001SN/A 2411001SN/Atemplate <class Impl> 2421001SN/Avoid 2432SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2442SN/A{ 2452SN/A DPRINTF(Rename, "Setting free list pointer.\n"); 2462SN/A freeList = fl_ptr; 2472SN/A} 2487897Shestness@cs.utexas.edu 2497897Shestness@cs.utexas.edutemplate<class Impl> 2507897Shestness@cs.utexas.eduvoid 2517897Shestness@cs.utexas.eduDefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2527897Shestness@cs.utexas.edu{ 2537897Shestness@cs.utexas.edu DPRINTF(Rename, "Setting scoreboard pointer.\n"); 2547897Shestness@cs.utexas.edu scoreboard = _scoreboard; 2557897Shestness@cs.utexas.edu} 2567897Shestness@cs.utexas.edu 2577897Shestness@cs.utexas.edutemplate <class Impl> 2582SN/Avoid 2592SN/ADefaultRename<Impl>::switchOut() 2602SN/A{ 2612SN/A cpu->signalSwitched(); 2622SN/A} 2632SN/A 2642SN/Atemplate <class Impl> 2652SN/Avoid 2662SN/ADefaultRename<Impl>::doSwitchOut() 2672SN/A{ 2682SN/A for (int i = 0; i < numThreads; i++) { 2692SN/A typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin(); 27010193SCurtis.Dunham@arm.com 27110193SCurtis.Dunham@arm.com while (!historyBuffer[i].empty()) { 27210193SCurtis.Dunham@arm.com assert(hb_it != historyBuffer[i].end()); 27310193SCurtis.Dunham@arm.com 27410193SCurtis.Dunham@arm.com DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 27510193SCurtis.Dunham@arm.com "number %i.\n", i, (*hb_it).instSeqNum); 27610193SCurtis.Dunham@arm.com 27710193SCurtis.Dunham@arm.com // Tell the rename map to set the architected register to the 27810193SCurtis.Dunham@arm.com // previous physical register that it was renamed to. 27910193SCurtis.Dunham@arm.com renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 280385SN/A 2817897Shestness@cs.utexas.edu // Put the renamed physical register back on the free list. 2827897Shestness@cs.utexas.edu freeList->addReg(hb_it->newPhysReg); 28310061Sandreas@sandberg.pp.se 28410061Sandreas@sandberg.pp.se historyBuffer[i].erase(hb_it++); 28510061Sandreas@sandberg.pp.se } 28610061Sandreas@sandberg.pp.se insts[i].clear(); 28710061Sandreas@sandberg.pp.se skidBuffer[i].clear(); 28810061Sandreas@sandberg.pp.se } 28910061Sandreas@sandberg.pp.se} 29010061Sandreas@sandberg.pp.se 29110061Sandreas@sandberg.pp.setemplate <class Impl> 29210061Sandreas@sandberg.pp.sevoid 29310061Sandreas@sandberg.pp.seDefaultRename<Impl>::takeOverFrom() 29410061Sandreas@sandberg.pp.se{ 29510061Sandreas@sandberg.pp.se _status = Inactive; 29610061Sandreas@sandberg.pp.se initStage(); 29710061Sandreas@sandberg.pp.se 2982SN/A // Reset all state prior to taking over from the other CPU. 2992SN/A for (int i=0; i< numThreads; i++) { 3002SN/A renameStatus[i] = Idle; 3012623SN/A 302334SN/A stalls[i].iew = false; 3032361SN/A stalls[i].commit = false; 3045496Ssaidi@eecs.umich.edu serializeInst[i] = NULL; 305334SN/A 306334SN/A instsInProgress[i] = 0; 307334SN/A 30810905Sandreas.sandberg@arm.com emptyROB[i] = true; 3092SN/A 3109448SAndreas.Sandberg@ARM.com serializeOnNextInst[i] = false; 3119448SAndreas.Sandberg@ARM.com } 3129448SAndreas.Sandberg@ARM.com} 31310905Sandreas.sandberg@arm.com 3142SN/Atemplate <class Impl> 3152SN/Avoid 3162SN/ADefaultRename<Impl>::squash(unsigned tid) 31710905Sandreas.sandberg@arm.com{ 3182SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3199448SAndreas.Sandberg@ARM.com 3209448SAndreas.Sandberg@ARM.com // Clear the stall signal if rename was blocked or unblocking before. 32110905Sandreas.sandberg@arm.com // If it still needs to block, the blocking should happen the next 3222SN/A // cycle and there should be space to hold everything due to the squash. 3232SN/A if (renameStatus[tid] == Blocked || 3242SN/A renameStatus[tid] == Unblocking || 3256221Snate@binkert.org renameStatus[tid] == SerializeStall) { 3262SN/A#if 0 3272SN/A // In syscall emulation, we can have both a block and a squash due 3282SN/A // to a syscall in the same cycle. This would cause both signals to 3292SN/A // be high. This shouldn't happen in full system. 3302623SN/A if (toDecode->renameBlock[tid]) { 3312SN/A toDecode->renameBlock[tid] = 0; 3322680Sktlim@umich.edu } else { 3332SN/A toDecode->renameUnblock[tid] = 1; 3342SN/A } 3352SN/A#else 3365807Snate@binkert.org toDecode->renameUnblock[tid] = 1; 3372SN/A#endif 33810529Smorr@cs.wisc.edu serializeInst[tid] = NULL; 33910529Smorr@cs.wisc.edu } 3405807Snate@binkert.org 3415807Snate@binkert.org // Set the status to Squashing. 3422SN/A renameStatus[tid] = Squashing; 3435807Snate@binkert.org 3445807Snate@binkert.org // Squash any instructions from decode. 3452SN/A unsigned squashCount = 0; 3462SN/A 3472SN/A for (int i=0; i<fromDecode->size; i++) { 3482623SN/A if (fromDecode->insts[i]->threadNumber == tid) { 3492SN/A fromDecode->insts[i]->squashed = true; 3505704Snate@binkert.org wroteToTimeBuffer = true; 3515647Sgblack@eecs.umich.edu squashCount++; 3522SN/A } 3533520Sgblack@eecs.umich.edu } 3547338SAli.Saidi@ARM.com 3555647Sgblack@eecs.umich.edu insts[tid].clear(); 3563520Sgblack@eecs.umich.edu 3579023Sgblack@eecs.umich.edu // Clear the skid buffer in case it has any data in it. 3582SN/A skidBuffer[tid].clear(); 3592SN/A 3602623SN/A doSquash(tid); 3612SN/A} 3622623SN/A 3635894Sgblack@eecs.umich.edutemplate <class Impl> 3642662Sstever@eecs.umich.eduvoid 3652623SN/ADefaultRename<Impl>::tick() 3667720Sgblack@eecs.umich.edu{ 3674495Sacolyte@umich.edu wroteToTimeBuffer = false; 3682623SN/A 3697720Sgblack@eecs.umich.edu blockThisCycle = false; 3702623SN/A 3717720Sgblack@eecs.umich.edu bool status_change = false; 3728832SAli.Saidi@ARM.com 3738832SAli.Saidi@ARM.com toIEWIndex = 0; 3742623SN/A 3752623SN/A sortInsts(); 3762623SN/A 3772623SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 3782623SN/A 3792623SN/A // Check stall and squash signals. 3802SN/A while (threads != (*activeThreads).end()) { 3812683Sktlim@umich.edu unsigned tid = *threads++; 3822427SN/A 3832683Sktlim@umich.edu DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3842427SN/A 3852SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 3862623SN/A 3872623SN/A rename(status_change, tid); 3887897Shestness@cs.utexas.edu } 3892SN/A 3902623SN/A if (status_change) { 3912623SN/A updateStatus(); 3924377Sgblack@eecs.umich.edu } 3937720Sgblack@eecs.umich.edu 3944377Sgblack@eecs.umich.edu if (wroteToTimeBuffer) { 3957720Sgblack@eecs.umich.edu DPRINTF(Activity, "Activity this cycle.\n"); 3965665Sgblack@eecs.umich.edu cpu->activityThisCycle(); 3977720Sgblack@eecs.umich.edu } 3987720Sgblack@eecs.umich.edu 3995665Sgblack@eecs.umich.edu threads = (*activeThreads).begin(); 4005665Sgblack@eecs.umich.edu 4014181Sgblack@eecs.umich.edu while (threads != (*activeThreads).end()) { 4024181Sgblack@eecs.umich.edu unsigned tid = *threads++; 4039023Sgblack@eecs.umich.edu 4049023Sgblack@eecs.umich.edu // If we committed this cycle then doneSeqNum will be > 0 4054181Sgblack@eecs.umich.edu if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4064182Sgblack@eecs.umich.edu !fromCommit->commitInfo[tid].squash && 4077720Sgblack@eecs.umich.edu renameStatus[tid] != Squashing) { 4089023Sgblack@eecs.umich.edu 4099023Sgblack@eecs.umich.edu removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4104593Sgblack@eecs.umich.edu tid); 4119023Sgblack@eecs.umich.edu } 4124377Sgblack@eecs.umich.edu } 4139023Sgblack@eecs.umich.edu 4144377Sgblack@eecs.umich.edu // @todo: make into updateProgress function 4159023Sgblack@eecs.umich.edu for (int tid=0; tid < numThreads; tid++) { 4169023Sgblack@eecs.umich.edu instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4174377Sgblack@eecs.umich.edu 4187720Sgblack@eecs.umich.edu assert(instsInProgress[tid] >=0); 4194377Sgblack@eecs.umich.edu } 4204377Sgblack@eecs.umich.edu 4214377Sgblack@eecs.umich.edu} 4224377Sgblack@eecs.umich.edu 4234181Sgblack@eecs.umich.edutemplate<class Impl> 4244181Sgblack@eecs.umich.eduvoid 4254181Sgblack@eecs.umich.eduDefaultRename<Impl>::rename(bool &status_change, unsigned tid) 4264539Sgblack@eecs.umich.edu{ 4273276Sgblack@eecs.umich.edu // If status is Running or idle, 4287720Sgblack@eecs.umich.edu // call renameInsts() 4293280Sgblack@eecs.umich.edu // If status is Unblocking, 4303280Sgblack@eecs.umich.edu // buffer any instructions coming from decode 4313276Sgblack@eecs.umich.edu // continue trying to empty skid buffer 4323276Sgblack@eecs.umich.edu // check if stall conditions have passed 4333276Sgblack@eecs.umich.edu 4347720Sgblack@eecs.umich.edu if (renameStatus[tid] == Blocked) { 4353276Sgblack@eecs.umich.edu ++renameBlockCycles; 4363276Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Squashing) { 4374181Sgblack@eecs.umich.edu ++renameSquashCycles; 4388955Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 4394522Ssaidi@eecs.umich.edu ++renameSerializeStallCycles; 4407823Ssteve.reinhardt@amd.com } 4417720Sgblack@eecs.umich.edu 4422470SN/A if (renameStatus[tid] == Running || 4438955Sgblack@eecs.umich.edu renameStatus[tid] == Idle) { 4444181Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4454522Ssaidi@eecs.umich.edu "stage.\n", tid); 4464181Sgblack@eecs.umich.edu 44710061Sandreas@sandberg.pp.se renameInsts(tid); 44810061Sandreas@sandberg.pp.se } else if (renameStatus[tid] == Unblocking) { 44910061Sandreas@sandberg.pp.se renameInsts(tid); 45010061Sandreas@sandberg.pp.se 45110061Sandreas@sandberg.pp.se if (validInsts()) { 45210061Sandreas@sandberg.pp.se // Add the current inputs to the skid buffer so they can be 45310061Sandreas@sandberg.pp.se // reprocessed when this stage unblocks. 45410061Sandreas@sandberg.pp.se skidInsert(tid); 45510061Sandreas@sandberg.pp.se } 45610061Sandreas@sandberg.pp.se 45710061Sandreas@sandberg.pp.se // If we switched over to blocking, then there's a potential for 45810061Sandreas@sandberg.pp.se // an overall status change. 45910061Sandreas@sandberg.pp.se status_change = unblock(tid) || status_change || blockThisCycle; 4602623SN/A } 4612623SN/A} 4622623SN/A 4632623SN/Atemplate <class Impl> 4642623SN/Avoid 4657720Sgblack@eecs.umich.eduDefaultRename<Impl>::renameInsts(unsigned tid) 4667720Sgblack@eecs.umich.edu{ 4677720Sgblack@eecs.umich.edu // Instructions can be either in the skid buffer or the queue of 4687720Sgblack@eecs.umich.edu // instructions coming from decode, depending on the status. 4698780Sgblack@eecs.umich.edu int insts_available = renameStatus[tid] == Unblocking ? 4703577Sgblack@eecs.umich.edu skidBuffer[tid].size() : insts[tid].size(); 4717720Sgblack@eecs.umich.edu 4725086Sgblack@eecs.umich.edu // Check the decode queue to see if instructions are available. 4732623SN/A // If there are no available instructions to rename, then do nothing. 4742683Sktlim@umich.edu if (insts_available == 0) { 4752623SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4762SN/A tid); 4772623SN/A // Should I change status to idle? 4782623SN/A ++renameIdleCycles; 4792SN/A return; 4802SN/A } else if (renameStatus[tid] == Unblocking) { 4812623SN/A ++renameUnblockCycles; 4822623SN/A } else if (renameStatus[tid] == Running) { 4832623SN/A ++renameRunCycles; 4842623SN/A } 4852SN/A 4865953Ssaidi@eecs.umich.edu DynInstPtr inst; 4877720Sgblack@eecs.umich.edu 4885953Ssaidi@eecs.umich.edu // Will have to do a different calculation for the number of free 4895953Ssaidi@eecs.umich.edu // entries. 49010061Sandreas@sandberg.pp.se int free_rob_entries = calcFreeROBEntries(tid); 49110061Sandreas@sandberg.pp.se int free_iq_entries = calcFreeIQEntries(tid); 49210061Sandreas@sandberg.pp.se int free_lsq_entries = calcFreeLSQEntries(tid); 49310061Sandreas@sandberg.pp.se int min_free_entries = free_rob_entries; 4947897Shestness@cs.utexas.edu 4957897Shestness@cs.utexas.edu FullSource source = ROB; 4967897Shestness@cs.utexas.edu 4977897Shestness@cs.utexas.edu if (free_iq_entries < min_free_entries) { 4987897Shestness@cs.utexas.edu min_free_entries = free_iq_entries; 4997897Shestness@cs.utexas.edu source = IQ; 5007897Shestness@cs.utexas.edu } 5017897Shestness@cs.utexas.edu 5027897Shestness@cs.utexas.edu if (free_lsq_entries < min_free_entries) { 5037897Shestness@cs.utexas.edu min_free_entries = free_lsq_entries; 5047897Shestness@cs.utexas.edu source = LSQ; 5057897Shestness@cs.utexas.edu } 5067897Shestness@cs.utexas.edu 5077897Shestness@cs.utexas.edu // Check if there's any space left. 5087897Shestness@cs.utexas.edu if (min_free_entries <= 0) { 5097897Shestness@cs.utexas.edu DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5107897Shestness@cs.utexas.edu "entries.\n" 5117897Shestness@cs.utexas.edu "ROB has %i free entries.\n" 5127897Shestness@cs.utexas.edu "IQ has %i free entries.\n" 5137897Shestness@cs.utexas.edu "LSQ has %i free entries.\n", 5147897Shestness@cs.utexas.edu tid, 5157897Shestness@cs.utexas.edu free_rob_entries, 5167897Shestness@cs.utexas.edu free_iq_entries, 5177897Shestness@cs.utexas.edu free_lsq_entries); 5187897Shestness@cs.utexas.edu 5197897Shestness@cs.utexas.edu blockThisCycle = true; 5207897Shestness@cs.utexas.edu 5217897Shestness@cs.utexas.edu block(tid); 5227897Shestness@cs.utexas.edu 5237897Shestness@cs.utexas.edu incrFullStat(source); 5247897Shestness@cs.utexas.edu 5257897Shestness@cs.utexas.edu return; 5267897Shestness@cs.utexas.edu } else if (min_free_entries < insts_available) { 52710193SCurtis.Dunham@arm.com DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 52810193SCurtis.Dunham@arm.com "%i insts available, but only %i insts can be " 5298780Sgblack@eecs.umich.edu "renamed due to ROB/IQ/LSQ limits.\n", 5308780Sgblack@eecs.umich.edu tid, insts_available, min_free_entries); 5312644Sstever@eecs.umich.edu 5322644Sstever@eecs.umich.edu insts_available = min_free_entries; 5334046Sbinkertn@umich.edu 5344046Sbinkertn@umich.edu blockThisCycle = true; 5354046Sbinkertn@umich.edu 5362644Sstever@eecs.umich.edu incrFullStat(source); 53710464SAndreas.Sandberg@ARM.com } 53810464SAndreas.Sandberg@ARM.com 53910464SAndreas.Sandberg@ARM.com InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5402623SN/A skidBuffer[tid] : insts[tid]; 5412SN/A 5422623SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 54310379Sandreas.hansson@arm.com "send iew.\n", tid, insts_available); 5442623SN/A 54510061Sandreas@sandberg.pp.se DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 54610061Sandreas@sandberg.pp.se "dispatched to IQ last cycle.\n", 5474377Sgblack@eecs.umich.edu tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5484377Sgblack@eecs.umich.edu 5492090SN/A // Handle serializing the next instruction if necessary. 5503905Ssaidi@eecs.umich.edu if (serializeOnNextInst[tid]) { 5517678Sgblack@eecs.umich.edu if (emptyROB[tid] && instsInProgress[tid] == 0) { 5529023Sgblack@eecs.umich.edu // ROB already empty; no need to serialize. 5534377Sgblack@eecs.umich.edu serializeOnNextInst[tid] = false; 5547720Sgblack@eecs.umich.edu } else if (!insts_to_rename.empty()) { 5557720Sgblack@eecs.umich.edu insts_to_rename.front()->setSerializeBefore(); 5567720Sgblack@eecs.umich.edu } 5577720Sgblack@eecs.umich.edu } 5587720Sgblack@eecs.umich.edu 5597720Sgblack@eecs.umich.edu int renamed_insts = 0; 5603276Sgblack@eecs.umich.edu 5612SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 56210061Sandreas@sandberg.pp.se DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 56310061Sandreas@sandberg.pp.se 56410061Sandreas@sandberg.pp.se assert(!insts_to_rename.empty()); 56510061Sandreas@sandberg.pp.se 56610061Sandreas@sandberg.pp.se inst = insts_to_rename.front(); 56710061Sandreas@sandberg.pp.se 56810061Sandreas@sandberg.pp.se insts_to_rename.pop_front(); 56910061Sandreas@sandberg.pp.se 57010061Sandreas@sandberg.pp.se if (renameStatus[tid] == Unblocking) { 57110061Sandreas@sandberg.pp.se DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 57210061Sandreas@sandberg.pp.se "skidBuffer\n", 57310061Sandreas@sandberg.pp.se tid, inst->seqNum, inst->readPC()); 57410061Sandreas@sandberg.pp.se } 57510061Sandreas@sandberg.pp.se 57610061Sandreas@sandberg.pp.se if (inst->isSquashed()) { 57710061Sandreas@sandberg.pp.se DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 57810061Sandreas@sandberg.pp.se "squashed, skipping.\n", 5792SN/A tid, inst->seqNum, inst->threadNumber,inst->readPC()); 5802SN/A 5819461Snilay@cs.wisc.edu ++renameSquashedInsts; 5829461Snilay@cs.wisc.edu 5839461Snilay@cs.wisc.edu // Decrement how many instructions are available. 5849461Snilay@cs.wisc.edu --insts_available; 5859461Snilay@cs.wisc.edu 5869461Snilay@cs.wisc.edu continue; 587 } 588 589 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 590 "PC %#x.\n", 591 tid, inst->seqNum, inst->readPC()); 592 593 // Handle serializeAfter/serializeBefore instructions. 594 // serializeAfter marks the next instruction as serializeBefore. 595 // serializeBefore makes the instruction wait in rename until the ROB 596 // is empty. 597 if (inst->isSerializeBefore() && !inst->isSerializeHandled()) { 598 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 599 600 if (!inst->isTempSerializeBefore()) { 601 renamedSerializing++; 602 inst->setSerializeHandled(); 603 } else { 604 renamedTempSerializing++; 605 } 606 607 // Change status over to SerializeStall so that other stages know 608 // what this is blocked on. 609 renameStatus[tid] = SerializeStall; 610 611 serializeInst[tid] = inst; 612 613 blockThisCycle = true; 614 615 break; 616 } else if (inst->isSerializeAfter() && !inst->isSerializeHandled()) { 617 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 618 619 renamedSerializing++; 620 621 inst->setSerializeHandled(); 622 623 serializeAfter(insts_to_rename, tid); 624 } 625 626 // Check here to make sure there are enough destination registers 627 // to rename to. Otherwise block. 628 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 629 DPRINTF(Rename, "Blocking due to lack of free " 630 "physical registers to rename to.\n"); 631 blockThisCycle = true; 632 633 ++renameFullRegistersEvents; 634 635 break; 636 } 637 638 renameSrcRegs(inst, inst->threadNumber); 639 640 renameDestRegs(inst, inst->threadNumber); 641 642 ++renamed_insts; 643 644 // Put instruction in rename queue. 645 toIEW->insts[toIEWIndex] = inst; 646 ++(toIEW->size); 647 648 // Increment which instruction we're on. 649 ++toIEWIndex; 650 651 // Decrement how many instructions are available. 652 --insts_available; 653 } 654 655 instsInProgress[tid] += renamed_insts; 656 renameRenamedInsts += renamed_insts; 657 658 // If we wrote to the time buffer, record this. 659 if (toIEWIndex) { 660 wroteToTimeBuffer = true; 661 } 662 663 // Check if there's any instructions left that haven't yet been renamed. 664 // If so then block. 665 if (insts_available) { 666 blockThisCycle = true; 667 } 668 669 if (blockThisCycle) { 670 block(tid); 671 toDecode->renameUnblock[tid] = false; 672 } 673} 674 675template<class Impl> 676void 677DefaultRename<Impl>::skidInsert(unsigned tid) 678{ 679 DynInstPtr inst = NULL; 680 681 while (!insts[tid].empty()) { 682 inst = insts[tid].front(); 683 684 insts[tid].pop_front(); 685 686 assert(tid == inst->threadNumber); 687 688 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 689 "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 690 691 ++renameSkidInsts; 692 693 skidBuffer[tid].push_back(inst); 694 } 695 696 if (skidBuffer[tid].size() > skidBufferMax) 697 panic("Skidbuffer Exceeded Max Size"); 698} 699 700template <class Impl> 701void 702DefaultRename<Impl>::sortInsts() 703{ 704 int insts_from_decode = fromDecode->size; 705#ifdef DEBUG 706 for (int i=0; i < numThreads; i++) 707 assert(insts[i].empty()); 708#endif 709 for (int i = 0; i < insts_from_decode; ++i) { 710 DynInstPtr inst = fromDecode->insts[i]; 711 insts[inst->threadNumber].push_back(inst); 712 } 713} 714 715template<class Impl> 716bool 717DefaultRename<Impl>::skidsEmpty() 718{ 719 list<unsigned>::iterator threads = (*activeThreads).begin(); 720 721 while (threads != (*activeThreads).end()) { 722 if (!skidBuffer[*threads++].empty()) 723 return false; 724 } 725 726 return true; 727} 728 729template<class Impl> 730void 731DefaultRename<Impl>::updateStatus() 732{ 733 bool any_unblocking = false; 734 735 list<unsigned>::iterator threads = (*activeThreads).begin(); 736 737 threads = (*activeThreads).begin(); 738 739 while (threads != (*activeThreads).end()) { 740 unsigned tid = *threads++; 741 742 if (renameStatus[tid] == Unblocking) { 743 any_unblocking = true; 744 break; 745 } 746 } 747 748 // Rename will have activity if it's unblocking. 749 if (any_unblocking) { 750 if (_status == Inactive) { 751 _status = Active; 752 753 DPRINTF(Activity, "Activating stage.\n"); 754 755 cpu->activateStage(FullCPU::RenameIdx); 756 } 757 } else { 758 // If it's not unblocking, then rename will not have any internal 759 // activity. Switch it to inactive. 760 if (_status == Active) { 761 _status = Inactive; 762 DPRINTF(Activity, "Deactivating stage.\n"); 763 764 cpu->deactivateStage(FullCPU::RenameIdx); 765 } 766 } 767} 768 769template <class Impl> 770bool 771DefaultRename<Impl>::block(unsigned tid) 772{ 773 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 774 775 // Add the current inputs onto the skid buffer, so they can be 776 // reprocessed when this stage unblocks. 777 skidInsert(tid); 778 779 // Only signal backwards to block if the previous stages do not think 780 // rename is already blocked. 781 if (renameStatus[tid] != Blocked) { 782 if (renameStatus[tid] != Unblocking) { 783 toDecode->renameBlock[tid] = true; 784 toDecode->renameUnblock[tid] = false; 785 wroteToTimeBuffer = true; 786 } 787 788 // Rename can not go from SerializeStall to Blocked, otherwise 789 // it would not know to complete the serialize stall. 790 if (renameStatus[tid] != SerializeStall) { 791 // Set status to Blocked. 792 renameStatus[tid] = Blocked; 793 return true; 794 } 795 } 796 797 return false; 798} 799 800template <class Impl> 801bool 802DefaultRename<Impl>::unblock(unsigned tid) 803{ 804 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 805 806 // Rename is done unblocking if the skid buffer is empty. 807 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 808 809 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 810 811 toDecode->renameUnblock[tid] = true; 812 wroteToTimeBuffer = true; 813 814 renameStatus[tid] = Running; 815 return true; 816 } 817 818 return false; 819} 820 821template <class Impl> 822void 823DefaultRename<Impl>::doSquash(unsigned tid) 824{ 825 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin(); 826 827 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 828 829 // After a syscall squashes everything, the history buffer may be empty 830 // but the ROB may still be squashing instructions. 831 if (historyBuffer[tid].empty()) { 832 return; 833 } 834 835 // Go through the most recent instructions, undoing the mappings 836 // they did and freeing up the registers. 837 while (!historyBuffer[tid].empty() && 838 (*hb_it).instSeqNum > squashed_seq_num) { 839 assert(hb_it != historyBuffer[tid].end()); 840 841 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 842 "number %i.\n", tid, (*hb_it).instSeqNum); 843 844 // Tell the rename map to set the architected register to the 845 // previous physical register that it was renamed to. 846 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 847 848 // Put the renamed physical register back on the free list. 849 freeList->addReg(hb_it->newPhysReg); 850 851 historyBuffer[tid].erase(hb_it++); 852 853 ++renameUndoneMaps; 854 } 855} 856 857template<class Impl> 858void 859DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 860{ 861 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 862 "history buffer %u (size=%i), until [sn:%lli].\n", 863 tid, tid, historyBuffer[tid].size(), inst_seq_num); 864 865 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end(); 866 867 --hb_it; 868 869 if (historyBuffer[tid].empty()) { 870 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 871 return; 872 } else if (hb_it->instSeqNum > inst_seq_num) { 873 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 874 "that a syscall happened recently.\n", tid); 875 return; 876 } 877 878 // Commit all the renames up until (and including) the committed sequence 879 // number. Some or even all of the committed instructions may not have 880 // rename histories if they did not have destination registers that were 881 // renamed. 882 while (!historyBuffer[tid].empty() && 883 hb_it != historyBuffer[tid].end() && 884 (*hb_it).instSeqNum <= inst_seq_num) { 885 886 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 887 "[sn:%lli].\n", 888 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 889 890 freeList->addReg((*hb_it).prevPhysReg); 891 ++renameCommittedMaps; 892 893 historyBuffer[tid].erase(hb_it--); 894 } 895} 896 897template <class Impl> 898inline void 899DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 900{ 901 assert(renameMap[tid] != 0); 902 903 unsigned num_src_regs = inst->numSrcRegs(); 904 905 // Get the architectual register numbers from the source and 906 // destination operands, and redirect them to the right register. 907 // Will need to mark dependencies though. 908 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 909 RegIndex src_reg = inst->srcRegIdx(src_idx); 910 911 // Look up the source registers to get the phys. register they've 912 // been renamed to, and set the sources to those registers. 913 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg); 914 915 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 916 "physical reg %i.\n", tid, (int)src_reg, 917 (int)renamed_reg); 918 919 inst->renameSrcReg(src_idx, renamed_reg); 920 921 // See if the register is ready or not. 922 if (scoreboard->getReg(renamed_reg) == true) { 923 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 924 925 inst->markSrcRegReady(src_idx); 926 } 927 928 ++renameRenameLookups; 929 } 930} 931 932template <class Impl> 933inline void 934DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 935{ 936 typename RenameMap::RenameInfo rename_result; 937 938 unsigned num_dest_regs = inst->numDestRegs(); 939 940 // Rename the destination registers. 941 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 942 RegIndex dest_reg = inst->destRegIdx(dest_idx); 943 944 // Get the physical register that the destination will be 945 // renamed to. 946 rename_result = renameMap[tid]->rename(dest_reg); 947 948 //Mark Scoreboard entry as not ready 949 scoreboard->unsetReg(rename_result.first); 950 951 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 952 "reg %i.\n", tid, (int)dest_reg, 953 (int)rename_result.first); 954 955 // Record the rename information so that a history can be kept. 956 RenameHistory hb_entry(inst->seqNum, dest_reg, 957 rename_result.first, 958 rename_result.second); 959 960 historyBuffer[tid].push_front(hb_entry); 961 962 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, " 963 "[sn:%lli].\n",tid, 964 (*historyBuffer[tid].begin()).instSeqNum); 965 966 // Tell the instruction to rename the appropriate destination 967 // register (dest_idx) to the new physical register 968 // (rename_result.first), and record the previous physical 969 // register that the same logical register was renamed to 970 // (rename_result.second). 971 inst->renameDestReg(dest_idx, 972 rename_result.first, 973 rename_result.second); 974 975 ++renameRenamedOperands; 976 } 977} 978 979template <class Impl> 980inline int 981DefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 982{ 983 int num_free = freeEntries[tid].robEntries - 984 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 985 986 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 987 988 return num_free; 989} 990 991template <class Impl> 992inline int 993DefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 994{ 995 int num_free = freeEntries[tid].iqEntries - 996 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 997 998 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 999 1000 return num_free; 1001} 1002 1003template <class Impl> 1004inline int 1005DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 1006{ 1007 int num_free = freeEntries[tid].lsqEntries - 1008 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 1009 1010 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1011 1012 return num_free; 1013} 1014 1015template <class Impl> 1016unsigned 1017DefaultRename<Impl>::validInsts() 1018{ 1019 unsigned inst_count = 0; 1020 1021 for (int i=0; i<fromDecode->size; i++) { 1022 if (!fromDecode->insts[i]->squashed) 1023 inst_count++; 1024 } 1025 1026 return inst_count; 1027} 1028 1029template <class Impl> 1030void 1031DefaultRename<Impl>::readStallSignals(unsigned tid) 1032{ 1033 if (fromIEW->iewBlock[tid]) { 1034 stalls[tid].iew = true; 1035 } 1036 1037 if (fromIEW->iewUnblock[tid]) { 1038 assert(stalls[tid].iew); 1039 stalls[tid].iew = false; 1040 } 1041 1042 if (fromCommit->commitBlock[tid]) { 1043 stalls[tid].commit = true; 1044 } 1045 1046 if (fromCommit->commitUnblock[tid]) { 1047 assert(stalls[tid].commit); 1048 stalls[tid].commit = false; 1049 } 1050} 1051 1052template <class Impl> 1053bool 1054DefaultRename<Impl>::checkStall(unsigned tid) 1055{ 1056 bool ret_val = false; 1057 1058 if (stalls[tid].iew) { 1059 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1060 ret_val = true; 1061 } else if (stalls[tid].commit) { 1062 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1063 ret_val = true; 1064 } else if (calcFreeROBEntries(tid) <= 0) { 1065 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1066 ret_val = true; 1067 } else if (calcFreeIQEntries(tid) <= 0) { 1068 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1069 ret_val = true; 1070 } else if (calcFreeLSQEntries(tid) <= 0) { 1071 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1072 ret_val = true; 1073 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1074 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1075 ret_val = true; 1076 } else if (renameStatus[tid] == SerializeStall && 1077 (!emptyROB[tid] || instsInProgress[tid])) { 1078 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1079 "empty.\n", 1080 tid); 1081 ret_val = true; 1082 } 1083 1084 return ret_val; 1085} 1086 1087template <class Impl> 1088void 1089DefaultRename<Impl>::readFreeEntries(unsigned tid) 1090{ 1091 bool updated = false; 1092 if (fromIEW->iewInfo[tid].usedIQ) { 1093 freeEntries[tid].iqEntries = 1094 fromIEW->iewInfo[tid].freeIQEntries; 1095 updated = true; 1096 } 1097 1098 if (fromIEW->iewInfo[tid].usedLSQ) { 1099 freeEntries[tid].lsqEntries = 1100 fromIEW->iewInfo[tid].freeLSQEntries; 1101 updated = true; 1102 } 1103 1104 if (fromCommit->commitInfo[tid].usedROB) { 1105 freeEntries[tid].robEntries = 1106 fromCommit->commitInfo[tid].freeROBEntries; 1107 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1108 updated = true; 1109 } 1110 1111 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1112 tid, 1113 freeEntries[tid].iqEntries, 1114 freeEntries[tid].robEntries, 1115 freeEntries[tid].lsqEntries); 1116 1117 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1118 tid, instsInProgress[tid]); 1119} 1120 1121template <class Impl> 1122bool 1123DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 1124{ 1125 // Check if there's a squash signal, squash if there is 1126 // Check stall signals, block if necessary. 1127 // If status was blocked 1128 // check if stall conditions have passed 1129 // if so then go to unblocking 1130 // If status was Squashing 1131 // check if squashing is not high. Switch to running this cycle. 1132 // If status was serialize stall 1133 // check if ROB is empty and no insts are in flight to the ROB 1134 1135 readFreeEntries(tid); 1136 readStallSignals(tid); 1137 1138 if (fromCommit->commitInfo[tid].squash) { 1139 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1140 "commit.\n", tid); 1141 1142 squash(tid); 1143 1144 return true; 1145 } 1146 1147 if (fromCommit->commitInfo[tid].robSquashing) { 1148 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1149 1150 renameStatus[tid] = Squashing; 1151 1152 return true; 1153 } 1154 1155 if (checkStall(tid)) { 1156 return block(tid); 1157 } 1158 1159 if (renameStatus[tid] == Blocked) { 1160 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1161 tid); 1162 1163 renameStatus[tid] = Unblocking; 1164 1165 unblock(tid); 1166 1167 return true; 1168 } 1169 1170 if (renameStatus[tid] == Squashing) { 1171 // Switch status to running if rename isn't being told to block or 1172 // squash this cycle. 1173 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1174 tid); 1175 1176 renameStatus[tid] = Running; 1177 1178 return false; 1179 } 1180 1181 if (renameStatus[tid] == SerializeStall) { 1182 // Stall ends once the ROB is free. 1183 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1184 "unblocking.\n", tid); 1185 1186 DynInstPtr serial_inst = serializeInst[tid]; 1187 1188 renameStatus[tid] = Unblocking; 1189 1190 unblock(tid); 1191 1192 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1193 "PC %#x.\n", 1194 tid, serial_inst->seqNum, serial_inst->readPC()); 1195 1196 // Put instruction into queue here. 1197 serial_inst->clearSerializeBefore(); 1198 1199 if (!skidBuffer[tid].empty()) { 1200 skidBuffer[tid].push_front(serial_inst); 1201 } else { 1202 insts[tid].push_front(serial_inst); 1203 } 1204 1205 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1206 " Adding to front of list.", tid); 1207 1208 serializeInst[tid] = NULL; 1209 1210 return true; 1211 } 1212 1213 // If we've reached this point, we have not gotten any signals that 1214 // cause rename to change its status. Rename remains the same as before. 1215 return false; 1216} 1217 1218template<class Impl> 1219void 1220DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 1221 unsigned tid) 1222{ 1223 if (inst_list.empty()) { 1224 // Mark a bit to say that I must serialize on the next instruction. 1225 serializeOnNextInst[tid] = true; 1226 return; 1227 } 1228 1229 // Set the next instruction as serializing. 1230 inst_list.front()->setSerializeBefore(); 1231} 1232 1233template <class Impl> 1234inline void 1235DefaultRename<Impl>::incrFullStat(const FullSource &source) 1236{ 1237 switch (source) { 1238 case ROB: 1239 ++renameROBFullEvents; 1240 break; 1241 case IQ: 1242 ++renameIQFullEvents; 1243 break; 1244 case LSQ: 1245 ++renameLSQFullEvents; 1246 break; 1247 default: 1248 panic("Rename full stall stat should be incremented for a reason!"); 1249 break; 1250 } 1251} 1252 1253template <class Impl> 1254void 1255DefaultRename<Impl>::dumpHistory() 1256{ 1257 typename list<RenameHistory>::iterator buf_it; 1258 1259 for (int i = 0; i < numThreads; i++) { 1260 1261 buf_it = historyBuffer[i].begin(); 1262 1263 while (buf_it != historyBuffer[i].end()) { 1264 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1265 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1266 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1267 1268 buf_it++; 1269 } 1270 } 1271} 1272