rename_impl.hh revision 13641 
1/*
2 * Copyright (c) 2010-2012, 2014-2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 */
44
45#ifndef __CPU_O3_RENAME_IMPL_HH__
46#define __CPU_O3_RENAME_IMPL_HH__
47
48#include <list>
49
50#include "arch/isa_traits.hh"
51#include "arch/registers.hh"
52#include "config/the_isa.hh"
53#include "cpu/o3/rename.hh"
54#include "cpu/reg_class.hh"
55#include "debug/Activity.hh"
56#include "debug/Rename.hh"
57#include "debug/O3PipeView.hh"
58#include "params/DerivO3CPU.hh"
59
60using namespace std;
61
62template <class Impl>
63DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
64    : cpu(_cpu),
65      iewToRenameDelay(params->iewToRenameDelay),
66      decodeToRenameDelay(params->decodeToRenameDelay),
67      commitToRenameDelay(params->commitToRenameDelay),
68      renameWidth(params->renameWidth),
69      commitWidth(params->commitWidth),
70      numThreads(params->numThreads)
71{
72    if (renameWidth > Impl::MaxWidth)
73        fatal("renameWidth (%d) is larger than compiled limit (%d),\n"
74             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
75             renameWidth, static_cast<int>(Impl::MaxWidth));
76
77    // @todo: Make into a parameter.
78    skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth;
79    for (uint32_t tid = 0; tid < Impl::MaxThreads; tid++) {
80        renameStatus[tid] = Idle;
81        renameMap[tid] = nullptr;
82        instsInProgress[tid] = 0;
83        loadsInProgress[tid] = 0;
84        storesInProgress[tid] = 0;
85        freeEntries[tid] = {0, 0, 0, 0};
86        emptyROB[tid] = true;
87        stalls[tid] = {false, false};
88        serializeInst[tid] = nullptr;
89        serializeOnNextInst[tid] = false;
90    }
91}
92
93template <class Impl>
94std::string
95DefaultRename<Impl>::name() const
96{
97    return cpu->name() + ".rename";
98}
99
100template <class Impl>
101void
102DefaultRename<Impl>::regStats()
103{
104    renameSquashCycles
105        .name(name() + ".SquashCycles")
106        .desc("Number of cycles rename is squashing")
107        .prereq(renameSquashCycles);
108    renameIdleCycles
109        .name(name() + ".IdleCycles")
110        .desc("Number of cycles rename is idle")
111        .prereq(renameIdleCycles);
112    renameBlockCycles
113        .name(name() + ".BlockCycles")
114        .desc("Number of cycles rename is blocking")
115        .prereq(renameBlockCycles);
116    renameSerializeStallCycles
117        .name(name() + ".serializeStallCycles")
118        .desc("count of cycles rename stalled for serializing inst")
119        .flags(Stats::total);
120    renameRunCycles
121        .name(name() + ".RunCycles")
122        .desc("Number of cycles rename is running")
123        .prereq(renameIdleCycles);
124    renameUnblockCycles
125        .name(name() + ".UnblockCycles")
126        .desc("Number of cycles rename is unblocking")
127        .prereq(renameUnblockCycles);
128    renameRenamedInsts
129        .name(name() + ".RenamedInsts")
130        .desc("Number of instructions processed by rename")
131        .prereq(renameRenamedInsts);
132    renameSquashedInsts
133        .name(name() + ".SquashedInsts")
134        .desc("Number of squashed instructions processed by rename")
135        .prereq(renameSquashedInsts);
136    renameROBFullEvents
137        .name(name() + ".ROBFullEvents")
138        .desc("Number of times rename has blocked due to ROB full")
139        .prereq(renameROBFullEvents);
140    renameIQFullEvents
141        .name(name() + ".IQFullEvents")
142        .desc("Number of times rename has blocked due to IQ full")
143        .prereq(renameIQFullEvents);
144    renameLQFullEvents
145        .name(name() + ".LQFullEvents")
146        .desc("Number of times rename has blocked due to LQ full")
147        .prereq(renameLQFullEvents);
148    renameSQFullEvents
149        .name(name() + ".SQFullEvents")
150        .desc("Number of times rename has blocked due to SQ full")
151        .prereq(renameSQFullEvents);
152    renameFullRegistersEvents
153        .name(name() + ".FullRegisterEvents")
154        .desc("Number of times there has been no free registers")
155        .prereq(renameFullRegistersEvents);
156    renameRenamedOperands
157        .name(name() + ".RenamedOperands")
158        .desc("Number of destination operands rename has renamed")
159        .prereq(renameRenamedOperands);
160    renameRenameLookups
161        .name(name() + ".RenameLookups")
162        .desc("Number of register rename lookups that rename has made")
163        .prereq(renameRenameLookups);
164    renameCommittedMaps
165        .name(name() + ".CommittedMaps")
166        .desc("Number of HB maps that are committed")
167        .prereq(renameCommittedMaps);
168    renameUndoneMaps
169        .name(name() + ".UndoneMaps")
170        .desc("Number of HB maps that are undone due to squashing")
171        .prereq(renameUndoneMaps);
172    renamedSerializing
173        .name(name() + ".serializingInsts")
174        .desc("count of serializing insts renamed")
175        .flags(Stats::total)
176        ;
177    renamedTempSerializing
178        .name(name() + ".tempSerializingInsts")
179        .desc("count of temporary serializing insts renamed")
180        .flags(Stats::total)
181        ;
182    renameSkidInsts
183        .name(name() + ".skidInsts")
184        .desc("count of insts added to the skid buffer")
185        .flags(Stats::total)
186        ;
187    intRenameLookups
188        .name(name() + ".int_rename_lookups")
189        .desc("Number of integer rename lookups")
190        .prereq(intRenameLookups);
191    fpRenameLookups
192        .name(name() + ".fp_rename_lookups")
193        .desc("Number of floating rename lookups")
194        .prereq(fpRenameLookups);
195    vecRenameLookups
196        .name(name() + ".vec_rename_lookups")
197        .desc("Number of vector rename lookups")
198        .prereq(vecRenameLookups);
199    vecPredRenameLookups
200        .name(name() + ".vec_pred_rename_lookups")
201        .desc("Number of vector predicate rename lookups")
202        .prereq(vecPredRenameLookups);
203}
204
205template <class Impl>
206void
207DefaultRename<Impl>::regProbePoints()
208{
209    ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename");
210    ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(),
211                                                        "SquashInRename");
212}
213
214template <class Impl>
215void
216DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
217{
218    timeBuffer = tb_ptr;
219
220    // Setup wire to read information from time buffer, from IEW stage.
221    fromIEW = timeBuffer->getWire(-iewToRenameDelay);
222
223    // Setup wire to read infromation from time buffer, from commit stage.
224    fromCommit = timeBuffer->getWire(-commitToRenameDelay);
225
226    // Setup wire to write information to previous stages.
227    toDecode = timeBuffer->getWire(0);
228}
229
230template <class Impl>
231void
232DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
233{
234    renameQueue = rq_ptr;
235
236    // Setup wire to write information to future stages.
237    toIEW = renameQueue->getWire(0);
238}
239
240template <class Impl>
241void
242DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
243{
244    decodeQueue = dq_ptr;
245
246    // Setup wire to get information from decode.
247    fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
248}
249
250template <class Impl>
251void
252DefaultRename<Impl>::startupStage()
253{
254    resetStage();
255}
256
257template <class Impl>
258void
259DefaultRename<Impl>::clearStates(ThreadID tid)
260{
261    renameStatus[tid] = Idle;
262
263    freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
264    freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid);
265    freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid);
266    freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
267    emptyROB[tid] = true;
268
269    stalls[tid].iew = false;
270    serializeInst[tid] = NULL;
271
272    instsInProgress[tid] = 0;
273    loadsInProgress[tid] = 0;
274    storesInProgress[tid] = 0;
275
276    serializeOnNextInst[tid] = false;
277}
278
279template <class Impl>
280void
281DefaultRename<Impl>::resetStage()
282{
283    _status = Inactive;
284
285    resumeSerialize = false;
286    resumeUnblocking = false;
287
288    // Grab the number of free entries directly from the stages.
289    for (ThreadID tid = 0; tid < numThreads; tid++) {
290        renameStatus[tid] = Idle;
291
292        freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
293        freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid);
294        freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid);
295        freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
296        emptyROB[tid] = true;
297
298        stalls[tid].iew = false;
299        serializeInst[tid] = NULL;
300
301        instsInProgress[tid] = 0;
302        loadsInProgress[tid] = 0;
303        storesInProgress[tid] = 0;
304
305        serializeOnNextInst[tid] = false;
306    }
307}
308
309template<class Impl>
310void
311DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
312{
313    activeThreads = at_ptr;
314}
315
316
317template <class Impl>
318void
319DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
320{
321    for (ThreadID tid = 0; tid < numThreads; tid++)
322        renameMap[tid] = &rm_ptr[tid];
323}
324
325template <class Impl>
326void
327DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
328{
329    freeList = fl_ptr;
330}
331
332template<class Impl>
333void
334DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
335{
336    scoreboard = _scoreboard;
337}
338
339template <class Impl>
340bool
341DefaultRename<Impl>::isDrained() const
342{
343    for (ThreadID tid = 0; tid < numThreads; tid++) {
344        if (instsInProgress[tid] != 0 ||
345            !historyBuffer[tid].empty() ||
346            !skidBuffer[tid].empty() ||
347            !insts[tid].empty() ||
348            (renameStatus[tid] != Idle && renameStatus[tid] != Running))
349            return false;
350    }
351    return true;
352}
353
354template <class Impl>
355void
356DefaultRename<Impl>::takeOverFrom()
357{
358    resetStage();
359}
360
361template <class Impl>
362void
363DefaultRename<Impl>::drainSanityCheck() const
364{
365    for (ThreadID tid = 0; tid < numThreads; tid++) {
366        assert(historyBuffer[tid].empty());
367        assert(insts[tid].empty());
368        assert(skidBuffer[tid].empty());
369        assert(instsInProgress[tid] == 0);
370    }
371}
372
373template <class Impl>
374void
375DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
376{
377    DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
378
379    // Clear the stall signal if rename was blocked or unblocking before.
380    // If it still needs to block, the blocking should happen the next
381    // cycle and there should be space to hold everything due to the squash.
382    if (renameStatus[tid] == Blocked ||
383        renameStatus[tid] == Unblocking) {
384        toDecode->renameUnblock[tid] = 1;
385
386        resumeSerialize = false;
387        serializeInst[tid] = NULL;
388    } else if (renameStatus[tid] == SerializeStall) {
389        if (serializeInst[tid]->seqNum <= squash_seq_num) {
390            DPRINTF(Rename, "Rename will resume serializing after squash\n");
391            resumeSerialize = true;
392            assert(serializeInst[tid]);
393        } else {
394            resumeSerialize = false;
395            toDecode->renameUnblock[tid] = 1;
396
397            serializeInst[tid] = NULL;
398        }
399    }
400
401    // Set the status to Squashing.
402    renameStatus[tid] = Squashing;
403
404    // Squash any instructions from decode.
405    for (int i=0; i<fromDecode->size; i++) {
406        if (fromDecode->insts[i]->threadNumber == tid &&
407            fromDecode->insts[i]->seqNum > squash_seq_num) {
408            fromDecode->insts[i]->setSquashed();
409            wroteToTimeBuffer = true;
410        }
411
412    }
413
414    // Clear the instruction list and skid buffer in case they have any
415    // insts in them.
416    insts[tid].clear();
417
418    // Clear the skid buffer in case it has any data in it.
419    skidBuffer[tid].clear();
420
421    doSquash(squash_seq_num, tid);
422}
423
424template <class Impl>
425void
426DefaultRename<Impl>::tick()
427{
428    wroteToTimeBuffer = false;
429
430    blockThisCycle = false;
431
432    bool status_change = false;
433
434    toIEWIndex = 0;
435
436    sortInsts();
437
438    list<ThreadID>::iterator threads = activeThreads->begin();
439    list<ThreadID>::iterator end = activeThreads->end();
440
441    // Check stall and squash signals.
442    while (threads != end) {
443        ThreadID tid = *threads++;
444
445        DPRINTF(Rename, "Processing [tid:%i]\n", tid);
446
447        status_change = checkSignalsAndUpdate(tid) || status_change;
448
449        rename(status_change, tid);
450    }
451
452    if (status_change) {
453        updateStatus();
454    }
455
456    if (wroteToTimeBuffer) {
457        DPRINTF(Activity, "Activity this cycle.\n");
458        cpu->activityThisCycle();
459    }
460
461    threads = activeThreads->begin();
462
463    while (threads != end) {
464        ThreadID tid = *threads++;
465
466        // If we committed this cycle then doneSeqNum will be > 0
467        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
468            !fromCommit->commitInfo[tid].squash &&
469            renameStatus[tid] != Squashing) {
470
471            removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
472                                  tid);
473        }
474    }
475
476    // @todo: make into updateProgress function
477    for (ThreadID tid = 0; tid < numThreads; tid++) {
478        instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
479        loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ;
480        storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ;
481        assert(loadsInProgress[tid] >= 0);
482        assert(storesInProgress[tid] >= 0);
483        assert(instsInProgress[tid] >=0);
484    }
485
486}
487
488template<class Impl>
489void
490DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
491{
492    // If status is Running or idle,
493    //     call renameInsts()
494    // If status is Unblocking,
495    //     buffer any instructions coming from decode
496    //     continue trying to empty skid buffer
497    //     check if stall conditions have passed
498
499    if (renameStatus[tid] == Blocked) {
500        ++renameBlockCycles;
501    } else if (renameStatus[tid] == Squashing) {
502        ++renameSquashCycles;
503    } else if (renameStatus[tid] == SerializeStall) {
504        ++renameSerializeStallCycles;
505        // If we are currently in SerializeStall and resumeSerialize
506        // was set, then that means that we are resuming serializing
507        // this cycle.  Tell the previous stages to block.
508        if (resumeSerialize) {
509            resumeSerialize = false;
510            block(tid);
511            toDecode->renameUnblock[tid] = false;
512        }
513    } else if (renameStatus[tid] == Unblocking) {
514        if (resumeUnblocking) {
515            block(tid);
516            resumeUnblocking = false;
517            toDecode->renameUnblock[tid] = false;
518        }
519    }
520
521    if (renameStatus[tid] == Running ||
522        renameStatus[tid] == Idle) {
523        DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
524                "stage.\n", tid);
525
526        renameInsts(tid);
527    } else if (renameStatus[tid] == Unblocking) {
528        renameInsts(tid);
529
530        if (validInsts()) {
531            // Add the current inputs to the skid buffer so they can be
532            // reprocessed when this stage unblocks.
533            skidInsert(tid);
534        }
535
536        // If we switched over to blocking, then there's a potential for
537        // an overall status change.
538        status_change = unblock(tid) || status_change || blockThisCycle;
539    }
540}
541
542template <class Impl>
543void
544DefaultRename<Impl>::renameInsts(ThreadID tid)
545{
546    // Instructions can be either in the skid buffer or the queue of
547    // instructions coming from decode, depending on the status.
548    int insts_available = renameStatus[tid] == Unblocking ?
549        skidBuffer[tid].size() : insts[tid].size();
550
551    // Check the decode queue to see if instructions are available.
552    // If there are no available instructions to rename, then do nothing.
553    if (insts_available == 0) {
554        DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
555                tid);
556        // Should I change status to idle?
557        ++renameIdleCycles;
558        return;
559    } else if (renameStatus[tid] == Unblocking) {
560        ++renameUnblockCycles;
561    } else if (renameStatus[tid] == Running) {
562        ++renameRunCycles;
563    }
564
565    // Will have to do a different calculation for the number of free
566    // entries.
567    int free_rob_entries = calcFreeROBEntries(tid);
568    int free_iq_entries  = calcFreeIQEntries(tid);
569    int min_free_entries = free_rob_entries;
570
571    FullSource source = ROB;
572
573    if (free_iq_entries < min_free_entries) {
574        min_free_entries = free_iq_entries;
575        source = IQ;
576    }
577
578    // Check if there's any space left.
579    if (min_free_entries <= 0) {
580        DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ "
581                "entries.\n"
582                "ROB has %i free entries.\n"
583                "IQ has %i free entries.\n",
584                tid,
585                free_rob_entries,
586                free_iq_entries);
587
588        blockThisCycle = true;
589
590        block(tid);
591
592        incrFullStat(source);
593
594        return;
595    } else if (min_free_entries < insts_available) {
596        DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
597                "%i insts available, but only %i insts can be "
598                "renamed due to ROB/IQ/LSQ limits.\n",
599                tid, insts_available, min_free_entries);
600
601        insts_available = min_free_entries;
602
603        blockThisCycle = true;
604
605        incrFullStat(source);
606    }
607
608    InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
609        skidBuffer[tid] : insts[tid];
610
611    DPRINTF(Rename, "[tid:%u]: %i available instructions to "
612            "send iew.\n", tid, insts_available);
613
614    DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
615            "dispatched to IQ last cycle.\n",
616            tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
617
618    // Handle serializing the next instruction if necessary.
619    if (serializeOnNextInst[tid]) {
620        if (emptyROB[tid] && instsInProgress[tid] == 0) {
621            // ROB already empty; no need to serialize.
622            serializeOnNextInst[tid] = false;
623        } else if (!insts_to_rename.empty()) {
624            insts_to_rename.front()->setSerializeBefore();
625        }
626    }
627
628    int renamed_insts = 0;
629
630    while (insts_available > 0 &&  toIEWIndex < renameWidth) {
631        DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
632
633        assert(!insts_to_rename.empty());
634
635        DynInstPtr inst = insts_to_rename.front();
636
637        //For all kind of instructions, check ROB and IQ first
638        //For load instruction, check LQ size and take into account the inflight loads
639        //For store instruction, check SQ size and take into account the inflight stores
640
641        if (inst->isLoad()) {
642            if (calcFreeLQEntries(tid) <= 0) {
643                DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n");
644                source = LQ;
645                incrFullStat(source);
646                break;
647            }
648        }
649
650        if (inst->isStore()) {
651            if (calcFreeSQEntries(tid) <= 0) {
652                DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n");
653                source = SQ;
654                incrFullStat(source);
655                break;
656            }
657        }
658
659        insts_to_rename.pop_front();
660
661        if (renameStatus[tid] == Unblocking) {
662            DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
663                    "skidBuffer\n", tid, inst->seqNum, inst->pcState());
664        }
665
666        if (inst->isSquashed()) {
667            DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
668                    "squashed, skipping.\n", tid, inst->seqNum,
669                    inst->pcState());
670
671            ++renameSquashedInsts;
672
673            // Decrement how many instructions are available.
674            --insts_available;
675
676            continue;
677        }
678
679        DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
680                "PC %s.\n", tid, inst->seqNum, inst->pcState());
681
682        // Check here to make sure there are enough destination registers
683        // to rename to.  Otherwise block.
684        if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
685                                       inst->numFPDestRegs(),
686                                       inst->numVecDestRegs(),
687                                       inst->numVecElemDestRegs(),
688                                       inst->numVecPredDestRegs(),
689                                       inst->numCCDestRegs())) {
690            DPRINTF(Rename, "Blocking due to lack of free "
691                    "physical registers to rename to.\n");
692            blockThisCycle = true;
693            insts_to_rename.push_front(inst);
694            ++renameFullRegistersEvents;
695
696            break;
697        }
698
699        // Handle serializeAfter/serializeBefore instructions.
700        // serializeAfter marks the next instruction as serializeBefore.
701        // serializeBefore makes the instruction wait in rename until the ROB
702        // is empty.
703
704        // In this model, IPR accesses are serialize before
705        // instructions, and store conditionals are serialize after
706        // instructions.  This is mainly due to lack of support for
707        // out-of-order operations of either of those classes of
708        // instructions.
709        if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
710            !inst->isSerializeHandled()) {
711            DPRINTF(Rename, "Serialize before instruction encountered.\n");
712
713            if (!inst->isTempSerializeBefore()) {
714                renamedSerializing++;
715                inst->setSerializeHandled();
716            } else {
717                renamedTempSerializing++;
718            }
719
720            // Change status over to SerializeStall so that other stages know
721            // what this is blocked on.
722            renameStatus[tid] = SerializeStall;
723
724            serializeInst[tid] = inst;
725
726            blockThisCycle = true;
727
728            break;
729        } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
730                   !inst->isSerializeHandled()) {
731            DPRINTF(Rename, "Serialize after instruction encountered.\n");
732
733            renamedSerializing++;
734
735            inst->setSerializeHandled();
736
737            serializeAfter(insts_to_rename, tid);
738        }
739
740        renameSrcRegs(inst, inst->threadNumber);
741
742        renameDestRegs(inst, inst->threadNumber);
743
744        if (inst->isLoad()) {
745                loadsInProgress[tid]++;
746        }
747        if (inst->isStore()) {
748                storesInProgress[tid]++;
749        }
750        ++renamed_insts;
751        // Notify potential listeners that source and destination registers for
752        // this instruction have been renamed.
753        ppRename->notify(inst);
754
755        // Put instruction in rename queue.
756        toIEW->insts[toIEWIndex] = inst;
757        ++(toIEW->size);
758
759        // Increment which instruction we're on.
760        ++toIEWIndex;
761
762        // Decrement how many instructions are available.
763        --insts_available;
764    }
765
766    instsInProgress[tid] += renamed_insts;
767    renameRenamedInsts += renamed_insts;
768
769    // If we wrote to the time buffer, record this.
770    if (toIEWIndex) {
771        wroteToTimeBuffer = true;
772    }
773
774    // Check if there's any instructions left that haven't yet been renamed.
775    // If so then block.
776    if (insts_available) {
777        blockThisCycle = true;
778    }
779
780    if (blockThisCycle) {
781        block(tid);
782        toDecode->renameUnblock[tid] = false;
783    }
784}
785
786template<class Impl>
787void
788DefaultRename<Impl>::skidInsert(ThreadID tid)
789{
790    DynInstPtr inst = NULL;
791
792    while (!insts[tid].empty()) {
793        inst = insts[tid].front();
794
795        insts[tid].pop_front();
796
797        assert(tid == inst->threadNumber);
798
799        DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
800                "skidBuffer\n", tid, inst->seqNum, inst->pcState());
801
802        ++renameSkidInsts;
803
804        skidBuffer[tid].push_back(inst);
805    }
806
807    if (skidBuffer[tid].size() > skidBufferMax)
808    {
809        typename InstQueue::iterator it;
810        warn("Skidbuffer contents:\n");
811        for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
812        {
813            warn("[tid:%u]: %s [sn:%i].\n", tid,
814                    (*it)->staticInst->disassemble(inst->instAddr()),
815                    (*it)->seqNum);
816        }
817        panic("Skidbuffer Exceeded Max Size");
818    }
819}
820
821template <class Impl>
822void
823DefaultRename<Impl>::sortInsts()
824{
825    int insts_from_decode = fromDecode->size;
826    for (int i = 0; i < insts_from_decode; ++i) {
827        const DynInstPtr &inst = fromDecode->insts[i];
828        insts[inst->threadNumber].push_back(inst);
829#if TRACING_ON
830        if (DTRACE(O3PipeView)) {
831            inst->renameTick = curTick() - inst->fetchTick;
832        }
833#endif
834    }
835}
836
837template<class Impl>
838bool
839DefaultRename<Impl>::skidsEmpty()
840{
841    list<ThreadID>::iterator threads = activeThreads->begin();
842    list<ThreadID>::iterator end = activeThreads->end();
843
844    while (threads != end) {
845        ThreadID tid = *threads++;
846
847        if (!skidBuffer[tid].empty())
848            return false;
849    }
850
851    return true;
852}
853
854template<class Impl>
855void
856DefaultRename<Impl>::updateStatus()
857{
858    bool any_unblocking = false;
859
860    list<ThreadID>::iterator threads = activeThreads->begin();
861    list<ThreadID>::iterator end = activeThreads->end();
862
863    while (threads != end) {
864        ThreadID tid = *threads++;
865
866        if (renameStatus[tid] == Unblocking) {
867            any_unblocking = true;
868            break;
869        }
870    }
871
872    // Rename will have activity if it's unblocking.
873    if (any_unblocking) {
874        if (_status == Inactive) {
875            _status = Active;
876
877            DPRINTF(Activity, "Activating stage.\n");
878
879            cpu->activateStage(O3CPU::RenameIdx);
880        }
881    } else {
882        // If it's not unblocking, then rename will not have any internal
883        // activity.  Switch it to inactive.
884        if (_status == Active) {
885            _status = Inactive;
886            DPRINTF(Activity, "Deactivating stage.\n");
887
888            cpu->deactivateStage(O3CPU::RenameIdx);
889        }
890    }
891}
892
893template <class Impl>
894bool
895DefaultRename<Impl>::block(ThreadID tid)
896{
897    DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
898
899    // Add the current inputs onto the skid buffer, so they can be
900    // reprocessed when this stage unblocks.
901    skidInsert(tid);
902
903    // Only signal backwards to block if the previous stages do not think
904    // rename is already blocked.
905    if (renameStatus[tid] != Blocked) {
906        // If resumeUnblocking is set, we unblocked during the squash,
907        // but now we're have unblocking status. We need to tell earlier
908        // stages to block.
909        if (resumeUnblocking || renameStatus[tid] != Unblocking) {
910            toDecode->renameBlock[tid] = true;
911            toDecode->renameUnblock[tid] = false;
912            wroteToTimeBuffer = true;
913        }
914
915        // Rename can not go from SerializeStall to Blocked, otherwise
916        // it would not know to complete the serialize stall.
917        if (renameStatus[tid] != SerializeStall) {
918            // Set status to Blocked.
919            renameStatus[tid] = Blocked;
920            return true;
921        }
922    }
923
924    return false;
925}
926
927template <class Impl>
928bool
929DefaultRename<Impl>::unblock(ThreadID tid)
930{
931    DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
932
933    // Rename is done unblocking if the skid buffer is empty.
934    if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
935
936        DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
937
938        toDecode->renameUnblock[tid] = true;
939        wroteToTimeBuffer = true;
940
941        renameStatus[tid] = Running;
942        return true;
943    }
944
945    return false;
946}
947
948template <class Impl>
949void
950DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
951{
952    typename std::list<RenameHistory>::iterator hb_it =
953        historyBuffer[tid].begin();
954
955    // After a syscall squashes everything, the history buffer may be empty
956    // but the ROB may still be squashing instructions.
957    // Go through the most recent instructions, undoing the mappings
958    // they did and freeing up the registers.
959    while (!historyBuffer[tid].empty() &&
960           hb_it->instSeqNum > squashed_seq_num) {
961        assert(hb_it != historyBuffer[tid].end());
962
963        DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
964                "number %i.\n", tid, hb_it->instSeqNum);
965
966        // Undo the rename mapping only if it was really a change.
967        // Special regs that are not really renamed (like misc regs
968        // and the zero reg) can be recognized because the new mapping
969        // is the same as the old one.  While it would be merely a
970        // waste of time to update the rename table, we definitely
971        // don't want to put these on the free list.
972        if (hb_it->newPhysReg != hb_it->prevPhysReg) {
973            // Tell the rename map to set the architected register to the
974            // previous physical register that it was renamed to.
975            renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
976
977            // Put the renamed physical register back on the free list.
978            freeList->addReg(hb_it->newPhysReg);
979        }
980
981        // Notify potential listeners that the register mapping needs to be
982        // removed because the instruction it was mapped to got squashed. Note
983        // that this is done before hb_it is incremented.
984        ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum,
985                                                hb_it->newPhysReg));
986
987        historyBuffer[tid].erase(hb_it++);
988
989        ++renameUndoneMaps;
990    }
991
992    // Check if we need to change vector renaming mode after squashing
993    cpu->switchRenameMode(tid, freeList);
994}
995
996template<class Impl>
997void
998DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
999{
1000    DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
1001            "history buffer %u (size=%i), until [sn:%lli].\n",
1002            tid, tid, historyBuffer[tid].size(), inst_seq_num);
1003
1004    typename std::list<RenameHistory>::iterator hb_it =
1005        historyBuffer[tid].end();
1006
1007    --hb_it;
1008
1009    if (historyBuffer[tid].empty()) {
1010        DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
1011        return;
1012    } else if (hb_it->instSeqNum > inst_seq_num) {
1013        DPRINTF(Rename, "[tid:%u]: Old sequence number encountered.  Ensure "
1014                "that a syscall happened recently.\n", tid);
1015        return;
1016    }
1017
1018    // Commit all the renames up until (and including) the committed sequence
1019    // number. Some or even all of the committed instructions may not have
1020    // rename histories if they did not have destination registers that were
1021    // renamed.
1022    while (!historyBuffer[tid].empty() &&
1023           hb_it != historyBuffer[tid].end() &&
1024           hb_it->instSeqNum <= inst_seq_num) {
1025
1026        DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), "
1027                "[sn:%lli].\n",
1028                tid, hb_it->prevPhysReg->index(),
1029                hb_it->prevPhysReg->className(),
1030                hb_it->instSeqNum);
1031
1032        // Don't free special phys regs like misc and zero regs, which
1033        // can be recognized because the new mapping is the same as
1034        // the old one.
1035        if (hb_it->newPhysReg != hb_it->prevPhysReg) {
1036            freeList->addReg(hb_it->prevPhysReg);
1037        }
1038
1039        ++renameCommittedMaps;
1040
1041        historyBuffer[tid].erase(hb_it--);
1042    }
1043}
1044
1045template <class Impl>
1046inline void
1047DefaultRename<Impl>::renameSrcRegs(const DynInstPtr &inst, ThreadID tid)
1048{
1049    ThreadContext *tc = inst->tcBase();
1050    RenameMap *map = renameMap[tid];
1051    unsigned num_src_regs = inst->numSrcRegs();
1052
1053    // Get the architectual register numbers from the source and
1054    // operands, and redirect them to the right physical register.
1055    for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
1056        const RegId& src_reg = inst->srcRegIdx(src_idx);
1057        PhysRegIdPtr renamed_reg;
1058
1059        renamed_reg = map->lookup(tc->flattenRegId(src_reg));
1060        switch (src_reg.classValue()) {
1061          case IntRegClass:
1062            intRenameLookups++;
1063            break;
1064          case FloatRegClass:
1065            fpRenameLookups++;
1066            break;
1067          case VecRegClass:
1068          case VecElemClass:
1069            vecRenameLookups++;
1070            break;
1071          case VecPredRegClass:
1072            vecPredRenameLookups++;
1073            break;
1074          case CCRegClass:
1075          case MiscRegClass:
1076            break;
1077
1078          default:
1079            panic("Invalid register class: %d.", src_reg.classValue());
1080        }
1081
1082        DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i"
1083                ", got phys reg %i (%s)\n", tid,
1084                src_reg.className(), src_reg.index(),
1085                renamed_reg->index(),
1086                renamed_reg->className());
1087
1088        inst->renameSrcReg(src_idx, renamed_reg);
1089
1090        // See if the register is ready or not.
1091        if (scoreboard->getReg(renamed_reg)) {
1092            DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)"
1093                    " is ready.\n", tid, renamed_reg->index(),
1094                    renamed_reg->flatIndex(),
1095                    renamed_reg->className());
1096
1097            inst->markSrcRegReady(src_idx);
1098        } else {
1099            DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)"
1100                    " is not ready.\n", tid, renamed_reg->index(),
1101                    renamed_reg->flatIndex(),
1102                    renamed_reg->className());
1103        }
1104
1105        ++renameRenameLookups;
1106    }
1107}
1108
1109template <class Impl>
1110inline void
1111DefaultRename<Impl>::renameDestRegs(const DynInstPtr &inst, ThreadID tid)
1112{
1113    ThreadContext *tc = inst->tcBase();
1114    RenameMap *map = renameMap[tid];
1115    unsigned num_dest_regs = inst->numDestRegs();
1116
1117    // Rename the destination registers.
1118    for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1119        const RegId& dest_reg = inst->destRegIdx(dest_idx);
1120        typename RenameMap::RenameInfo rename_result;
1121
1122        RegId flat_dest_regid = tc->flattenRegId(dest_reg);
1123
1124        rename_result = map->rename(flat_dest_regid);
1125
1126        inst->flattenDestReg(dest_idx, flat_dest_regid);
1127
1128        // Mark Scoreboard entry as not ready
1129        scoreboard->unsetReg(rename_result.first);
1130
1131        DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical "
1132                "reg %i (%i).\n", tid, dest_reg.index(),
1133                dest_reg.className(),
1134                rename_result.first->index(),
1135                rename_result.first->flatIndex());
1136
1137        // Record the rename information so that a history can be kept.
1138        RenameHistory hb_entry(inst->seqNum, flat_dest_regid,
1139                               rename_result.first,
1140                               rename_result.second);
1141
1142        historyBuffer[tid].push_front(hb_entry);
1143
1144        DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1145                "(size=%i), [sn:%lli].\n",tid,
1146                historyBuffer[tid].size(),
1147                (*historyBuffer[tid].begin()).instSeqNum);
1148
1149        // Tell the instruction to rename the appropriate destination
1150        // register (dest_idx) to the new physical register
1151        // (rename_result.first), and record the previous physical
1152        // register that the same logical register was renamed to
1153        // (rename_result.second).
1154        inst->renameDestReg(dest_idx,
1155                            rename_result.first,
1156                            rename_result.second);
1157
1158        ++renameRenamedOperands;
1159    }
1160}
1161
1162template <class Impl>
1163inline int
1164DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1165{
1166    int num_free = freeEntries[tid].robEntries -
1167                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1168
1169    //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1170
1171    return num_free;
1172}
1173
1174template <class Impl>
1175inline int
1176DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1177{
1178    int num_free = freeEntries[tid].iqEntries -
1179                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1180
1181    //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1182
1183    return num_free;
1184}
1185
1186template <class Impl>
1187inline int
1188DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid)
1189{
1190        int num_free = freeEntries[tid].lqEntries -
1191                                  (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ);
1192        DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, "
1193                "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries,
1194                loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ);
1195        return num_free;
1196}
1197
1198template <class Impl>
1199inline int
1200DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid)
1201{
1202        int num_free = freeEntries[tid].sqEntries -
1203                                  (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ);
1204        DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, "
1205                "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries,
1206                storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ);
1207        return num_free;
1208}
1209
1210template <class Impl>
1211unsigned
1212DefaultRename<Impl>::validInsts()
1213{
1214    unsigned inst_count = 0;
1215
1216    for (int i=0; i<fromDecode->size; i++) {
1217        if (!fromDecode->insts[i]->isSquashed())
1218            inst_count++;
1219    }
1220
1221    return inst_count;
1222}
1223
1224template <class Impl>
1225void
1226DefaultRename<Impl>::readStallSignals(ThreadID tid)
1227{
1228    if (fromIEW->iewBlock[tid]) {
1229        stalls[tid].iew = true;
1230    }
1231
1232    if (fromIEW->iewUnblock[tid]) {
1233        assert(stalls[tid].iew);
1234        stalls[tid].iew = false;
1235    }
1236}
1237
1238template <class Impl>
1239bool
1240DefaultRename<Impl>::checkStall(ThreadID tid)
1241{
1242    bool ret_val = false;
1243
1244    if (stalls[tid].iew) {
1245        DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1246        ret_val = true;
1247    } else if (calcFreeROBEntries(tid) <= 0) {
1248        DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1249        ret_val = true;
1250    } else if (calcFreeIQEntries(tid) <= 0) {
1251        DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1252        ret_val = true;
1253    } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) {
1254        DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1255        ret_val = true;
1256    } else if (renameMap[tid]->numFreeEntries() <= 0) {
1257        DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1258        ret_val = true;
1259    } else if (renameStatus[tid] == SerializeStall &&
1260               (!emptyROB[tid] || instsInProgress[tid])) {
1261        DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1262                "empty.\n",
1263                tid);
1264        ret_val = true;
1265    }
1266
1267    return ret_val;
1268}
1269
1270template <class Impl>
1271void
1272DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1273{
1274    if (fromIEW->iewInfo[tid].usedIQ)
1275        freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
1276
1277    if (fromIEW->iewInfo[tid].usedLSQ) {
1278        freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries;
1279        freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries;
1280    }
1281
1282    if (fromCommit->commitInfo[tid].usedROB) {
1283        freeEntries[tid].robEntries =
1284            fromCommit->commitInfo[tid].freeROBEntries;
1285        emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1286    }
1287
1288    DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, "
1289                    "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i %i)\n",
1290            tid,
1291            freeEntries[tid].iqEntries,
1292            freeEntries[tid].robEntries,
1293            freeEntries[tid].lqEntries,
1294            freeEntries[tid].sqEntries,
1295            renameMap[tid]->numFreeEntries(),
1296            renameMap[tid]->numFreeIntEntries(),
1297            renameMap[tid]->numFreeFloatEntries(),
1298            renameMap[tid]->numFreeVecEntries(),
1299            renameMap[tid]->numFreePredEntries(),
1300            renameMap[tid]->numFreeCCEntries());
1301
1302    DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1303            tid, instsInProgress[tid]);
1304}
1305
1306template <class Impl>
1307bool
1308DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1309{
1310    // Check if there's a squash signal, squash if there is
1311    // Check stall signals, block if necessary.
1312    // If status was blocked
1313    //     check if stall conditions have passed
1314    //         if so then go to unblocking
1315    // If status was Squashing
1316    //     check if squashing is not high.  Switch to running this cycle.
1317    // If status was serialize stall
1318    //     check if ROB is empty and no insts are in flight to the ROB
1319
1320    readFreeEntries(tid);
1321    readStallSignals(tid);
1322
1323    if (fromCommit->commitInfo[tid].squash) {
1324        DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1325                "commit.\n", tid);
1326
1327        squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1328
1329        return true;
1330    }
1331
1332    if (checkStall(tid)) {
1333        return block(tid);
1334    }
1335
1336    if (renameStatus[tid] == Blocked) {
1337        DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1338                tid);
1339
1340        renameStatus[tid] = Unblocking;
1341
1342        unblock(tid);
1343
1344        return true;
1345    }
1346
1347    if (renameStatus[tid] == Squashing) {
1348        // Switch status to running if rename isn't being told to block or
1349        // squash this cycle.
1350        if (resumeSerialize) {
1351            DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1352                    tid);
1353
1354            renameStatus[tid] = SerializeStall;
1355            return true;
1356        } else if (resumeUnblocking) {
1357            DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1358                    tid);
1359            renameStatus[tid] = Unblocking;
1360            return true;
1361        } else {
1362            DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1363                    tid);
1364
1365            renameStatus[tid] = Running;
1366            return false;
1367        }
1368    }
1369
1370    if (renameStatus[tid] == SerializeStall) {
1371        // Stall ends once the ROB is free.
1372        DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1373                "unblocking.\n", tid);
1374
1375        DynInstPtr serial_inst = serializeInst[tid];
1376
1377        renameStatus[tid] = Unblocking;
1378
1379        unblock(tid);
1380
1381        DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1382                "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1383
1384        // Put instruction into queue here.
1385        serial_inst->clearSerializeBefore();
1386
1387        if (!skidBuffer[tid].empty()) {
1388            skidBuffer[tid].push_front(serial_inst);
1389        } else {
1390            insts[tid].push_front(serial_inst);
1391        }
1392
1393        DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1394                " Adding to front of list.\n", tid);
1395
1396        serializeInst[tid] = NULL;
1397
1398        return true;
1399    }
1400
1401    // If we've reached this point, we have not gotten any signals that
1402    // cause rename to change its status.  Rename remains the same as before.
1403    return false;
1404}
1405
1406template<class Impl>
1407void
1408DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1409{
1410    if (inst_list.empty()) {
1411        // Mark a bit to say that I must serialize on the next instruction.
1412        serializeOnNextInst[tid] = true;
1413        return;
1414    }
1415
1416    // Set the next instruction as serializing.
1417    inst_list.front()->setSerializeBefore();
1418}
1419
1420template <class Impl>
1421inline void
1422DefaultRename<Impl>::incrFullStat(const FullSource &source)
1423{
1424    switch (source) {
1425      case ROB:
1426        ++renameROBFullEvents;
1427        break;
1428      case IQ:
1429        ++renameIQFullEvents;
1430        break;
1431      case LQ:
1432        ++renameLQFullEvents;
1433        break;
1434      case SQ:
1435        ++renameSQFullEvents;
1436        break;
1437      default:
1438        panic("Rename full stall stat should be incremented for a reason!");
1439        break;
1440    }
1441}
1442
1443template <class Impl>
1444void
1445DefaultRename<Impl>::dumpHistory()
1446{
1447    typename std::list<RenameHistory>::iterator buf_it;
1448
1449    for (ThreadID tid = 0; tid < numThreads; tid++) {
1450
1451        buf_it = historyBuffer[tid].begin();
1452
1453        while (buf_it != historyBuffer[tid].end()) {
1454            cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:"
1455                    " %i[%s] Old phys reg: %i[%s]\n",
1456                    (*buf_it).instSeqNum,
1457                    (*buf_it).archReg.className(),
1458                    (*buf_it).archReg.index(),
1459                    (*buf_it).newPhysReg->index(),
1460                    (*buf_it).newPhysReg->className(),
1461                    (*buf_it).prevPhysReg->index(),
1462                    (*buf_it).prevPhysReg->className());
1463
1464            buf_it++;
1465        }
1466    }
1467}
1468
1469#endif//__CPU_O3_RENAME_IMPL_HH__
1470