rename_impl.hh revision 13601
11689SN/A/* 212106SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2010-2012, 2014-2016 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47854SAli.Saidi@ARM.com * All rights reserved. 57854SAli.Saidi@ARM.com * 67854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147854SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422935Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_RENAME_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_RENAME_IMPL_HH__ 479944Smatt.horsnell@ARM.com 481060SN/A#include <list> 491060SN/A 503773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 516329Sgblack@eecs.umich.edu#include "arch/registers.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 531717SN/A#include "cpu/o3/rename.hh" 549913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 558232Snate@binkert.org#include "debug/Activity.hh" 568232Snate@binkert.org#include "debug/Rename.hh" 579527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 585529Snate@binkert.org#include "params/DerivO3CPU.hh" 591060SN/A 606221Snate@binkert.orgusing namespace std; 616221Snate@binkert.org 621061SN/Atemplate <class Impl> 635529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 644329Sktlim@umich.edu : cpu(_cpu), 654329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 662292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 672292SN/A commitToRenameDelay(params->commitToRenameDelay), 682292SN/A renameWidth(params->renameWidth), 692292SN/A commitWidth(params->commitWidth), 7012109SRekai.GonzalezAlberquilla@arm.com numThreads(params->numThreads) 711060SN/A{ 7210172Sdam.sunwoo@arm.com if (renameWidth > Impl::MaxWidth) 7310172Sdam.sunwoo@arm.com fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 7410172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 7510172Sdam.sunwoo@arm.com renameWidth, static_cast<int>(Impl::MaxWidth)); 7610172Sdam.sunwoo@arm.com 772292SN/A // @todo: Make into a parameter. 7810328Smitch.hayenga@arm.com skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; 7913453Srekai.gonzalezalberquilla@arm.com for (uint32_t tid = 0; tid < Impl::MaxThreads; tid++) { 8013453Srekai.gonzalezalberquilla@arm.com renameStatus[tid] = Idle; 8113453Srekai.gonzalezalberquilla@arm.com renameMap[tid] = nullptr; 8213453Srekai.gonzalezalberquilla@arm.com instsInProgress[tid] = 0; 8313453Srekai.gonzalezalberquilla@arm.com loadsInProgress[tid] = 0; 8413453Srekai.gonzalezalberquilla@arm.com storesInProgress[tid] = 0; 8513453Srekai.gonzalezalberquilla@arm.com freeEntries[tid] = {0, 0, 0, 0}; 8613453Srekai.gonzalezalberquilla@arm.com emptyROB[tid] = true; 8713453Srekai.gonzalezalberquilla@arm.com stalls[tid] = {false, false}; 8813453Srekai.gonzalezalberquilla@arm.com serializeInst[tid] = nullptr; 8913453Srekai.gonzalezalberquilla@arm.com serializeOnNextInst[tid] = false; 9013453Srekai.gonzalezalberquilla@arm.com } 912292SN/A} 922292SN/A 932292SN/Atemplate <class Impl> 942292SN/Astd::string 952292SN/ADefaultRename<Impl>::name() const 962292SN/A{ 972292SN/A return cpu->name() + ".rename"; 981060SN/A} 991060SN/A 1001061SN/Atemplate <class Impl> 1011060SN/Avoid 1022292SN/ADefaultRename<Impl>::regStats() 1031062SN/A{ 1041062SN/A renameSquashCycles 1058240Snate@binkert.org .name(name() + ".SquashCycles") 1061062SN/A .desc("Number of cycles rename is squashing") 1071062SN/A .prereq(renameSquashCycles); 1081062SN/A renameIdleCycles 1098240Snate@binkert.org .name(name() + ".IdleCycles") 1101062SN/A .desc("Number of cycles rename is idle") 1111062SN/A .prereq(renameIdleCycles); 1121062SN/A renameBlockCycles 1138240Snate@binkert.org .name(name() + ".BlockCycles") 1141062SN/A .desc("Number of cycles rename is blocking") 1151062SN/A .prereq(renameBlockCycles); 1162301SN/A renameSerializeStallCycles 1178240Snate@binkert.org .name(name() + ".serializeStallCycles") 1182301SN/A .desc("count of cycles rename stalled for serializing inst") 1192301SN/A .flags(Stats::total); 1202292SN/A renameRunCycles 1218240Snate@binkert.org .name(name() + ".RunCycles") 1222292SN/A .desc("Number of cycles rename is running") 1232292SN/A .prereq(renameIdleCycles); 1241062SN/A renameUnblockCycles 1258240Snate@binkert.org .name(name() + ".UnblockCycles") 1261062SN/A .desc("Number of cycles rename is unblocking") 1271062SN/A .prereq(renameUnblockCycles); 1281062SN/A renameRenamedInsts 1298240Snate@binkert.org .name(name() + ".RenamedInsts") 1301062SN/A .desc("Number of instructions processed by rename") 1311062SN/A .prereq(renameRenamedInsts); 1321062SN/A renameSquashedInsts 1338240Snate@binkert.org .name(name() + ".SquashedInsts") 1341062SN/A .desc("Number of squashed instructions processed by rename") 1351062SN/A .prereq(renameSquashedInsts); 1361062SN/A renameROBFullEvents 1378240Snate@binkert.org .name(name() + ".ROBFullEvents") 1382292SN/A .desc("Number of times rename has blocked due to ROB full") 1391062SN/A .prereq(renameROBFullEvents); 1401062SN/A renameIQFullEvents 1418240Snate@binkert.org .name(name() + ".IQFullEvents") 1422292SN/A .desc("Number of times rename has blocked due to IQ full") 1431062SN/A .prereq(renameIQFullEvents); 14410239Sbinhpham@cs.rutgers.edu renameLQFullEvents 14510239Sbinhpham@cs.rutgers.edu .name(name() + ".LQFullEvents") 14610239Sbinhpham@cs.rutgers.edu .desc("Number of times rename has blocked due to LQ full") 14710239Sbinhpham@cs.rutgers.edu .prereq(renameLQFullEvents); 14810239Sbinhpham@cs.rutgers.edu renameSQFullEvents 14910239Sbinhpham@cs.rutgers.edu .name(name() + ".SQFullEvents") 15010239Sbinhpham@cs.rutgers.edu .desc("Number of times rename has blocked due to SQ full") 15110239Sbinhpham@cs.rutgers.edu .prereq(renameSQFullEvents); 1521062SN/A renameFullRegistersEvents 1538240Snate@binkert.org .name(name() + ".FullRegisterEvents") 1541062SN/A .desc("Number of times there has been no free registers") 1551062SN/A .prereq(renameFullRegistersEvents); 1561062SN/A renameRenamedOperands 1578240Snate@binkert.org .name(name() + ".RenamedOperands") 1581062SN/A .desc("Number of destination operands rename has renamed") 1591062SN/A .prereq(renameRenamedOperands); 1601062SN/A renameRenameLookups 1618240Snate@binkert.org .name(name() + ".RenameLookups") 1621062SN/A .desc("Number of register rename lookups that rename has made") 1631062SN/A .prereq(renameRenameLookups); 1641062SN/A renameCommittedMaps 1658240Snate@binkert.org .name(name() + ".CommittedMaps") 1661062SN/A .desc("Number of HB maps that are committed") 1671062SN/A .prereq(renameCommittedMaps); 1681062SN/A renameUndoneMaps 1698240Snate@binkert.org .name(name() + ".UndoneMaps") 1701062SN/A .desc("Number of HB maps that are undone due to squashing") 1711062SN/A .prereq(renameUndoneMaps); 1722301SN/A renamedSerializing 1738240Snate@binkert.org .name(name() + ".serializingInsts") 1742301SN/A .desc("count of serializing insts renamed") 1752301SN/A .flags(Stats::total) 1762301SN/A ; 1772301SN/A renamedTempSerializing 1788240Snate@binkert.org .name(name() + ".tempSerializingInsts") 1792301SN/A .desc("count of temporary serializing insts renamed") 1802301SN/A .flags(Stats::total) 1812301SN/A ; 1822307SN/A renameSkidInsts 1838240Snate@binkert.org .name(name() + ".skidInsts") 1842307SN/A .desc("count of insts added to the skid buffer") 1852307SN/A .flags(Stats::total) 1862307SN/A ; 1877897Shestness@cs.utexas.edu intRenameLookups 1888240Snate@binkert.org .name(name() + ".int_rename_lookups") 1897897Shestness@cs.utexas.edu .desc("Number of integer rename lookups") 1907897Shestness@cs.utexas.edu .prereq(intRenameLookups); 1917897Shestness@cs.utexas.edu fpRenameLookups 1928240Snate@binkert.org .name(name() + ".fp_rename_lookups") 1937897Shestness@cs.utexas.edu .desc("Number of floating rename lookups") 1947897Shestness@cs.utexas.edu .prereq(fpRenameLookups); 19512109SRekai.GonzalezAlberquilla@arm.com vecRenameLookups 19612109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_rename_lookups") 19712109SRekai.GonzalezAlberquilla@arm.com .desc("Number of vector rename lookups") 19812109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRenameLookups); 1991062SN/A} 2001062SN/A 2011062SN/Atemplate <class Impl> 2021062SN/Avoid 20311246Sradhika.jagtap@ARM.comDefaultRename<Impl>::regProbePoints() 20411246Sradhika.jagtap@ARM.com{ 20511246Sradhika.jagtap@ARM.com ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); 20611246Sradhika.jagtap@ARM.com ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), 20711246Sradhika.jagtap@ARM.com "SquashInRename"); 20811246Sradhika.jagtap@ARM.com} 20911246Sradhika.jagtap@ARM.com 21011246Sradhika.jagtap@ARM.comtemplate <class Impl> 21111246Sradhika.jagtap@ARM.comvoid 2122292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2131060SN/A{ 2141060SN/A timeBuffer = tb_ptr; 2151060SN/A 2161060SN/A // Setup wire to read information from time buffer, from IEW stage. 2171060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 2181060SN/A 2191060SN/A // Setup wire to read infromation from time buffer, from commit stage. 2201060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 2211060SN/A 2221060SN/A // Setup wire to write information to previous stages. 2231060SN/A toDecode = timeBuffer->getWire(0); 2241060SN/A} 2251060SN/A 2261061SN/Atemplate <class Impl> 2271060SN/Avoid 2282292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2291060SN/A{ 2301060SN/A renameQueue = rq_ptr; 2311060SN/A 2321060SN/A // Setup wire to write information to future stages. 2331060SN/A toIEW = renameQueue->getWire(0); 2341060SN/A} 2351060SN/A 2361061SN/Atemplate <class Impl> 2371060SN/Avoid 2382292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2391060SN/A{ 2401060SN/A decodeQueue = dq_ptr; 2411060SN/A 2421060SN/A // Setup wire to get information from decode. 2431060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2441060SN/A} 2451060SN/A 2461061SN/Atemplate <class Impl> 2471060SN/Avoid 2489427SAndreas.Sandberg@ARM.comDefaultRename<Impl>::startupStage() 2491060SN/A{ 2509444SAndreas.Sandberg@ARM.com resetStage(); 2519444SAndreas.Sandberg@ARM.com} 2529444SAndreas.Sandberg@ARM.com 2539444SAndreas.Sandberg@ARM.comtemplate <class Impl> 2549444SAndreas.Sandberg@ARM.comvoid 2559444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::resetStage() 2569444SAndreas.Sandberg@ARM.com{ 2579444SAndreas.Sandberg@ARM.com _status = Inactive; 2589444SAndreas.Sandberg@ARM.com 2599444SAndreas.Sandberg@ARM.com resumeSerialize = false; 2609444SAndreas.Sandberg@ARM.com resumeUnblocking = false; 2619444SAndreas.Sandberg@ARM.com 2622329SN/A // Grab the number of free entries directly from the stages. 2636221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2649444SAndreas.Sandberg@ARM.com renameStatus[tid] = Idle; 2659444SAndreas.Sandberg@ARM.com 2662292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 26710239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 26810239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 2692292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2702292SN/A emptyROB[tid] = true; 2719444SAndreas.Sandberg@ARM.com 2729444SAndreas.Sandberg@ARM.com stalls[tid].iew = false; 2739444SAndreas.Sandberg@ARM.com serializeInst[tid] = NULL; 2749444SAndreas.Sandberg@ARM.com 2759444SAndreas.Sandberg@ARM.com instsInProgress[tid] = 0; 27610239Sbinhpham@cs.rutgers.edu loadsInProgress[tid] = 0; 27710239Sbinhpham@cs.rutgers.edu storesInProgress[tid] = 0; 2789444SAndreas.Sandberg@ARM.com 2799444SAndreas.Sandberg@ARM.com serializeOnNextInst[tid] = false; 2802292SN/A } 2811060SN/A} 2821060SN/A 2832292SN/Atemplate<class Impl> 2842292SN/Avoid 2856221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2862292SN/A{ 2872292SN/A activeThreads = at_ptr; 2882292SN/A} 2892292SN/A 2902292SN/A 2911061SN/Atemplate <class Impl> 2921060SN/Avoid 2932292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2941060SN/A{ 2956221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 2966221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 2971060SN/A} 2981060SN/A 2991061SN/Atemplate <class Impl> 3001060SN/Avoid 3012292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 3021060SN/A{ 3032292SN/A freeList = fl_ptr; 3042292SN/A} 3051060SN/A 3062292SN/Atemplate<class Impl> 3072292SN/Avoid 3082292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 3092292SN/A{ 3102292SN/A scoreboard = _scoreboard; 3111060SN/A} 3121060SN/A 3131061SN/Atemplate <class Impl> 3142863Sktlim@umich.edubool 3159444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::isDrained() const 3161060SN/A{ 3179444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3189444SAndreas.Sandberg@ARM.com if (instsInProgress[tid] != 0 || 3199444SAndreas.Sandberg@ARM.com !historyBuffer[tid].empty() || 3209444SAndreas.Sandberg@ARM.com !skidBuffer[tid].empty() || 32111650Srekai.gonzalezalberquilla@arm.com !insts[tid].empty() || 32211650Srekai.gonzalezalberquilla@arm.com (renameStatus[tid] != Idle && renameStatus[tid] != Running)) 3239444SAndreas.Sandberg@ARM.com return false; 3249444SAndreas.Sandberg@ARM.com } 3252863Sktlim@umich.edu return true; 3262316SN/A} 3271060SN/A 3282316SN/Atemplate <class Impl> 3292316SN/Avoid 3302307SN/ADefaultRename<Impl>::takeOverFrom() 3311060SN/A{ 3329444SAndreas.Sandberg@ARM.com resetStage(); 3339444SAndreas.Sandberg@ARM.com} 3341060SN/A 3359444SAndreas.Sandberg@ARM.comtemplate <class Impl> 3369444SAndreas.Sandberg@ARM.comvoid 3379444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::drainSanityCheck() const 3389444SAndreas.Sandberg@ARM.com{ 3396221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3409444SAndreas.Sandberg@ARM.com assert(historyBuffer[tid].empty()); 3419444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 3429444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 3439444SAndreas.Sandberg@ARM.com assert(instsInProgress[tid] == 0); 3442307SN/A } 3452307SN/A} 3462307SN/A 3472307SN/Atemplate <class Impl> 3482307SN/Avoid 3496221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3501858SN/A{ 3512292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3521858SN/A 3532292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3542292SN/A // If it still needs to block, the blocking should happen the next 3552292SN/A // cycle and there should be space to hold everything due to the squash. 3562292SN/A if (renameStatus[tid] == Blocked || 3573788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3582292SN/A toDecode->renameUnblock[tid] = 1; 3592698Sktlim@umich.edu 3603788Sgblack@eecs.umich.edu resumeSerialize = false; 3612301SN/A serializeInst[tid] = NULL; 3623788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3633788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3643788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3653788Sgblack@eecs.umich.edu resumeSerialize = true; 3663788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3673788Sgblack@eecs.umich.edu } else { 3683788Sgblack@eecs.umich.edu resumeSerialize = false; 3693788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3703788Sgblack@eecs.umich.edu 3713788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3723788Sgblack@eecs.umich.edu } 3732292SN/A } 3742292SN/A 3752292SN/A // Set the status to Squashing. 3762292SN/A renameStatus[tid] = Squashing; 3772292SN/A 3782329SN/A // Squash any instructions from decode. 3792292SN/A for (int i=0; i<fromDecode->size; i++) { 3802935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3812935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3822731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3832292SN/A wroteToTimeBuffer = true; 3842292SN/A } 3852935Sksewell@umich.edu 3862292SN/A } 3872292SN/A 3882935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3894632Sgblack@eecs.umich.edu // insts in them. 3903093Sksewell@umich.edu insts[tid].clear(); 3912292SN/A 3922292SN/A // Clear the skid buffer in case it has any data in it. 3933093Sksewell@umich.edu skidBuffer[tid].clear(); 3944632Sgblack@eecs.umich.edu 3952935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3962292SN/A} 3972292SN/A 3982292SN/Atemplate <class Impl> 3992292SN/Avoid 4002292SN/ADefaultRename<Impl>::tick() 4012292SN/A{ 4022292SN/A wroteToTimeBuffer = false; 4032292SN/A 4042292SN/A blockThisCycle = false; 4052292SN/A 4062292SN/A bool status_change = false; 4072292SN/A 4082292SN/A toIEWIndex = 0; 4092292SN/A 4102292SN/A sortInsts(); 4112292SN/A 4126221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4136221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4142292SN/A 4152292SN/A // Check stall and squash signals. 4163867Sbinkertn@umich.edu while (threads != end) { 4176221Snate@binkert.org ThreadID tid = *threads++; 4182292SN/A 4192292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4202292SN/A 4212292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4222292SN/A 4232292SN/A rename(status_change, tid); 4242292SN/A } 4252292SN/A 4262292SN/A if (status_change) { 4272292SN/A updateStatus(); 4282292SN/A } 4292292SN/A 4302292SN/A if (wroteToTimeBuffer) { 4312292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4322292SN/A cpu->activityThisCycle(); 4332292SN/A } 4342292SN/A 4353867Sbinkertn@umich.edu threads = activeThreads->begin(); 4362292SN/A 4373867Sbinkertn@umich.edu while (threads != end) { 4386221Snate@binkert.org ThreadID tid = *threads++; 4392292SN/A 4402292SN/A // If we committed this cycle then doneSeqNum will be > 0 4412292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4422292SN/A !fromCommit->commitInfo[tid].squash && 4432292SN/A renameStatus[tid] != Squashing) { 4442292SN/A 4452292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4462292SN/A tid); 4472292SN/A } 4482292SN/A } 4492292SN/A 4502292SN/A // @todo: make into updateProgress function 4516221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4522292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 45310239Sbinhpham@cs.rutgers.edu loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 45410239Sbinhpham@cs.rutgers.edu storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 45510239Sbinhpham@cs.rutgers.edu assert(loadsInProgress[tid] >= 0); 45610239Sbinhpham@cs.rutgers.edu assert(storesInProgress[tid] >= 0); 4572292SN/A assert(instsInProgress[tid] >=0); 4582292SN/A } 4592292SN/A 4602292SN/A} 4612292SN/A 4622292SN/Atemplate<class Impl> 4632292SN/Avoid 4646221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4652292SN/A{ 4662292SN/A // If status is Running or idle, 4672292SN/A // call renameInsts() 4682292SN/A // If status is Unblocking, 4692292SN/A // buffer any instructions coming from decode 4702292SN/A // continue trying to empty skid buffer 4712292SN/A // check if stall conditions have passed 4722292SN/A 4732292SN/A if (renameStatus[tid] == Blocked) { 4742292SN/A ++renameBlockCycles; 4752292SN/A } else if (renameStatus[tid] == Squashing) { 4762292SN/A ++renameSquashCycles; 4772301SN/A } else if (renameStatus[tid] == SerializeStall) { 4782301SN/A ++renameSerializeStallCycles; 4793788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4803788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4813788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4823788Sgblack@eecs.umich.edu if (resumeSerialize) { 4833788Sgblack@eecs.umich.edu resumeSerialize = false; 4843788Sgblack@eecs.umich.edu block(tid); 4853788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4863788Sgblack@eecs.umich.edu } 4873798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4883798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4893798Sgblack@eecs.umich.edu block(tid); 4903798Sgblack@eecs.umich.edu resumeUnblocking = false; 4913798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4923798Sgblack@eecs.umich.edu } 4932292SN/A } 4942292SN/A 4952292SN/A if (renameStatus[tid] == Running || 4962292SN/A renameStatus[tid] == Idle) { 4972292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4982292SN/A "stage.\n", tid); 4992292SN/A 5002292SN/A renameInsts(tid); 5012292SN/A } else if (renameStatus[tid] == Unblocking) { 5022292SN/A renameInsts(tid); 5032292SN/A 5042292SN/A if (validInsts()) { 5052292SN/A // Add the current inputs to the skid buffer so they can be 5062292SN/A // reprocessed when this stage unblocks. 5072292SN/A skidInsert(tid); 5082292SN/A } 5092292SN/A 5102292SN/A // If we switched over to blocking, then there's a potential for 5112292SN/A // an overall status change. 5122292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 5131858SN/A } 5141858SN/A} 5151858SN/A 5161858SN/Atemplate <class Impl> 5171858SN/Avoid 5186221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 5191858SN/A{ 5202292SN/A // Instructions can be either in the skid buffer or the queue of 5212292SN/A // instructions coming from decode, depending on the status. 5222292SN/A int insts_available = renameStatus[tid] == Unblocking ? 5232292SN/A skidBuffer[tid].size() : insts[tid].size(); 5241858SN/A 5252292SN/A // Check the decode queue to see if instructions are available. 5262292SN/A // If there are no available instructions to rename, then do nothing. 5272292SN/A if (insts_available == 0) { 5282292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5292292SN/A tid); 5302292SN/A // Should I change status to idle? 5312292SN/A ++renameIdleCycles; 5322292SN/A return; 5332292SN/A } else if (renameStatus[tid] == Unblocking) { 5342292SN/A ++renameUnblockCycles; 5352292SN/A } else if (renameStatus[tid] == Running) { 5362292SN/A ++renameRunCycles; 5372292SN/A } 5381858SN/A 5392292SN/A // Will have to do a different calculation for the number of free 5402292SN/A // entries. 5412292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5422292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5432292SN/A int min_free_entries = free_rob_entries; 5442292SN/A 5452292SN/A FullSource source = ROB; 5462292SN/A 5472292SN/A if (free_iq_entries < min_free_entries) { 5482292SN/A min_free_entries = free_iq_entries; 5492292SN/A source = IQ; 5502292SN/A } 5512292SN/A 5522292SN/A // Check if there's any space left. 5532292SN/A if (min_free_entries <= 0) { 55410239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " 5552292SN/A "entries.\n" 5562292SN/A "ROB has %i free entries.\n" 55710239Sbinhpham@cs.rutgers.edu "IQ has %i free entries.\n", 5582292SN/A tid, 5592292SN/A free_rob_entries, 56010239Sbinhpham@cs.rutgers.edu free_iq_entries); 5612292SN/A 5622292SN/A blockThisCycle = true; 5632292SN/A 5642292SN/A block(tid); 5652292SN/A 5662292SN/A incrFullStat(source); 5672292SN/A 5682292SN/A return; 5692292SN/A } else if (min_free_entries < insts_available) { 5702292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5712292SN/A "%i insts available, but only %i insts can be " 5722292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5732292SN/A tid, insts_available, min_free_entries); 5742292SN/A 5752292SN/A insts_available = min_free_entries; 5762292SN/A 5772292SN/A blockThisCycle = true; 5782292SN/A 5792292SN/A incrFullStat(source); 5802292SN/A } 5812292SN/A 5822292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5832292SN/A skidBuffer[tid] : insts[tid]; 5842292SN/A 5852292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5862292SN/A "send iew.\n", tid, insts_available); 5872292SN/A 5882292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5892292SN/A "dispatched to IQ last cycle.\n", 5902292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5912292SN/A 5922292SN/A // Handle serializing the next instruction if necessary. 5932292SN/A if (serializeOnNextInst[tid]) { 5942292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5952292SN/A // ROB already empty; no need to serialize. 5962292SN/A serializeOnNextInst[tid] = false; 5972292SN/A } else if (!insts_to_rename.empty()) { 5982292SN/A insts_to_rename.front()->setSerializeBefore(); 5992292SN/A } 6002292SN/A } 6012292SN/A 6022292SN/A int renamed_insts = 0; 6032292SN/A 6042292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 6052292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 6062292SN/A 6072292SN/A assert(!insts_to_rename.empty()); 6082292SN/A 60913429Srekai.gonzalezalberquilla@arm.com DynInstPtr inst = insts_to_rename.front(); 6102292SN/A 61110239Sbinhpham@cs.rutgers.edu //For all kind of instructions, check ROB and IQ first 61210239Sbinhpham@cs.rutgers.edu //For load instruction, check LQ size and take into account the inflight loads 61310239Sbinhpham@cs.rutgers.edu //For store instruction, check SQ size and take into account the inflight stores 61410239Sbinhpham@cs.rutgers.edu 61510239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 61610933Snilay@cs.wisc.edu if (calcFreeLQEntries(tid) <= 0) { 61710933Snilay@cs.wisc.edu DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n"); 61810933Snilay@cs.wisc.edu source = LQ; 61910933Snilay@cs.wisc.edu incrFullStat(source); 62010933Snilay@cs.wisc.edu break; 62110933Snilay@cs.wisc.edu } 62210239Sbinhpham@cs.rutgers.edu } 62310239Sbinhpham@cs.rutgers.edu 62410239Sbinhpham@cs.rutgers.edu if (inst->isStore()) { 62510933Snilay@cs.wisc.edu if (calcFreeSQEntries(tid) <= 0) { 62610933Snilay@cs.wisc.edu DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n"); 62710933Snilay@cs.wisc.edu source = SQ; 62810933Snilay@cs.wisc.edu incrFullStat(source); 62910933Snilay@cs.wisc.edu break; 63010933Snilay@cs.wisc.edu } 63110239Sbinhpham@cs.rutgers.edu } 63210239Sbinhpham@cs.rutgers.edu 6332292SN/A insts_to_rename.pop_front(); 6342292SN/A 6352292SN/A if (renameStatus[tid] == Unblocking) { 6367720Sgblack@eecs.umich.edu DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 6377720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 6382292SN/A } 6392292SN/A 6402292SN/A if (inst->isSquashed()) { 6417720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 6427720Sgblack@eecs.umich.edu "squashed, skipping.\n", tid, inst->seqNum, 6437720Sgblack@eecs.umich.edu inst->pcState()); 6442292SN/A 6452292SN/A ++renameSquashedInsts; 6462292SN/A 6472292SN/A // Decrement how many instructions are available. 6482292SN/A --insts_available; 6492292SN/A 6502292SN/A continue; 6512292SN/A } 6522292SN/A 6532292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6547720Sgblack@eecs.umich.edu "PC %s.\n", tid, inst->seqNum, inst->pcState()); 6552292SN/A 6569531Sgeoffrey.blake@arm.com // Check here to make sure there are enough destination registers 6579531Sgeoffrey.blake@arm.com // to rename to. Otherwise block. 65810715SRekai.GonzalezAlberquilla@arm.com if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 65910715SRekai.GonzalezAlberquilla@arm.com inst->numFPDestRegs(), 66012109SRekai.GonzalezAlberquilla@arm.com inst->numVecDestRegs(), 66112109SRekai.GonzalezAlberquilla@arm.com inst->numVecElemDestRegs(), 66210935Snilay@cs.wisc.edu inst->numCCDestRegs())) { 6639531Sgeoffrey.blake@arm.com DPRINTF(Rename, "Blocking due to lack of free " 6649531Sgeoffrey.blake@arm.com "physical registers to rename to.\n"); 6659531Sgeoffrey.blake@arm.com blockThisCycle = true; 6669531Sgeoffrey.blake@arm.com insts_to_rename.push_front(inst); 6679531Sgeoffrey.blake@arm.com ++renameFullRegistersEvents; 6689531Sgeoffrey.blake@arm.com 6699531Sgeoffrey.blake@arm.com break; 6709531Sgeoffrey.blake@arm.com } 6719531Sgeoffrey.blake@arm.com 6722292SN/A // Handle serializeAfter/serializeBefore instructions. 6732292SN/A // serializeAfter marks the next instruction as serializeBefore. 6742292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6752292SN/A // is empty. 6762336SN/A 6772336SN/A // In this model, IPR accesses are serialize before 6782336SN/A // instructions, and store conditionals are serialize after 6792336SN/A // instructions. This is mainly due to lack of support for 6802336SN/A // out-of-order operations of either of those classes of 6812336SN/A // instructions. 6822336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6832336SN/A !inst->isSerializeHandled()) { 6842292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6852292SN/A 6862301SN/A if (!inst->isTempSerializeBefore()) { 6872301SN/A renamedSerializing++; 6882292SN/A inst->setSerializeHandled(); 6892301SN/A } else { 6902301SN/A renamedTempSerializing++; 6912301SN/A } 6922292SN/A 6932301SN/A // Change status over to SerializeStall so that other stages know 6942292SN/A // what this is blocked on. 6952301SN/A renameStatus[tid] = SerializeStall; 6962292SN/A 6972301SN/A serializeInst[tid] = inst; 6982292SN/A 6992292SN/A blockThisCycle = true; 7002292SN/A 7012292SN/A break; 7022336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 7032336SN/A !inst->isSerializeHandled()) { 7042292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 7052292SN/A 7062307SN/A renamedSerializing++; 7072307SN/A 7082292SN/A inst->setSerializeHandled(); 7092292SN/A 7102292SN/A serializeAfter(insts_to_rename, tid); 7112292SN/A } 7122292SN/A 7132292SN/A renameSrcRegs(inst, inst->threadNumber); 7142292SN/A 7152292SN/A renameDestRegs(inst, inst->threadNumber); 7162292SN/A 71710239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 71810239Sbinhpham@cs.rutgers.edu loadsInProgress[tid]++; 71910239Sbinhpham@cs.rutgers.edu } 72010239Sbinhpham@cs.rutgers.edu if (inst->isStore()) { 72110239Sbinhpham@cs.rutgers.edu storesInProgress[tid]++; 72210239Sbinhpham@cs.rutgers.edu } 7232292SN/A ++renamed_insts; 72411246Sradhika.jagtap@ARM.com // Notify potential listeners that source and destination registers for 72511246Sradhika.jagtap@ARM.com // this instruction have been renamed. 72611246Sradhika.jagtap@ARM.com ppRename->notify(inst); 7278471SGiacomo.Gabrielli@arm.com 7282292SN/A // Put instruction in rename queue. 7292292SN/A toIEW->insts[toIEWIndex] = inst; 7302292SN/A ++(toIEW->size); 7312292SN/A 7322292SN/A // Increment which instruction we're on. 7332292SN/A ++toIEWIndex; 7342292SN/A 7352292SN/A // Decrement how many instructions are available. 7362292SN/A --insts_available; 7372292SN/A } 7382292SN/A 7392292SN/A instsInProgress[tid] += renamed_insts; 7402307SN/A renameRenamedInsts += renamed_insts; 7412292SN/A 7422292SN/A // If we wrote to the time buffer, record this. 7432292SN/A if (toIEWIndex) { 7442292SN/A wroteToTimeBuffer = true; 7452292SN/A } 7462292SN/A 7472292SN/A // Check if there's any instructions left that haven't yet been renamed. 7482292SN/A // If so then block. 7492292SN/A if (insts_available) { 7502292SN/A blockThisCycle = true; 7512292SN/A } 7522292SN/A 7532292SN/A if (blockThisCycle) { 7542292SN/A block(tid); 7552292SN/A toDecode->renameUnblock[tid] = false; 7562292SN/A } 7572292SN/A} 7582292SN/A 7592292SN/Atemplate<class Impl> 7602292SN/Avoid 7616221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 7622292SN/A{ 7632292SN/A DynInstPtr inst = NULL; 7642292SN/A 7652292SN/A while (!insts[tid].empty()) { 7662292SN/A inst = insts[tid].front(); 7672292SN/A 7682292SN/A insts[tid].pop_front(); 7692292SN/A 7702292SN/A assert(tid == inst->threadNumber); 7712292SN/A 7727720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 7737720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 7742292SN/A 7752307SN/A ++renameSkidInsts; 7762307SN/A 7772292SN/A skidBuffer[tid].push_back(inst); 7782292SN/A } 7792292SN/A 7802292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7813798Sgblack@eecs.umich.edu { 7823798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7833798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 78411321Ssteve.reinhardt@amd.com for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7853798Sgblack@eecs.umich.edu { 7863798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7877720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 7883798Sgblack@eecs.umich.edu (*it)->seqNum); 7893798Sgblack@eecs.umich.edu } 7902292SN/A panic("Skidbuffer Exceeded Max Size"); 7913798Sgblack@eecs.umich.edu } 7922292SN/A} 7932292SN/A 7942292SN/Atemplate <class Impl> 7952292SN/Avoid 7962292SN/ADefaultRename<Impl>::sortInsts() 7972292SN/A{ 7982292SN/A int insts_from_decode = fromDecode->size; 7992292SN/A for (int i = 0; i < insts_from_decode; ++i) { 80013429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &inst = fromDecode->insts[i]; 8012292SN/A insts[inst->threadNumber].push_back(inst); 8029527SMatt.Horsnell@arm.com#if TRACING_ON 8039527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 8049527SMatt.Horsnell@arm.com inst->renameTick = curTick() - inst->fetchTick; 8059527SMatt.Horsnell@arm.com } 8069527SMatt.Horsnell@arm.com#endif 8072292SN/A } 8082292SN/A} 8092292SN/A 8102292SN/Atemplate<class Impl> 8112292SN/Abool 8122292SN/ADefaultRename<Impl>::skidsEmpty() 8132292SN/A{ 8146221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8156221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8162292SN/A 8173867Sbinkertn@umich.edu while (threads != end) { 8186221Snate@binkert.org ThreadID tid = *threads++; 8193867Sbinkertn@umich.edu 8203867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 8212292SN/A return false; 8222292SN/A } 8232292SN/A 8242292SN/A return true; 8252292SN/A} 8262292SN/A 8272292SN/Atemplate<class Impl> 8282292SN/Avoid 8292292SN/ADefaultRename<Impl>::updateStatus() 8302292SN/A{ 8312292SN/A bool any_unblocking = false; 8322292SN/A 8336221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8346221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8352292SN/A 8363867Sbinkertn@umich.edu while (threads != end) { 8376221Snate@binkert.org ThreadID tid = *threads++; 8382292SN/A 8392292SN/A if (renameStatus[tid] == Unblocking) { 8402292SN/A any_unblocking = true; 8412292SN/A break; 8422292SN/A } 8432292SN/A } 8442292SN/A 8452292SN/A // Rename will have activity if it's unblocking. 8462292SN/A if (any_unblocking) { 8472292SN/A if (_status == Inactive) { 8482292SN/A _status = Active; 8492292SN/A 8502292SN/A DPRINTF(Activity, "Activating stage.\n"); 8512292SN/A 8522733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 8532292SN/A } 8542292SN/A } else { 8552292SN/A // If it's not unblocking, then rename will not have any internal 8562292SN/A // activity. Switch it to inactive. 8572292SN/A if (_status == Active) { 8582292SN/A _status = Inactive; 8592292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8602292SN/A 8612733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8622292SN/A } 8632292SN/A } 8642292SN/A} 8652292SN/A 8662292SN/Atemplate <class Impl> 8672292SN/Abool 8686221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8692292SN/A{ 8702292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8712292SN/A 8722292SN/A // Add the current inputs onto the skid buffer, so they can be 8732292SN/A // reprocessed when this stage unblocks. 8742292SN/A skidInsert(tid); 8752292SN/A 8762292SN/A // Only signal backwards to block if the previous stages do not think 8772292SN/A // rename is already blocked. 8782292SN/A if (renameStatus[tid] != Blocked) { 8793798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8803798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8813798Sgblack@eecs.umich.edu // stages to block. 8823798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8832292SN/A toDecode->renameBlock[tid] = true; 8842292SN/A toDecode->renameUnblock[tid] = false; 8852292SN/A wroteToTimeBuffer = true; 8862292SN/A } 8872292SN/A 8882329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8892329SN/A // it would not know to complete the serialize stall. 8902301SN/A if (renameStatus[tid] != SerializeStall) { 8912292SN/A // Set status to Blocked. 8922292SN/A renameStatus[tid] = Blocked; 8932292SN/A return true; 8942292SN/A } 8952292SN/A } 8962292SN/A 8972292SN/A return false; 8982292SN/A} 8992292SN/A 9002292SN/Atemplate <class Impl> 9012292SN/Abool 9026221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 9032292SN/A{ 9042292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 9052292SN/A 9062292SN/A // Rename is done unblocking if the skid buffer is empty. 9072301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 9082292SN/A 9092292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 9102292SN/A 9112292SN/A toDecode->renameUnblock[tid] = true; 9122292SN/A wroteToTimeBuffer = true; 9132292SN/A 9142292SN/A renameStatus[tid] = Running; 9152292SN/A return true; 9162292SN/A } 9172292SN/A 9182292SN/A return false; 9192292SN/A} 9202292SN/A 9212292SN/Atemplate <class Impl> 9222292SN/Avoid 9236221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 9242292SN/A{ 9252980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9262980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 9272292SN/A 9281060SN/A // After a syscall squashes everything, the history buffer may be empty 9291060SN/A // but the ROB may still be squashing instructions. 9301060SN/A // Go through the most recent instructions, undoing the mappings 9311060SN/A // they did and freeing up the registers. 9322292SN/A while (!historyBuffer[tid].empty() && 9339919Ssteve.reinhardt@amd.com hb_it->instSeqNum > squashed_seq_num) { 9342292SN/A assert(hb_it != historyBuffer[tid].end()); 9351062SN/A 9362292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 9379919Ssteve.reinhardt@amd.com "number %i.\n", tid, hb_it->instSeqNum); 9381060SN/A 9399919Ssteve.reinhardt@amd.com // Undo the rename mapping only if it was really a change. 9409919Ssteve.reinhardt@amd.com // Special regs that are not really renamed (like misc regs 9419919Ssteve.reinhardt@amd.com // and the zero reg) can be recognized because the new mapping 9429919Ssteve.reinhardt@amd.com // is the same as the old one. While it would be merely a 9439919Ssteve.reinhardt@amd.com // waste of time to update the rename table, we definitely 9449919Ssteve.reinhardt@amd.com // don't want to put these on the free list. 9459919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 9469919Ssteve.reinhardt@amd.com // Tell the rename map to set the architected register to the 9479919Ssteve.reinhardt@amd.com // previous physical register that it was renamed to. 9489919Ssteve.reinhardt@amd.com renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 9491060SN/A 9509919Ssteve.reinhardt@amd.com // Put the renamed physical register back on the free list. 9519919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->newPhysReg); 9529919Ssteve.reinhardt@amd.com } 9531062SN/A 95411246Sradhika.jagtap@ARM.com // Notify potential listeners that the register mapping needs to be 95511246Sradhika.jagtap@ARM.com // removed because the instruction it was mapped to got squashed. Note 95611246Sradhika.jagtap@ARM.com // that this is done before hb_it is incremented. 95711246Sradhika.jagtap@ARM.com ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum, 95811246Sradhika.jagtap@ARM.com hb_it->newPhysReg)); 95911246Sradhika.jagtap@ARM.com 9602292SN/A historyBuffer[tid].erase(hb_it++); 9611061SN/A 9621062SN/A ++renameUndoneMaps; 9631060SN/A } 96413601Sgiacomo.travaglini@arm.com 96513601Sgiacomo.travaglini@arm.com // Check if we need to change vector renaming mode after squashing 96613601Sgiacomo.travaglini@arm.com cpu->switchRenameMode(tid, freeList); 9671060SN/A} 9681060SN/A 9691060SN/Atemplate<class Impl> 9701060SN/Avoid 9716221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 9721060SN/A{ 9732292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9742292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9752292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9762292SN/A 9772980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9782980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9791060SN/A 9801061SN/A --hb_it; 9811060SN/A 9822292SN/A if (historyBuffer[tid].empty()) { 9832292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9842292SN/A return; 9852292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9862292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9872292SN/A "that a syscall happened recently.\n", tid); 9881060SN/A return; 9891060SN/A } 9901060SN/A 9912292SN/A // Commit all the renames up until (and including) the committed sequence 9922292SN/A // number. Some or even all of the committed instructions may not have 9932292SN/A // rename histories if they did not have destination registers that were 9942292SN/A // renamed. 9952292SN/A while (!historyBuffer[tid].empty() && 9962292SN/A hb_it != historyBuffer[tid].end() && 9979919Ssteve.reinhardt@amd.com hb_it->instSeqNum <= inst_seq_num) { 9981060SN/A 99912105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), " 10002329SN/A "[sn:%lli].\n", 100112106SRekai.GonzalezAlberquilla@arm.com tid, hb_it->prevPhysReg->index(), 100212106SRekai.GonzalezAlberquilla@arm.com hb_it->prevPhysReg->className(), 100312105Snathanael.premillieu@arm.com hb_it->instSeqNum); 10041061SN/A 10059919Ssteve.reinhardt@amd.com // Don't free special phys regs like misc and zero regs, which 10069919Ssteve.reinhardt@amd.com // can be recognized because the new mapping is the same as 10079919Ssteve.reinhardt@amd.com // the old one. 10089919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 10099919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->prevPhysReg); 10109919Ssteve.reinhardt@amd.com } 10119919Ssteve.reinhardt@amd.com 10122292SN/A ++renameCommittedMaps; 10131061SN/A 10142292SN/A historyBuffer[tid].erase(hb_it--); 10151060SN/A } 10161060SN/A} 10171060SN/A 10181061SN/Atemplate <class Impl> 10191061SN/Ainline void 102013429Srekai.gonzalezalberquilla@arm.comDefaultRename<Impl>::renameSrcRegs(const DynInstPtr &inst, ThreadID tid) 10211061SN/A{ 10229919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 10239919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 10241061SN/A unsigned num_src_regs = inst->numSrcRegs(); 10251061SN/A 10261061SN/A // Get the architectual register numbers from the source and 10279919Ssteve.reinhardt@amd.com // operands, and redirect them to the right physical register. 10282292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 102912106SRekai.GonzalezAlberquilla@arm.com const RegId& src_reg = inst->srcRegIdx(src_idx); 103012105Snathanael.premillieu@arm.com PhysRegIdPtr renamed_reg; 10319919Ssteve.reinhardt@amd.com 103212106SRekai.GonzalezAlberquilla@arm.com renamed_reg = map->lookup(tc->flattenRegId(src_reg)); 103312106SRekai.GonzalezAlberquilla@arm.com switch (src_reg.classValue()) { 10349913Ssteve.reinhardt@amd.com case IntRegClass: 10359919Ssteve.reinhardt@amd.com intRenameLookups++; 10369913Ssteve.reinhardt@amd.com break; 10379913Ssteve.reinhardt@amd.com case FloatRegClass: 10389919Ssteve.reinhardt@amd.com fpRenameLookups++; 10399913Ssteve.reinhardt@amd.com break; 104012144Srekai.gonzalezalberquilla@arm.com case VecRegClass: 104113598Sgiacomo.travaglini@arm.com case VecElemClass: 104212144Srekai.gonzalezalberquilla@arm.com vecRenameLookups++; 104312144Srekai.gonzalezalberquilla@arm.com break; 10449920Syasuko.eckert@amd.com case CCRegClass: 10459913Ssteve.reinhardt@amd.com case MiscRegClass: 10469913Ssteve.reinhardt@amd.com break; 10479913Ssteve.reinhardt@amd.com 10489913Ssteve.reinhardt@amd.com default: 104912106SRekai.GonzalezAlberquilla@arm.com panic("Invalid register class: %d.", src_reg.classValue()); 10503773Sgblack@eecs.umich.edu } 10514352Sgblack@eecs.umich.edu 105212105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i" 105312106SRekai.GonzalezAlberquilla@arm.com ", got phys reg %i (%s)\n", tid, 105412106SRekai.GonzalezAlberquilla@arm.com src_reg.className(), src_reg.index(), 105512106SRekai.GonzalezAlberquilla@arm.com renamed_reg->index(), 105612106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 10571061SN/A 10581061SN/A inst->renameSrcReg(src_idx, renamed_reg); 10591061SN/A 10602292SN/A // See if the register is ready or not. 10619919Ssteve.reinhardt@amd.com if (scoreboard->getReg(renamed_reg)) { 106212105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 106312106SRekai.GonzalezAlberquilla@arm.com " is ready.\n", tid, renamed_reg->index(), 106412106SRekai.GonzalezAlberquilla@arm.com renamed_reg->flatIndex(), 106512106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 10661061SN/A 10671061SN/A inst->markSrcRegReady(src_idx); 10684636Sgblack@eecs.umich.edu } else { 106912105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 107012106SRekai.GonzalezAlberquilla@arm.com " is not ready.\n", tid, renamed_reg->index(), 107112106SRekai.GonzalezAlberquilla@arm.com renamed_reg->flatIndex(), 107212106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 10731061SN/A } 10741062SN/A 10751062SN/A ++renameRenameLookups; 10761061SN/A } 10771061SN/A} 10781061SN/A 10791061SN/Atemplate <class Impl> 10801061SN/Ainline void 108113429Srekai.gonzalezalberquilla@arm.comDefaultRename<Impl>::renameDestRegs(const DynInstPtr &inst, ThreadID tid) 10821061SN/A{ 10839919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 10849919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 10851061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10861061SN/A 10872292SN/A // Rename the destination registers. 10882292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 108912106SRekai.GonzalezAlberquilla@arm.com const RegId& dest_reg = inst->destRegIdx(dest_idx); 10909919Ssteve.reinhardt@amd.com typename RenameMap::RenameInfo rename_result; 10919919Ssteve.reinhardt@amd.com 109212106SRekai.GonzalezAlberquilla@arm.com RegId flat_dest_regid = tc->flattenRegId(dest_reg); 10939913Ssteve.reinhardt@amd.com 109412106SRekai.GonzalezAlberquilla@arm.com rename_result = map->rename(flat_dest_regid); 10959913Ssteve.reinhardt@amd.com 109612106SRekai.GonzalezAlberquilla@arm.com inst->flattenDestReg(dest_idx, flat_dest_regid); 10971061SN/A 10989919Ssteve.reinhardt@amd.com // Mark Scoreboard entry as not ready 10999916Ssteve.reinhardt@amd.com scoreboard->unsetReg(rename_result.first); 11001062SN/A 110112105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical " 110212106SRekai.GonzalezAlberquilla@arm.com "reg %i (%i).\n", tid, dest_reg.index(), 110312106SRekai.GonzalezAlberquilla@arm.com dest_reg.className(), 110412106SRekai.GonzalezAlberquilla@arm.com rename_result.first->index(), 110512106SRekai.GonzalezAlberquilla@arm.com rename_result.first->flatIndex()); 11061062SN/A 11072292SN/A // Record the rename information so that a history can be kept. 110812106SRekai.GonzalezAlberquilla@arm.com RenameHistory hb_entry(inst->seqNum, flat_dest_regid, 11092292SN/A rename_result.first, 11102292SN/A rename_result.second); 11111062SN/A 11122292SN/A historyBuffer[tid].push_front(hb_entry); 11131062SN/A 11142935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 11152935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 11162935Sksewell@umich.edu historyBuffer[tid].size(), 11172292SN/A (*historyBuffer[tid].begin()).instSeqNum); 11181062SN/A 11192292SN/A // Tell the instruction to rename the appropriate destination 11202292SN/A // register (dest_idx) to the new physical register 11212292SN/A // (rename_result.first), and record the previous physical 11222292SN/A // register that the same logical register was renamed to 11232292SN/A // (rename_result.second). 11242292SN/A inst->renameDestReg(dest_idx, 11252292SN/A rename_result.first, 11262292SN/A rename_result.second); 11271062SN/A 11282292SN/A ++renameRenamedOperands; 11291061SN/A } 11301061SN/A} 11311061SN/A 11321061SN/Atemplate <class Impl> 11331061SN/Ainline int 11346221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 11351061SN/A{ 11362292SN/A int num_free = freeEntries[tid].robEntries - 11372292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11382292SN/A 11392292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 11402292SN/A 11412292SN/A return num_free; 11421061SN/A} 11431061SN/A 11441061SN/Atemplate <class Impl> 11451061SN/Ainline int 11466221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 11471061SN/A{ 11482292SN/A int num_free = freeEntries[tid].iqEntries - 11492292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11502292SN/A 11512292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 11522292SN/A 11532292SN/A return num_free; 11542292SN/A} 11552292SN/A 11562292SN/Atemplate <class Impl> 11572292SN/Ainline int 115810239Sbinhpham@cs.rutgers.eduDefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 11592292SN/A{ 116010239Sbinhpham@cs.rutgers.edu int num_free = freeEntries[tid].lqEntries - 116110935Snilay@cs.wisc.edu (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 116210239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 116310239Sbinhpham@cs.rutgers.edu "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 116410239Sbinhpham@cs.rutgers.edu loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 116510239Sbinhpham@cs.rutgers.edu return num_free; 116610239Sbinhpham@cs.rutgers.edu} 11672292SN/A 116810239Sbinhpham@cs.rutgers.edutemplate <class Impl> 116910239Sbinhpham@cs.rutgers.eduinline int 117010239Sbinhpham@cs.rutgers.eduDefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 117110239Sbinhpham@cs.rutgers.edu{ 117210239Sbinhpham@cs.rutgers.edu int num_free = freeEntries[tid].sqEntries - 117310935Snilay@cs.wisc.edu (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 117410239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 117510239Sbinhpham@cs.rutgers.edu "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 117610239Sbinhpham@cs.rutgers.edu storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 117710239Sbinhpham@cs.rutgers.edu return num_free; 11782292SN/A} 11792292SN/A 11802292SN/Atemplate <class Impl> 11812292SN/Aunsigned 11822292SN/ADefaultRename<Impl>::validInsts() 11832292SN/A{ 11842292SN/A unsigned inst_count = 0; 11852292SN/A 11862292SN/A for (int i=0; i<fromDecode->size; i++) { 11872731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11882292SN/A inst_count++; 11892292SN/A } 11902292SN/A 11912292SN/A return inst_count; 11922292SN/A} 11932292SN/A 11942292SN/Atemplate <class Impl> 11952292SN/Avoid 11966221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 11972292SN/A{ 11982292SN/A if (fromIEW->iewBlock[tid]) { 11992292SN/A stalls[tid].iew = true; 12002292SN/A } 12012292SN/A 12022292SN/A if (fromIEW->iewUnblock[tid]) { 12032292SN/A assert(stalls[tid].iew); 12042292SN/A stalls[tid].iew = false; 12052292SN/A } 12062292SN/A} 12072292SN/A 12082292SN/Atemplate <class Impl> 12092292SN/Abool 12106221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 12112292SN/A{ 12122292SN/A bool ret_val = false; 12132292SN/A 12142292SN/A if (stalls[tid].iew) { 12152292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 12162292SN/A ret_val = true; 12172292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 12182292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 12192292SN/A ret_val = true; 12202292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 12212292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 12222292SN/A ret_val = true; 122310239Sbinhpham@cs.rutgers.edu } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { 12242292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 12252292SN/A ret_val = true; 12262292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 12272292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 12282292SN/A ret_val = true; 12292301SN/A } else if (renameStatus[tid] == SerializeStall && 12302292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 12312301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 12322292SN/A "empty.\n", 12332292SN/A tid); 12342292SN/A ret_val = true; 12352292SN/A } 12362292SN/A 12372292SN/A return ret_val; 12382292SN/A} 12392292SN/A 12402292SN/Atemplate <class Impl> 12412292SN/Avoid 12426221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 12432292SN/A{ 12448607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedIQ) 12458607Sgblack@eecs.umich.edu freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 12462292SN/A 124710239Sbinhpham@cs.rutgers.edu if (fromIEW->iewInfo[tid].usedLSQ) { 124810239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 124910239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 125010239Sbinhpham@cs.rutgers.edu } 12512292SN/A 12522292SN/A if (fromCommit->commitInfo[tid].usedROB) { 12532292SN/A freeEntries[tid].robEntries = 12542292SN/A fromCommit->commitInfo[tid].freeROBEntries; 12552292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12562292SN/A } 12572292SN/A 125810239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " 125912109SRekai.GonzalezAlberquilla@arm.com "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i)\n", 12602292SN/A tid, 12612292SN/A freeEntries[tid].iqEntries, 12622292SN/A freeEntries[tid].robEntries, 126310239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries, 126412109SRekai.GonzalezAlberquilla@arm.com freeEntries[tid].sqEntries, 126512109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeEntries(), 126612109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeIntEntries(), 126712109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeFloatEntries(), 126812109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeVecEntries(), 126912109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeCCEntries()); 12702292SN/A 12712292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12722292SN/A tid, instsInProgress[tid]); 12732292SN/A} 12742292SN/A 12752292SN/Atemplate <class Impl> 12762292SN/Abool 12776221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 12782292SN/A{ 12792292SN/A // Check if there's a squash signal, squash if there is 12802292SN/A // Check stall signals, block if necessary. 12812292SN/A // If status was blocked 12822292SN/A // check if stall conditions have passed 12832292SN/A // if so then go to unblocking 12842292SN/A // If status was Squashing 12852292SN/A // check if squashing is not high. Switch to running this cycle. 12862301SN/A // If status was serialize stall 12872292SN/A // check if ROB is empty and no insts are in flight to the ROB 12882292SN/A 12892292SN/A readFreeEntries(tid); 12902292SN/A readStallSignals(tid); 12912292SN/A 12922292SN/A if (fromCommit->commitInfo[tid].squash) { 12932292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12942292SN/A "commit.\n", tid); 12952292SN/A 12964632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 12972292SN/A 12982292SN/A return true; 12992292SN/A } 13002292SN/A 13012292SN/A if (checkStall(tid)) { 13022292SN/A return block(tid); 13032292SN/A } 13042292SN/A 13052292SN/A if (renameStatus[tid] == Blocked) { 13062292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 13072292SN/A tid); 13082292SN/A 13092292SN/A renameStatus[tid] = Unblocking; 13102292SN/A 13112292SN/A unblock(tid); 13122292SN/A 13132292SN/A return true; 13142292SN/A } 13152292SN/A 13162292SN/A if (renameStatus[tid] == Squashing) { 13172292SN/A // Switch status to running if rename isn't being told to block or 13182292SN/A // squash this cycle. 13193798Sgblack@eecs.umich.edu if (resumeSerialize) { 13203798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 13213798Sgblack@eecs.umich.edu tid); 13222292SN/A 13233798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 13243798Sgblack@eecs.umich.edu return true; 13253798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 13263798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 13273798Sgblack@eecs.umich.edu tid); 13283798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 13293798Sgblack@eecs.umich.edu return true; 13303798Sgblack@eecs.umich.edu } else { 13313788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 13323788Sgblack@eecs.umich.edu tid); 13332292SN/A 13343788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 13353788Sgblack@eecs.umich.edu return false; 13363788Sgblack@eecs.umich.edu } 13372292SN/A } 13382292SN/A 13392301SN/A if (renameStatus[tid] == SerializeStall) { 13402292SN/A // Stall ends once the ROB is free. 13412301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 13422292SN/A "unblocking.\n", tid); 13432292SN/A 13442301SN/A DynInstPtr serial_inst = serializeInst[tid]; 13452292SN/A 13462292SN/A renameStatus[tid] = Unblocking; 13472292SN/A 13482292SN/A unblock(tid); 13492292SN/A 13502292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 13517720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 13522292SN/A 13532292SN/A // Put instruction into queue here. 13542301SN/A serial_inst->clearSerializeBefore(); 13552292SN/A 13562292SN/A if (!skidBuffer[tid].empty()) { 13572301SN/A skidBuffer[tid].push_front(serial_inst); 13582292SN/A } else { 13592301SN/A insts[tid].push_front(serial_inst); 13602292SN/A } 13612292SN/A 13622292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13632703Sktlim@umich.edu " Adding to front of list.\n", tid); 13642292SN/A 13652301SN/A serializeInst[tid] = NULL; 13662292SN/A 13672292SN/A return true; 13682292SN/A } 13692292SN/A 13702292SN/A // If we've reached this point, we have not gotten any signals that 13712292SN/A // cause rename to change its status. Rename remains the same as before. 13722292SN/A return false; 13731061SN/A} 13741061SN/A 13751060SN/Atemplate<class Impl> 13761060SN/Avoid 13776221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 13781060SN/A{ 13792292SN/A if (inst_list.empty()) { 13802292SN/A // Mark a bit to say that I must serialize on the next instruction. 13812292SN/A serializeOnNextInst[tid] = true; 13821060SN/A return; 13831060SN/A } 13841060SN/A 13852292SN/A // Set the next instruction as serializing. 13862292SN/A inst_list.front()->setSerializeBefore(); 13872292SN/A} 13882292SN/A 13892292SN/Atemplate <class Impl> 13902292SN/Ainline void 13912292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13922292SN/A{ 13932292SN/A switch (source) { 13942292SN/A case ROB: 13952292SN/A ++renameROBFullEvents; 13962292SN/A break; 13972292SN/A case IQ: 13982292SN/A ++renameIQFullEvents; 13992292SN/A break; 140010239Sbinhpham@cs.rutgers.edu case LQ: 140110239Sbinhpham@cs.rutgers.edu ++renameLQFullEvents; 140210239Sbinhpham@cs.rutgers.edu break; 140310239Sbinhpham@cs.rutgers.edu case SQ: 140410239Sbinhpham@cs.rutgers.edu ++renameSQFullEvents; 14052292SN/A break; 14062292SN/A default: 14072292SN/A panic("Rename full stall stat should be incremented for a reason!"); 14082292SN/A break; 14091060SN/A } 14102292SN/A} 14111060SN/A 14122292SN/Atemplate <class Impl> 14132292SN/Avoid 14142292SN/ADefaultRename<Impl>::dumpHistory() 14152292SN/A{ 14162980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 14171060SN/A 14186221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 14191060SN/A 14206221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 14211060SN/A 14226221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 142312105Snathanael.premillieu@arm.com cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:" 142412105Snathanael.premillieu@arm.com " %i[%s] Old phys reg: %i[%s]\n", 142512105Snathanael.premillieu@arm.com (*buf_it).instSeqNum, 142612106SRekai.GonzalezAlberquilla@arm.com (*buf_it).archReg.className(), 142712106SRekai.GonzalezAlberquilla@arm.com (*buf_it).archReg.index(), 142812106SRekai.GonzalezAlberquilla@arm.com (*buf_it).newPhysReg->index(), 142912106SRekai.GonzalezAlberquilla@arm.com (*buf_it).newPhysReg->className(), 143012106SRekai.GonzalezAlberquilla@arm.com (*buf_it).prevPhysReg->index(), 143112106SRekai.GonzalezAlberquilla@arm.com (*buf_it).prevPhysReg->className()); 14321060SN/A 14332292SN/A buf_it++; 14341062SN/A } 14351060SN/A } 14361060SN/A} 14379944Smatt.horsnell@ARM.com 14389944Smatt.horsnell@ARM.com#endif//__CPU_O3_RENAME_IMPL_HH__ 1439