rename.hh revision 9444
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_O3_RENAME_HH__ 44#define __CPU_O3_RENAME_HH__ 45 46#include <list> 47 48#include "base/statistics.hh" 49#include "config/the_isa.hh" 50#include "cpu/timebuf.hh" 51 52struct DerivO3CPUParams; 53 54/** 55 * DefaultRename handles both single threaded and SMT rename. Its 56 * width is specified by the parameters; each cycle it tries to rename 57 * that many instructions. It holds onto the rename history of all 58 * instructions with destination registers, storing the 59 * arch. register, the new physical register, and the old physical 60 * register, to allow for undoing of mappings if squashing happens, or 61 * freeing up registers upon commit. Rename handles blocking if the 62 * ROB, IQ, or LSQ is going to be full. Rename also handles barriers, 63 * and does so by stalling on the instruction until the ROB is empty 64 * and there are no instructions in flight to the ROB. 65 */ 66template<class Impl> 67class DefaultRename 68{ 69 public: 70 // Typedefs from the Impl. 71 typedef typename Impl::CPUPol CPUPol; 72 typedef typename Impl::DynInstPtr DynInstPtr; 73 typedef typename Impl::O3CPU O3CPU; 74 75 // Typedefs from the CPUPol 76 typedef typename CPUPol::DecodeStruct DecodeStruct; 77 typedef typename CPUPol::RenameStruct RenameStruct; 78 typedef typename CPUPol::TimeStruct TimeStruct; 79 typedef typename CPUPol::FreeList FreeList; 80 typedef typename CPUPol::RenameMap RenameMap; 81 // These are used only for initialization. 82 typedef typename CPUPol::IEW IEW; 83 typedef typename CPUPol::Commit Commit; 84 85 // Typedefs from the ISA. 86 typedef TheISA::RegIndex RegIndex; 87 88 // A list is used to queue the instructions. Barrier insts must 89 // be added to the front of the list, which is the only reason for 90 // using a list instead of a queue. (Most other stages use a 91 // queue) 92 typedef std::list<DynInstPtr> InstQueue; 93 typedef typename std::list<DynInstPtr>::iterator ListIt; 94 95 public: 96 /** Overall rename status. Used to determine if the CPU can 97 * deschedule itself due to a lack of activity. 98 */ 99 enum RenameStatus { 100 Active, 101 Inactive 102 }; 103 104 /** Individual thread status. */ 105 enum ThreadStatus { 106 Running, 107 Idle, 108 StartSquash, 109 Squashing, 110 Blocked, 111 Unblocking, 112 SerializeStall 113 }; 114 115 private: 116 /** Rename status. */ 117 RenameStatus _status; 118 119 /** Per-thread status. */ 120 ThreadStatus renameStatus[Impl::MaxThreads]; 121 122 public: 123 /** DefaultRename constructor. */ 124 DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params); 125 126 /** Returns the name of rename. */ 127 std::string name() const; 128 129 /** Registers statistics. */ 130 void regStats(); 131 132 /** Sets the main backwards communication time buffer pointer. */ 133 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 134 135 /** Sets pointer to time buffer used to communicate to the next stage. */ 136 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 137 138 /** Sets pointer to time buffer coming from decode. */ 139 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 140 141 /** Sets pointer to IEW stage. Used only for initialization. */ 142 void setIEWStage(IEW *iew_stage) 143 { iew_ptr = iew_stage; } 144 145 /** Sets pointer to commit stage. Used only for initialization. */ 146 void setCommitStage(Commit *commit_stage) 147 { commit_ptr = commit_stage; } 148 149 private: 150 /** Pointer to IEW stage. Used only for initialization. */ 151 IEW *iew_ptr; 152 153 /** Pointer to commit stage. Used only for initialization. */ 154 Commit *commit_ptr; 155 156 public: 157 /** Initializes variables for the stage. */ 158 void startupStage(); 159 160 /** Sets pointer to list of active threads. */ 161 void setActiveThreads(std::list<ThreadID> *at_ptr); 162 163 /** Sets pointer to rename maps (per-thread structures). */ 164 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 165 166 /** Sets pointer to the free list. */ 167 void setFreeList(FreeList *fl_ptr); 168 169 /** Sets pointer to the scoreboard. */ 170 void setScoreboard(Scoreboard *_scoreboard); 171 172 /** Perform sanity checks after a drain. */ 173 void drainSanityCheck() const; 174 175 /** Has the stage drained? */ 176 bool isDrained() const; 177 178 /** Takes over from another CPU's thread. */ 179 void takeOverFrom(); 180 181 /** Squashes all instructions in a thread. */ 182 void squash(const InstSeqNum &squash_seq_num, ThreadID tid); 183 184 /** Ticks rename, which processes all input signals and attempts to rename 185 * as many instructions as possible. 186 */ 187 void tick(); 188 189 /** Debugging function used to dump history buffer of renamings. */ 190 void dumpHistory(); 191 192 private: 193 /** Reset this pipeline stage */ 194 void resetStage(); 195 196 /** Determines what to do based on rename's current status. 197 * @param status_change rename() sets this variable if there was a status 198 * change (ie switching from blocking to unblocking). 199 * @param tid Thread id to rename instructions from. 200 */ 201 void rename(bool &status_change, ThreadID tid); 202 203 /** Renames instructions for the given thread. Also handles serializing 204 * instructions. 205 */ 206 void renameInsts(ThreadID tid); 207 208 /** Inserts unused instructions from a given thread into the skid buffer, 209 * to be renamed once rename unblocks. 210 */ 211 void skidInsert(ThreadID tid); 212 213 /** Separates instructions from decode into individual lists of instructions 214 * sorted by thread. 215 */ 216 void sortInsts(); 217 218 /** Returns if all of the skid buffers are empty. */ 219 bool skidsEmpty(); 220 221 /** Updates overall rename status based on all of the threads' statuses. */ 222 void updateStatus(); 223 224 /** Switches rename to blocking, and signals back that rename has become 225 * blocked. 226 * @return Returns true if there is a status change. 227 */ 228 bool block(ThreadID tid); 229 230 /** Switches rename to unblocking if the skid buffer is empty, and signals 231 * back that rename has unblocked. 232 * @return Returns true if there is a status change. 233 */ 234 bool unblock(ThreadID tid); 235 236 /** Executes actual squash, removing squashed instructions. */ 237 void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid); 238 239 /** Removes a committed instruction's rename history. */ 240 void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid); 241 242 /** Renames the source registers of an instruction. */ 243 inline void renameSrcRegs(DynInstPtr &inst, ThreadID tid); 244 245 /** Renames the destination registers of an instruction. */ 246 inline void renameDestRegs(DynInstPtr &inst, ThreadID tid); 247 248 /** Calculates the number of free ROB entries for a specific thread. */ 249 inline int calcFreeROBEntries(ThreadID tid); 250 251 /** Calculates the number of free IQ entries for a specific thread. */ 252 inline int calcFreeIQEntries(ThreadID tid); 253 254 /** Calculates the number of free LSQ entries for a specific thread. */ 255 inline int calcFreeLSQEntries(ThreadID tid); 256 257 /** Returns the number of valid instructions coming from decode. */ 258 unsigned validInsts(); 259 260 /** Reads signals telling rename to block/unblock. */ 261 void readStallSignals(ThreadID tid); 262 263 /** Checks if any stages are telling rename to block. */ 264 bool checkStall(ThreadID tid); 265 266 /** Gets the number of free entries for a specific thread. */ 267 void readFreeEntries(ThreadID tid); 268 269 /** Checks the signals and updates the status. */ 270 bool checkSignalsAndUpdate(ThreadID tid); 271 272 /** Either serializes on the next instruction available in the InstQueue, 273 * or records that it must serialize on the next instruction to enter 274 * rename. 275 * @param inst_list The list of younger, unprocessed instructions for the 276 * thread that has the serializeAfter instruction. 277 * @param tid The thread id. 278 */ 279 void serializeAfter(InstQueue &inst_list, ThreadID tid); 280 281 /** Holds the information for each destination register rename. It holds 282 * the instruction's sequence number, the arch register, the old physical 283 * register for that arch. register, and the new physical register. 284 */ 285 struct RenameHistory { 286 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 287 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 288 : instSeqNum(_instSeqNum), archReg(_archReg), 289 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg) 290 { 291 } 292 293 /** The sequence number of the instruction that renamed. */ 294 InstSeqNum instSeqNum; 295 /** The architectural register index that was renamed. */ 296 RegIndex archReg; 297 /** The new physical register that the arch. register is renamed to. */ 298 PhysRegIndex newPhysReg; 299 /** The old physical register that the arch. register was renamed to. */ 300 PhysRegIndex prevPhysReg; 301 }; 302 303 /** A per-thread list of all destination register renames, used to either 304 * undo rename mappings or free old physical registers. 305 */ 306 std::list<RenameHistory> historyBuffer[Impl::MaxThreads]; 307 308 /** Pointer to CPU. */ 309 O3CPU *cpu; 310 311 /** Pointer to main time buffer used for backwards communication. */ 312 TimeBuffer<TimeStruct> *timeBuffer; 313 314 /** Wire to get IEW's output from backwards time buffer. */ 315 typename TimeBuffer<TimeStruct>::wire fromIEW; 316 317 /** Wire to get commit's output from backwards time buffer. */ 318 typename TimeBuffer<TimeStruct>::wire fromCommit; 319 320 /** Wire to write infromation heading to previous stages. */ 321 typename TimeBuffer<TimeStruct>::wire toDecode; 322 323 /** Rename instruction queue. */ 324 TimeBuffer<RenameStruct> *renameQueue; 325 326 /** Wire to write any information heading to IEW. */ 327 typename TimeBuffer<RenameStruct>::wire toIEW; 328 329 /** Decode instruction queue interface. */ 330 TimeBuffer<DecodeStruct> *decodeQueue; 331 332 /** Wire to get decode's output from decode queue. */ 333 typename TimeBuffer<DecodeStruct>::wire fromDecode; 334 335 /** Queue of all instructions coming from decode this cycle. */ 336 InstQueue insts[Impl::MaxThreads]; 337 338 /** Skid buffer between rename and decode. */ 339 InstQueue skidBuffer[Impl::MaxThreads]; 340 341 /** Rename map interface. */ 342 RenameMap *renameMap[Impl::MaxThreads]; 343 344 /** Free list interface. */ 345 FreeList *freeList; 346 347 /** Pointer to the list of active threads. */ 348 std::list<ThreadID> *activeThreads; 349 350 /** Pointer to the scoreboard. */ 351 Scoreboard *scoreboard; 352 353 /** Count of instructions in progress that have been sent off to the IQ 354 * and ROB, but are not yet included in their occupancy counts. 355 */ 356 int instsInProgress[Impl::MaxThreads]; 357 358 /** Variable that tracks if decode has written to the time buffer this 359 * cycle. Used to tell CPU if there is activity this cycle. 360 */ 361 bool wroteToTimeBuffer; 362 363 /** Structures whose free entries impact the amount of instructions that 364 * can be renamed. 365 */ 366 struct FreeEntries { 367 unsigned iqEntries; 368 unsigned lsqEntries; 369 unsigned robEntries; 370 }; 371 372 /** Per-thread tracking of the number of free entries of back-end 373 * structures. 374 */ 375 FreeEntries freeEntries[Impl::MaxThreads]; 376 377 /** Records if the ROB is empty. In SMT mode the ROB may be dynamically 378 * partitioned between threads, so the ROB must tell rename when it is 379 * empty. 380 */ 381 bool emptyROB[Impl::MaxThreads]; 382 383 /** Source of possible stalls. */ 384 struct Stalls { 385 bool iew; 386 bool commit; 387 }; 388 389 /** Tracks which stages are telling decode to stall. */ 390 Stalls stalls[Impl::MaxThreads]; 391 392 /** The serialize instruction that rename has stalled on. */ 393 DynInstPtr serializeInst[Impl::MaxThreads]; 394 395 /** Records if rename needs to serialize on the next instruction for any 396 * thread. 397 */ 398 bool serializeOnNextInst[Impl::MaxThreads]; 399 400 /** Delay between iew and rename, in ticks. */ 401 int iewToRenameDelay; 402 403 /** Delay between decode and rename, in ticks. */ 404 int decodeToRenameDelay; 405 406 /** Delay between commit and rename, in ticks. */ 407 unsigned commitToRenameDelay; 408 409 /** Rename width, in instructions. */ 410 unsigned renameWidth; 411 412 /** Commit width, in instructions. Used so rename knows how many 413 * instructions might have freed registers in the previous cycle. 414 */ 415 unsigned commitWidth; 416 417 /** The index of the instruction in the time buffer to IEW that rename is 418 * currently using. 419 */ 420 unsigned toIEWIndex; 421 422 /** Whether or not rename needs to block this cycle. */ 423 bool blockThisCycle; 424 425 /** Whether or not rename needs to resume a serialize instruction 426 * after squashing. */ 427 bool resumeSerialize; 428 429 /** Whether or not rename needs to resume clearing out the skidbuffer 430 * after squashing. */ 431 bool resumeUnblocking; 432 433 /** The number of threads active in rename. */ 434 ThreadID numThreads; 435 436 /** The maximum skid buffer size. */ 437 unsigned skidBufferMax; 438 439 PhysRegIndex maxPhysicalRegs; 440 441 /** Enum to record the source of a structure full stall. Can come from 442 * either ROB, IQ, LSQ, and it is priortized in that order. 443 */ 444 enum FullSource { 445 ROB, 446 IQ, 447 LSQ, 448 NONE 449 }; 450 451 /** Function used to increment the stat that corresponds to the source of 452 * the stall. 453 */ 454 inline void incrFullStat(const FullSource &source); 455 456 /** Stat for total number of cycles spent squashing. */ 457 Stats::Scalar renameSquashCycles; 458 /** Stat for total number of cycles spent idle. */ 459 Stats::Scalar renameIdleCycles; 460 /** Stat for total number of cycles spent blocking. */ 461 Stats::Scalar renameBlockCycles; 462 /** Stat for total number of cycles spent stalling for a serializing inst. */ 463 Stats::Scalar renameSerializeStallCycles; 464 /** Stat for total number of cycles spent running normally. */ 465 Stats::Scalar renameRunCycles; 466 /** Stat for total number of cycles spent unblocking. */ 467 Stats::Scalar renameUnblockCycles; 468 /** Stat for total number of renamed instructions. */ 469 Stats::Scalar renameRenamedInsts; 470 /** Stat for total number of squashed instructions that rename discards. */ 471 Stats::Scalar renameSquashedInsts; 472 /** Stat for total number of times that the ROB starts a stall in rename. */ 473 Stats::Scalar renameROBFullEvents; 474 /** Stat for total number of times that the IQ starts a stall in rename. */ 475 Stats::Scalar renameIQFullEvents; 476 /** Stat for total number of times that the LSQ starts a stall in rename. */ 477 Stats::Scalar renameLSQFullEvents; 478 /** Stat for total number of times that rename runs out of free registers 479 * to use to rename. */ 480 Stats::Scalar renameFullRegistersEvents; 481 /** Stat for total number of renamed destination registers. */ 482 Stats::Scalar renameRenamedOperands; 483 /** Stat for total number of source register rename lookups. */ 484 Stats::Scalar renameRenameLookups; 485 Stats::Scalar intRenameLookups; 486 Stats::Scalar fpRenameLookups; 487 /** Stat for total number of committed renaming mappings. */ 488 Stats::Scalar renameCommittedMaps; 489 /** Stat for total number of mappings that were undone due to a squash. */ 490 Stats::Scalar renameUndoneMaps; 491 /** Number of serialize instructions handled. */ 492 Stats::Scalar renamedSerializing; 493 /** Number of instructions marked as temporarily serializing. */ 494 Stats::Scalar renamedTempSerializing; 495 /** Number of instructions inserted into skid buffers. */ 496 Stats::Scalar renameSkidInsts; 497}; 498 499#endif // __CPU_O3_RENAME_HH__ 500