rename.hh revision 9427:ddf45c1d54d4
12735Sktlim@umich.edu/* 210319SAndreas.Sandberg@ARM.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 310319SAndreas.Sandberg@ARM.com * All rights reserved. 410319SAndreas.Sandberg@ARM.com * 510319SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 610319SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 710319SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 810319SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 910319SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 1010319SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 1110319SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 1210319SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 1310319SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 142735Sktlim@umich.edu * this software without specific prior written permission. 152735Sktlim@umich.edu * 162735Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172735Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182735Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192735Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202735Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212735Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222735Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232735Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242735Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252735Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262735Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272735Sktlim@umich.edu * 282735Sktlim@umich.edu * Authors: Kevin Lim 292735Sktlim@umich.edu */ 302735Sktlim@umich.edu 312735Sktlim@umich.edu#ifndef __CPU_O3_RENAME_HH__ 322735Sktlim@umich.edu#define __CPU_O3_RENAME_HH__ 332735Sktlim@umich.edu 342735Sktlim@umich.edu#include <list> 352735Sktlim@umich.edu 362735Sktlim@umich.edu#include "base/statistics.hh" 372735Sktlim@umich.edu#include "config/the_isa.hh" 382735Sktlim@umich.edu#include "cpu/timebuf.hh" 392735Sktlim@umich.edu 402735Sktlim@umich.edustruct DerivO3CPUParams; 4110319SAndreas.Sandberg@ARM.com 422735Sktlim@umich.edu/** 432735Sktlim@umich.edu * DefaultRename handles both single threaded and SMT rename. Its 4410319SAndreas.Sandberg@ARM.com * width is specified by the parameters; each cycle it tries to rename 4510319SAndreas.Sandberg@ARM.com * that many instructions. It holds onto the rename history of all 4610319SAndreas.Sandberg@ARM.com * instructions with destination registers, storing the 4710319SAndreas.Sandberg@ARM.com * arch. register, the new physical register, and the old physical 4810319SAndreas.Sandberg@ARM.com * register, to allow for undoing of mappings if squashing happens, or 4910319SAndreas.Sandberg@ARM.com * freeing up registers upon commit. Rename handles blocking if the 5010319SAndreas.Sandberg@ARM.com * ROB, IQ, or LSQ is going to be full. Rename also handles barriers, 5110319SAndreas.Sandberg@ARM.com * and does so by stalling on the instruction until the ROB is empty 5210319SAndreas.Sandberg@ARM.com * and there are no instructions in flight to the ROB. 532735Sktlim@umich.edu */ 542735Sktlim@umich.edutemplate<class Impl> 5510319SAndreas.Sandberg@ARM.comclass DefaultRename 5610319SAndreas.Sandberg@ARM.com{ 5710319SAndreas.Sandberg@ARM.com public: 5810319SAndreas.Sandberg@ARM.com // Typedefs from the Impl. 5910319SAndreas.Sandberg@ARM.com typedef typename Impl::CPUPol CPUPol; 6010319SAndreas.Sandberg@ARM.com typedef typename Impl::DynInstPtr DynInstPtr; 6110319SAndreas.Sandberg@ARM.com typedef typename Impl::O3CPU O3CPU; 6210319SAndreas.Sandberg@ARM.com 6310319SAndreas.Sandberg@ARM.com // Typedefs from the CPUPol 6410319SAndreas.Sandberg@ARM.com typedef typename CPUPol::DecodeStruct DecodeStruct; 6510319SAndreas.Sandberg@ARM.com typedef typename CPUPol::RenameStruct RenameStruct; 6610319SAndreas.Sandberg@ARM.com typedef typename CPUPol::TimeStruct TimeStruct; 6710319SAndreas.Sandberg@ARM.com typedef typename CPUPol::FreeList FreeList; 6810319SAndreas.Sandberg@ARM.com typedef typename CPUPol::RenameMap RenameMap; 692735Sktlim@umich.edu // These are used only for initialization. 702735Sktlim@umich.edu typedef typename CPUPol::IEW IEW; 7110319SAndreas.Sandberg@ARM.com typedef typename CPUPol::Commit Commit; 7210319SAndreas.Sandberg@ARM.com 7310319SAndreas.Sandberg@ARM.com // Typedefs from the ISA. 7410319SAndreas.Sandberg@ARM.com typedef TheISA::RegIndex RegIndex; 7510319SAndreas.Sandberg@ARM.com 7610319SAndreas.Sandberg@ARM.com // A list is used to queue the instructions. Barrier insts must 7710319SAndreas.Sandberg@ARM.com // be added to the front of the list, which is the only reason for 7810319SAndreas.Sandberg@ARM.com // using a list instead of a queue. (Most other stages use a 7910319SAndreas.Sandberg@ARM.com // queue) 8010319SAndreas.Sandberg@ARM.com typedef std::list<DynInstPtr> InstQueue; 8110319SAndreas.Sandberg@ARM.com typedef typename std::list<DynInstPtr>::iterator ListIt; 8210319SAndreas.Sandberg@ARM.com 8310319SAndreas.Sandberg@ARM.com public: 8410319SAndreas.Sandberg@ARM.com /** Overall rename status. Used to determine if the CPU can 8510319SAndreas.Sandberg@ARM.com * deschedule itself due to a lack of activity. 862735Sktlim@umich.edu */ 872735Sktlim@umich.edu enum RenameStatus { 8810319SAndreas.Sandberg@ARM.com Active, 8910319SAndreas.Sandberg@ARM.com Inactive 9010319SAndreas.Sandberg@ARM.com }; 9110319SAndreas.Sandberg@ARM.com 9210319SAndreas.Sandberg@ARM.com /** Individual thread status. */ 9310319SAndreas.Sandberg@ARM.com enum ThreadStatus { 9410319SAndreas.Sandberg@ARM.com Running, 9510319SAndreas.Sandberg@ARM.com Idle, 9610319SAndreas.Sandberg@ARM.com StartSquash, 9710319SAndreas.Sandberg@ARM.com Squashing, 9810319SAndreas.Sandberg@ARM.com Blocked, 9910319SAndreas.Sandberg@ARM.com Unblocking, 10010319SAndreas.Sandberg@ARM.com SerializeStall 1012735Sktlim@umich.edu }; 1022735Sktlim@umich.edu 10310319SAndreas.Sandberg@ARM.com private: 1042735Sktlim@umich.edu /** Rename status. */ 1052735Sktlim@umich.edu RenameStatus _status; 1062735Sktlim@umich.edu 10710319SAndreas.Sandberg@ARM.com /** Per-thread status. */ 10810319SAndreas.Sandberg@ARM.com ThreadStatus renameStatus[Impl::MaxThreads]; 1092735Sktlim@umich.edu 1102735Sktlim@umich.edu public: 11110319SAndreas.Sandberg@ARM.com /** DefaultRename constructor. */ 11210319SAndreas.Sandberg@ARM.com DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params); 1132735Sktlim@umich.edu 1142735Sktlim@umich.edu /** Returns the name of rename. */ 1152735Sktlim@umich.edu std::string name() const; 11610319SAndreas.Sandberg@ARM.com 11710319SAndreas.Sandberg@ARM.com /** Registers statistics. */ 1182735Sktlim@umich.edu void regStats(); 11910319SAndreas.Sandberg@ARM.com 1202735Sktlim@umich.edu /** Sets the main backwards communication time buffer pointer. */ 12110319SAndreas.Sandberg@ARM.com void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 12210319SAndreas.Sandberg@ARM.com 12310319SAndreas.Sandberg@ARM.com /** Sets pointer to time buffer used to communicate to the next stage. */ 12410319SAndreas.Sandberg@ARM.com void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 12510319SAndreas.Sandberg@ARM.com 12610319SAndreas.Sandberg@ARM.com /** Sets pointer to time buffer coming from decode. */ 12710319SAndreas.Sandberg@ARM.com void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 1282735Sktlim@umich.edu 12910319SAndreas.Sandberg@ARM.com /** Sets pointer to IEW stage. Used only for initialization. */ 13010319SAndreas.Sandberg@ARM.com void setIEWStage(IEW *iew_stage) 13110319SAndreas.Sandberg@ARM.com { iew_ptr = iew_stage; } 13210319SAndreas.Sandberg@ARM.com 13310319SAndreas.Sandberg@ARM.com /** Sets pointer to commit stage. Used only for initialization. */ 13410319SAndreas.Sandberg@ARM.com void setCommitStage(Commit *commit_stage) 13510319SAndreas.Sandberg@ARM.com { commit_ptr = commit_stage; } 1362735Sktlim@umich.edu 13710319SAndreas.Sandberg@ARM.com private: 13810319SAndreas.Sandberg@ARM.com /** Pointer to IEW stage. Used only for initialization. */ 13910319SAndreas.Sandberg@ARM.com IEW *iew_ptr; 14010319SAndreas.Sandberg@ARM.com 14110319SAndreas.Sandberg@ARM.com /** Pointer to commit stage. Used only for initialization. */ 1422735Sktlim@umich.edu Commit *commit_ptr; 14310319SAndreas.Sandberg@ARM.com 14410319SAndreas.Sandberg@ARM.com public: 14510319SAndreas.Sandberg@ARM.com /** Initializes variables for the stage. */ 14610319SAndreas.Sandberg@ARM.com void startupStage(); 14710319SAndreas.Sandberg@ARM.com 1482735Sktlim@umich.edu /** Sets pointer to list of active threads. */ 14910319SAndreas.Sandberg@ARM.com void setActiveThreads(std::list<ThreadID> *at_ptr); 1502735Sktlim@umich.edu 15110319SAndreas.Sandberg@ARM.com /** Sets pointer to rename maps (per-thread structures). */ 15210319SAndreas.Sandberg@ARM.com void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 15310319SAndreas.Sandberg@ARM.com 15410319SAndreas.Sandberg@ARM.com /** Sets pointer to the free list. */ 15510319SAndreas.Sandberg@ARM.com void setFreeList(FreeList *fl_ptr); 15610319SAndreas.Sandberg@ARM.com 15710319SAndreas.Sandberg@ARM.com /** Sets pointer to the scoreboard. */ 15810319SAndreas.Sandberg@ARM.com void setScoreboard(Scoreboard *_scoreboard); 15910319SAndreas.Sandberg@ARM.com 16010319SAndreas.Sandberg@ARM.com /** Drains the rename stage. */ 16110319SAndreas.Sandberg@ARM.com bool drain(); 16210319SAndreas.Sandberg@ARM.com 16310319SAndreas.Sandberg@ARM.com /** Resumes execution after a drain. */ 16410319SAndreas.Sandberg@ARM.com void resume() { } 16510319SAndreas.Sandberg@ARM.com 16610319SAndreas.Sandberg@ARM.com /** Switches out the rename stage. */ 16710319SAndreas.Sandberg@ARM.com void switchOut(); 16810319SAndreas.Sandberg@ARM.com 16910319SAndreas.Sandberg@ARM.com /** Takes over from another CPU's thread. */ 17010319SAndreas.Sandberg@ARM.com void takeOverFrom(); 17110319SAndreas.Sandberg@ARM.com 17210319SAndreas.Sandberg@ARM.com /** Squashes all instructions in a thread. */ 17310319SAndreas.Sandberg@ARM.com void squash(const InstSeqNum &squash_seq_num, ThreadID tid); 17410319SAndreas.Sandberg@ARM.com 17510319SAndreas.Sandberg@ARM.com /** Ticks rename, which processes all input signals and attempts to rename 17610319SAndreas.Sandberg@ARM.com * as many instructions as possible. 17710319SAndreas.Sandberg@ARM.com */ 17810319SAndreas.Sandberg@ARM.com void tick(); 17910319SAndreas.Sandberg@ARM.com 18010319SAndreas.Sandberg@ARM.com /** Debugging function used to dump history buffer of renamings. */ 18110319SAndreas.Sandberg@ARM.com void dumpHistory(); 18210319SAndreas.Sandberg@ARM.com 18310319SAndreas.Sandberg@ARM.com private: 18410319SAndreas.Sandberg@ARM.com /** Determines what to do based on rename's current status. 18510319SAndreas.Sandberg@ARM.com * @param status_change rename() sets this variable if there was a status 18610319SAndreas.Sandberg@ARM.com * change (ie switching from blocking to unblocking). 18710319SAndreas.Sandberg@ARM.com * @param tid Thread id to rename instructions from. 18810319SAndreas.Sandberg@ARM.com */ 18910319SAndreas.Sandberg@ARM.com void rename(bool &status_change, ThreadID tid); 19010319SAndreas.Sandberg@ARM.com 19110319SAndreas.Sandberg@ARM.com /** Renames instructions for the given thread. Also handles serializing 19210319SAndreas.Sandberg@ARM.com * instructions. 19310319SAndreas.Sandberg@ARM.com */ 19410319SAndreas.Sandberg@ARM.com void renameInsts(ThreadID tid); 19510319SAndreas.Sandberg@ARM.com 19610319SAndreas.Sandberg@ARM.com /** Inserts unused instructions from a given thread into the skid buffer, 19710319SAndreas.Sandberg@ARM.com * to be renamed once rename unblocks. 19810319SAndreas.Sandberg@ARM.com */ 19910319SAndreas.Sandberg@ARM.com void skidInsert(ThreadID tid); 20010319SAndreas.Sandberg@ARM.com 20110319SAndreas.Sandberg@ARM.com /** Separates instructions from decode into individual lists of instructions 20210319SAndreas.Sandberg@ARM.com * sorted by thread. 20310319SAndreas.Sandberg@ARM.com */ 20410319SAndreas.Sandberg@ARM.com void sortInsts(); 2052735Sktlim@umich.edu 2062735Sktlim@umich.edu /** Returns if all of the skid buffers are empty. */ 20710319SAndreas.Sandberg@ARM.com bool skidsEmpty(); 2082735Sktlim@umich.edu 20910319SAndreas.Sandberg@ARM.com /** Updates overall rename status based on all of the threads' statuses. */ 21010319SAndreas.Sandberg@ARM.com void updateStatus(); 21110319SAndreas.Sandberg@ARM.com 21210319SAndreas.Sandberg@ARM.com /** Switches rename to blocking, and signals back that rename has become 2137520Sgblack@eecs.umich.edu * blocked. 21410319SAndreas.Sandberg@ARM.com * @return Returns true if there is a status change. 21510319SAndreas.Sandberg@ARM.com */ 21610319SAndreas.Sandberg@ARM.com bool block(ThreadID tid); 21710319SAndreas.Sandberg@ARM.com 21810319SAndreas.Sandberg@ARM.com /** Switches rename to unblocking if the skid buffer is empty, and signals 2195702Ssaidi@eecs.umich.edu * back that rename has unblocked. 2205702Ssaidi@eecs.umich.edu * @return Returns true if there is a status change. 2215702Ssaidi@eecs.umich.edu */ 2225702Ssaidi@eecs.umich.edu bool unblock(ThreadID tid); 2235702Ssaidi@eecs.umich.edu 22410319SAndreas.Sandberg@ARM.com /** Executes actual squash, removing squashed instructions. */ 2258779Sgblack@eecs.umich.edu void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid); 22610319SAndreas.Sandberg@ARM.com 2276973Stjones1@inf.ed.ac.uk /** Removes a committed instruction's rename history. */ 22810319SAndreas.Sandberg@ARM.com void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid); 22910319SAndreas.Sandberg@ARM.com 23010319SAndreas.Sandberg@ARM.com /** Renames the source registers of an instruction. */ 23110319SAndreas.Sandberg@ARM.com inline void renameSrcRegs(DynInstPtr &inst, ThreadID tid); 23210319SAndreas.Sandberg@ARM.com 23310319SAndreas.Sandberg@ARM.com /** Renames the destination registers of an instruction. */ 23410319SAndreas.Sandberg@ARM.com inline void renameDestRegs(DynInstPtr &inst, ThreadID tid); 23510319SAndreas.Sandberg@ARM.com 23610319SAndreas.Sandberg@ARM.com /** Calculates the number of free ROB entries for a specific thread. */ 23710319SAndreas.Sandberg@ARM.com inline int calcFreeROBEntries(ThreadID tid); 23810319SAndreas.Sandberg@ARM.com 23910319SAndreas.Sandberg@ARM.com /** Calculates the number of free IQ entries for a specific thread. */ 24010319SAndreas.Sandberg@ARM.com inline int calcFreeIQEntries(ThreadID tid); 24110319SAndreas.Sandberg@ARM.com 24210319SAndreas.Sandberg@ARM.com /** Calculates the number of free LSQ entries for a specific thread. */ 24310319SAndreas.Sandberg@ARM.com inline int calcFreeLSQEntries(ThreadID tid); 24410319SAndreas.Sandberg@ARM.com 24510319SAndreas.Sandberg@ARM.com /** Returns the number of valid instructions coming from decode. */ 24610319SAndreas.Sandberg@ARM.com unsigned validInsts(); 24710319SAndreas.Sandberg@ARM.com 24810319SAndreas.Sandberg@ARM.com /** Reads signals telling rename to block/unblock. */ 24910319SAndreas.Sandberg@ARM.com void readStallSignals(ThreadID tid); 25010319SAndreas.Sandberg@ARM.com 25110319SAndreas.Sandberg@ARM.com /** Checks if any stages are telling rename to block. */ 25210319SAndreas.Sandberg@ARM.com bool checkStall(ThreadID tid); 25310319SAndreas.Sandberg@ARM.com 25410319SAndreas.Sandberg@ARM.com /** Gets the number of free entries for a specific thread. */ 25510319SAndreas.Sandberg@ARM.com void readFreeEntries(ThreadID tid); 25610319SAndreas.Sandberg@ARM.com 25710319SAndreas.Sandberg@ARM.com /** Checks the signals and updates the status. */ 25810319SAndreas.Sandberg@ARM.com bool checkSignalsAndUpdate(ThreadID tid); 25910319SAndreas.Sandberg@ARM.com 26010319SAndreas.Sandberg@ARM.com /** Either serializes on the next instruction available in the InstQueue, 26110319SAndreas.Sandberg@ARM.com * or records that it must serialize on the next instruction to enter 26210319SAndreas.Sandberg@ARM.com * rename. 2632735Sktlim@umich.edu * @param inst_list The list of younger, unprocessed instructions for the 26410319SAndreas.Sandberg@ARM.com * thread that has the serializeAfter instruction. 26510319SAndreas.Sandberg@ARM.com * @param tid The thread id. 266 */ 267 void serializeAfter(InstQueue &inst_list, ThreadID tid); 268 269 /** Holds the information for each destination register rename. It holds 270 * the instruction's sequence number, the arch register, the old physical 271 * register for that arch. register, and the new physical register. 272 */ 273 struct RenameHistory { 274 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 275 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 276 : instSeqNum(_instSeqNum), archReg(_archReg), 277 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg) 278 { 279 } 280 281 /** The sequence number of the instruction that renamed. */ 282 InstSeqNum instSeqNum; 283 /** The architectural register index that was renamed. */ 284 RegIndex archReg; 285 /** The new physical register that the arch. register is renamed to. */ 286 PhysRegIndex newPhysReg; 287 /** The old physical register that the arch. register was renamed to. */ 288 PhysRegIndex prevPhysReg; 289 }; 290 291 /** A per-thread list of all destination register renames, used to either 292 * undo rename mappings or free old physical registers. 293 */ 294 std::list<RenameHistory> historyBuffer[Impl::MaxThreads]; 295 296 /** Pointer to CPU. */ 297 O3CPU *cpu; 298 299 /** Pointer to main time buffer used for backwards communication. */ 300 TimeBuffer<TimeStruct> *timeBuffer; 301 302 /** Wire to get IEW's output from backwards time buffer. */ 303 typename TimeBuffer<TimeStruct>::wire fromIEW; 304 305 /** Wire to get commit's output from backwards time buffer. */ 306 typename TimeBuffer<TimeStruct>::wire fromCommit; 307 308 /** Wire to write infromation heading to previous stages. */ 309 typename TimeBuffer<TimeStruct>::wire toDecode; 310 311 /** Rename instruction queue. */ 312 TimeBuffer<RenameStruct> *renameQueue; 313 314 /** Wire to write any information heading to IEW. */ 315 typename TimeBuffer<RenameStruct>::wire toIEW; 316 317 /** Decode instruction queue interface. */ 318 TimeBuffer<DecodeStruct> *decodeQueue; 319 320 /** Wire to get decode's output from decode queue. */ 321 typename TimeBuffer<DecodeStruct>::wire fromDecode; 322 323 /** Queue of all instructions coming from decode this cycle. */ 324 InstQueue insts[Impl::MaxThreads]; 325 326 /** Skid buffer between rename and decode. */ 327 InstQueue skidBuffer[Impl::MaxThreads]; 328 329 /** Rename map interface. */ 330 RenameMap *renameMap[Impl::MaxThreads]; 331 332 /** Free list interface. */ 333 FreeList *freeList; 334 335 /** Pointer to the list of active threads. */ 336 std::list<ThreadID> *activeThreads; 337 338 /** Pointer to the scoreboard. */ 339 Scoreboard *scoreboard; 340 341 /** Count of instructions in progress that have been sent off to the IQ 342 * and ROB, but are not yet included in their occupancy counts. 343 */ 344 int instsInProgress[Impl::MaxThreads]; 345 346 /** Variable that tracks if decode has written to the time buffer this 347 * cycle. Used to tell CPU if there is activity this cycle. 348 */ 349 bool wroteToTimeBuffer; 350 351 /** Structures whose free entries impact the amount of instructions that 352 * can be renamed. 353 */ 354 struct FreeEntries { 355 unsigned iqEntries; 356 unsigned lsqEntries; 357 unsigned robEntries; 358 }; 359 360 /** Per-thread tracking of the number of free entries of back-end 361 * structures. 362 */ 363 FreeEntries freeEntries[Impl::MaxThreads]; 364 365 /** Records if the ROB is empty. In SMT mode the ROB may be dynamically 366 * partitioned between threads, so the ROB must tell rename when it is 367 * empty. 368 */ 369 bool emptyROB[Impl::MaxThreads]; 370 371 /** Source of possible stalls. */ 372 struct Stalls { 373 bool iew; 374 bool commit; 375 }; 376 377 /** Tracks which stages are telling decode to stall. */ 378 Stalls stalls[Impl::MaxThreads]; 379 380 /** The serialize instruction that rename has stalled on. */ 381 DynInstPtr serializeInst[Impl::MaxThreads]; 382 383 /** Records if rename needs to serialize on the next instruction for any 384 * thread. 385 */ 386 bool serializeOnNextInst[Impl::MaxThreads]; 387 388 /** Delay between iew and rename, in ticks. */ 389 int iewToRenameDelay; 390 391 /** Delay between decode and rename, in ticks. */ 392 int decodeToRenameDelay; 393 394 /** Delay between commit and rename, in ticks. */ 395 unsigned commitToRenameDelay; 396 397 /** Rename width, in instructions. */ 398 unsigned renameWidth; 399 400 /** Commit width, in instructions. Used so rename knows how many 401 * instructions might have freed registers in the previous cycle. 402 */ 403 unsigned commitWidth; 404 405 /** The index of the instruction in the time buffer to IEW that rename is 406 * currently using. 407 */ 408 unsigned toIEWIndex; 409 410 /** Whether or not rename needs to block this cycle. */ 411 bool blockThisCycle; 412 413 /** Whether or not rename needs to resume a serialize instruction 414 * after squashing. */ 415 bool resumeSerialize; 416 417 /** Whether or not rename needs to resume clearing out the skidbuffer 418 * after squashing. */ 419 bool resumeUnblocking; 420 421 /** The number of threads active in rename. */ 422 ThreadID numThreads; 423 424 /** The maximum skid buffer size. */ 425 unsigned skidBufferMax; 426 427 PhysRegIndex maxPhysicalRegs; 428 429 /** Enum to record the source of a structure full stall. Can come from 430 * either ROB, IQ, LSQ, and it is priortized in that order. 431 */ 432 enum FullSource { 433 ROB, 434 IQ, 435 LSQ, 436 NONE 437 }; 438 439 /** Function used to increment the stat that corresponds to the source of 440 * the stall. 441 */ 442 inline void incrFullStat(const FullSource &source); 443 444 /** Stat for total number of cycles spent squashing. */ 445 Stats::Scalar renameSquashCycles; 446 /** Stat for total number of cycles spent idle. */ 447 Stats::Scalar renameIdleCycles; 448 /** Stat for total number of cycles spent blocking. */ 449 Stats::Scalar renameBlockCycles; 450 /** Stat for total number of cycles spent stalling for a serializing inst. */ 451 Stats::Scalar renameSerializeStallCycles; 452 /** Stat for total number of cycles spent running normally. */ 453 Stats::Scalar renameRunCycles; 454 /** Stat for total number of cycles spent unblocking. */ 455 Stats::Scalar renameUnblockCycles; 456 /** Stat for total number of renamed instructions. */ 457 Stats::Scalar renameRenamedInsts; 458 /** Stat for total number of squashed instructions that rename discards. */ 459 Stats::Scalar renameSquashedInsts; 460 /** Stat for total number of times that the ROB starts a stall in rename. */ 461 Stats::Scalar renameROBFullEvents; 462 /** Stat for total number of times that the IQ starts a stall in rename. */ 463 Stats::Scalar renameIQFullEvents; 464 /** Stat for total number of times that the LSQ starts a stall in rename. */ 465 Stats::Scalar renameLSQFullEvents; 466 /** Stat for total number of times that rename runs out of free registers 467 * to use to rename. */ 468 Stats::Scalar renameFullRegistersEvents; 469 /** Stat for total number of renamed destination registers. */ 470 Stats::Scalar renameRenamedOperands; 471 /** Stat for total number of source register rename lookups. */ 472 Stats::Scalar renameRenameLookups; 473 Stats::Scalar intRenameLookups; 474 Stats::Scalar fpRenameLookups; 475 /** Stat for total number of committed renaming mappings. */ 476 Stats::Scalar renameCommittedMaps; 477 /** Stat for total number of mappings that were undone due to a squash. */ 478 Stats::Scalar renameUndoneMaps; 479 /** Number of serialize instructions handled. */ 480 Stats::Scalar renamedSerializing; 481 /** Number of instructions marked as temporarily serializing. */ 482 Stats::Scalar renamedTempSerializing; 483 /** Number of instructions inserted into skid buffers. */ 484 Stats::Scalar renameSkidInsts; 485}; 486 487#endif // __CPU_O3_RENAME_HH__ 488