rename.hh revision 5999 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_RENAME_HH__
32#define __CPU_O3_RENAME_HH__
33
34#include <list>
35
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38
39class DerivO3CPUParams;
40
41/**
42 * DefaultRename handles both single threaded and SMT rename. Its
43 * width is specified by the parameters; each cycle it tries to rename
44 * that many instructions. It holds onto the rename history of all
45 * instructions with destination registers, storing the
46 * arch. register, the new physical register, and the old physical
47 * register, to allow for undoing of mappings if squashing happens, or
48 * freeing up registers upon commit. Rename handles blocking if the
49 * ROB, IQ, or LSQ is going to be full. Rename also handles barriers,
50 * and does so by stalling on the instruction until the ROB is empty
51 * and there are no instructions in flight to the ROB.
52 */
53template<class Impl>
54class DefaultRename
55{
56  public:
57    // Typedefs from the Impl.
58    typedef typename Impl::CPUPol CPUPol;
59    typedef typename Impl::DynInstPtr DynInstPtr;
60    typedef typename Impl::O3CPU O3CPU;
61
62    // Typedefs from the CPUPol
63    typedef typename CPUPol::DecodeStruct DecodeStruct;
64    typedef typename CPUPol::RenameStruct RenameStruct;
65    typedef typename CPUPol::TimeStruct TimeStruct;
66    typedef typename CPUPol::FreeList FreeList;
67    typedef typename CPUPol::RenameMap RenameMap;
68    // These are used only for initialization.
69    typedef typename CPUPol::IEW IEW;
70    typedef typename CPUPol::Commit Commit;
71
72    // Typedefs from the ISA.
73    typedef TheISA::RegIndex RegIndex;
74
75    // A list is used to queue the instructions.  Barrier insts must
76    // be added to the front of the list, which is the only reason for
77    // using a list instead of a queue. (Most other stages use a
78    // queue)
79    typedef std::list<DynInstPtr> InstQueue;
80    typedef typename std::list<DynInstPtr>::iterator ListIt;
81
82  public:
83    /** Overall rename status. Used to determine if the CPU can
84     * deschedule itself due to a lack of activity.
85     */
86    enum RenameStatus {
87        Active,
88        Inactive
89    };
90
91    /** Individual thread status. */
92    enum ThreadStatus {
93        Running,
94        Idle,
95        StartSquash,
96        Squashing,
97        Blocked,
98        Unblocking,
99        SerializeStall
100    };
101
102  private:
103    /** Rename status. */
104    RenameStatus _status;
105
106    /** Per-thread status. */
107    ThreadStatus renameStatus[Impl::MaxThreads];
108
109  public:
110    /** DefaultRename constructor. */
111    DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params);
112
113    /** Returns the name of rename. */
114    std::string name() const;
115
116    /** Registers statistics. */
117    void regStats();
118
119    /** Sets the main backwards communication time buffer pointer. */
120    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
121
122    /** Sets pointer to time buffer used to communicate to the next stage. */
123    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
124
125    /** Sets pointer to time buffer coming from decode. */
126    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
127
128    /** Sets pointer to IEW stage. Used only for initialization. */
129    void setIEWStage(IEW *iew_stage)
130    { iew_ptr = iew_stage; }
131
132    /** Sets pointer to commit stage. Used only for initialization. */
133    void setCommitStage(Commit *commit_stage)
134    { commit_ptr = commit_stage; }
135
136  private:
137    /** Pointer to IEW stage. Used only for initialization. */
138    IEW *iew_ptr;
139
140    /** Pointer to commit stage. Used only for initialization. */
141    Commit *commit_ptr;
142
143  public:
144    /** Initializes variables for the stage. */
145    void initStage();
146
147    /** Sets pointer to list of active threads. */
148    void setActiveThreads(std::list<unsigned> *at_ptr);
149
150    /** Sets pointer to rename maps (per-thread structures). */
151    void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
152
153    /** Sets pointer to the free list. */
154    void setFreeList(FreeList *fl_ptr);
155
156    /** Sets pointer to the scoreboard. */
157    void setScoreboard(Scoreboard *_scoreboard);
158
159    /** Drains the rename stage. */
160    bool drain();
161
162    /** Resumes execution after a drain. */
163    void resume() { }
164
165    /** Switches out the rename stage. */
166    void switchOut();
167
168    /** Takes over from another CPU's thread. */
169    void takeOverFrom();
170
171    /** Squashes all instructions in a thread. */
172    void squash(const InstSeqNum &squash_seq_num, unsigned tid);
173
174    /** Ticks rename, which processes all input signals and attempts to rename
175     * as many instructions as possible.
176     */
177    void tick();
178
179    /** Debugging function used to dump history buffer of renamings. */
180    void dumpHistory();
181
182  private:
183    /** Determines what to do based on rename's current status.
184     * @param status_change rename() sets this variable if there was a status
185     * change (ie switching from blocking to unblocking).
186     * @param tid Thread id to rename instructions from.
187     */
188    void rename(bool &status_change, unsigned tid);
189
190    /** Renames instructions for the given thread. Also handles serializing
191     * instructions.
192     */
193    void renameInsts(unsigned tid);
194
195    /** Inserts unused instructions from a given thread into the skid buffer,
196     * to be renamed once rename unblocks.
197     */
198    void skidInsert(unsigned tid);
199
200    /** Separates instructions from decode into individual lists of instructions
201     * sorted by thread.
202     */
203    void sortInsts();
204
205    /** Returns if all of the skid buffers are empty. */
206    bool skidsEmpty();
207
208    /** Updates overall rename status based on all of the threads' statuses. */
209    void updateStatus();
210
211    /** Switches rename to blocking, and signals back that rename has become
212     * blocked.
213     * @return Returns true if there is a status change.
214     */
215    bool block(unsigned tid);
216
217    /** Switches rename to unblocking if the skid buffer is empty, and signals
218     * back that rename has unblocked.
219     * @return Returns true if there is a status change.
220     */
221    bool unblock(unsigned tid);
222
223    /** Executes actual squash, removing squashed instructions. */
224    void doSquash(const InstSeqNum &squash_seq_num, unsigned tid);
225
226    /** Removes a committed instruction's rename history. */
227    void removeFromHistory(InstSeqNum inst_seq_num, unsigned tid);
228
229    /** Renames the source registers of an instruction. */
230    inline void renameSrcRegs(DynInstPtr &inst, unsigned tid);
231
232    /** Renames the destination registers of an instruction. */
233    inline void renameDestRegs(DynInstPtr &inst, unsigned tid);
234
235    /** Calculates the number of free ROB entries for a specific thread. */
236    inline int calcFreeROBEntries(unsigned tid);
237
238    /** Calculates the number of free IQ entries for a specific thread. */
239    inline int calcFreeIQEntries(unsigned tid);
240
241    /** Calculates the number of free LSQ entries for a specific thread. */
242    inline int calcFreeLSQEntries(unsigned tid);
243
244    /** Returns the number of valid instructions coming from decode. */
245    unsigned validInsts();
246
247    /** Reads signals telling rename to block/unblock. */
248    void readStallSignals(unsigned tid);
249
250    /** Checks if any stages are telling rename to block. */
251    bool checkStall(unsigned tid);
252
253    /** Gets the number of free entries for a specific thread. */
254    void readFreeEntries(unsigned tid);
255
256    /** Checks the signals and updates the status. */
257    bool checkSignalsAndUpdate(unsigned tid);
258
259    /** Either serializes on the next instruction available in the InstQueue,
260     * or records that it must serialize on the next instruction to enter
261     * rename.
262     * @param inst_list The list of younger, unprocessed instructions for the
263     * thread that has the serializeAfter instruction.
264     * @param tid The thread id.
265     */
266    void serializeAfter(InstQueue &inst_list, unsigned tid);
267
268    /** Holds the information for each destination register rename. It holds
269     * the instruction's sequence number, the arch register, the old physical
270     * register for that arch. register, and the new physical register.
271     */
272    struct RenameHistory {
273        RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
274                      PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
275            : instSeqNum(_instSeqNum), archReg(_archReg),
276              newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
277        {
278        }
279
280        /** The sequence number of the instruction that renamed. */
281        InstSeqNum instSeqNum;
282        /** The architectural register index that was renamed. */
283        RegIndex archReg;
284        /** The new physical register that the arch. register is renamed to. */
285        PhysRegIndex newPhysReg;
286        /** The old physical register that the arch. register was renamed to. */
287        PhysRegIndex prevPhysReg;
288    };
289
290    /** A per-thread list of all destination register renames, used to either
291     * undo rename mappings or free old physical registers.
292     */
293    std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
294
295    /** Pointer to CPU. */
296    O3CPU *cpu;
297
298    /** Pointer to main time buffer used for backwards communication. */
299    TimeBuffer<TimeStruct> *timeBuffer;
300
301    /** Wire to get IEW's output from backwards time buffer. */
302    typename TimeBuffer<TimeStruct>::wire fromIEW;
303
304    /** Wire to get commit's output from backwards time buffer. */
305    typename TimeBuffer<TimeStruct>::wire fromCommit;
306
307    /** Wire to write infromation heading to previous stages. */
308    typename TimeBuffer<TimeStruct>::wire toDecode;
309
310    /** Rename instruction queue. */
311    TimeBuffer<RenameStruct> *renameQueue;
312
313    /** Wire to write any information heading to IEW. */
314    typename TimeBuffer<RenameStruct>::wire toIEW;
315
316    /** Decode instruction queue interface. */
317    TimeBuffer<DecodeStruct> *decodeQueue;
318
319    /** Wire to get decode's output from decode queue. */
320    typename TimeBuffer<DecodeStruct>::wire fromDecode;
321
322    /** Queue of all instructions coming from decode this cycle. */
323    InstQueue insts[Impl::MaxThreads];
324
325    /** Skid buffer between rename and decode. */
326    InstQueue skidBuffer[Impl::MaxThreads];
327
328    /** Rename map interface. */
329    RenameMap *renameMap[Impl::MaxThreads];
330
331    /** Free list interface. */
332    FreeList *freeList;
333
334    /** Pointer to the list of active threads. */
335    std::list<unsigned> *activeThreads;
336
337    /** Pointer to the scoreboard. */
338    Scoreboard *scoreboard;
339
340    /** Count of instructions in progress that have been sent off to the IQ
341     * and ROB, but are not yet included in their occupancy counts.
342     */
343    int instsInProgress[Impl::MaxThreads];
344
345    /** Variable that tracks if decode has written to the time buffer this
346     * cycle. Used to tell CPU if there is activity this cycle.
347     */
348    bool wroteToTimeBuffer;
349
350    /** Structures whose free entries impact the amount of instructions that
351     * can be renamed.
352     */
353    struct FreeEntries {
354        unsigned iqEntries;
355        unsigned lsqEntries;
356        unsigned robEntries;
357    };
358
359    /** Per-thread tracking of the number of free entries of back-end
360     * structures.
361     */
362    FreeEntries freeEntries[Impl::MaxThreads];
363
364    /** Records if the ROB is empty. In SMT mode the ROB may be dynamically
365     * partitioned between threads, so the ROB must tell rename when it is
366     * empty.
367     */
368    bool emptyROB[Impl::MaxThreads];
369
370    /** Source of possible stalls. */
371    struct Stalls {
372        bool iew;
373        bool commit;
374    };
375
376    /** Tracks which stages are telling decode to stall. */
377    Stalls stalls[Impl::MaxThreads];
378
379    /** The serialize instruction that rename has stalled on. */
380    DynInstPtr serializeInst[Impl::MaxThreads];
381
382    /** Records if rename needs to serialize on the next instruction for any
383     * thread.
384     */
385    bool serializeOnNextInst[Impl::MaxThreads];
386
387    /** Delay between iew and rename, in ticks. */
388    int iewToRenameDelay;
389
390    /** Delay between decode and rename, in ticks. */
391    int decodeToRenameDelay;
392
393    /** Delay between commit and rename, in ticks. */
394    unsigned commitToRenameDelay;
395
396    /** Rename width, in instructions. */
397    unsigned renameWidth;
398
399    /** Commit width, in instructions.  Used so rename knows how many
400     *  instructions might have freed registers in the previous cycle.
401     */
402    unsigned commitWidth;
403
404    /** The index of the instruction in the time buffer to IEW that rename is
405     * currently using.
406     */
407    unsigned toIEWIndex;
408
409    /** Whether or not rename needs to block this cycle. */
410    bool blockThisCycle;
411
412    /** Whether or not rename needs to resume a serialize instruction
413     * after squashing. */
414    bool resumeSerialize;
415
416    /** Whether or not rename needs to resume clearing out the skidbuffer
417     * after squashing. */
418    bool resumeUnblocking;
419
420    /** The number of threads active in rename. */
421    unsigned numThreads;
422
423    /** The maximum skid buffer size. */
424    unsigned skidBufferMax;
425
426    PhysRegIndex maxPhysicalRegs;
427
428    /** Enum to record the source of a structure full stall.  Can come from
429     * either ROB, IQ, LSQ, and it is priortized in that order.
430     */
431    enum FullSource {
432        ROB,
433        IQ,
434        LSQ,
435        NONE
436    };
437
438    /** Function used to increment the stat that corresponds to the source of
439     * the stall.
440     */
441    inline void incrFullStat(const FullSource &source);
442
443    /** Stat for total number of cycles spent squashing. */
444    Stats::Scalar renameSquashCycles;
445    /** Stat for total number of cycles spent idle. */
446    Stats::Scalar renameIdleCycles;
447    /** Stat for total number of cycles spent blocking. */
448    Stats::Scalar renameBlockCycles;
449    /** Stat for total number of cycles spent stalling for a serializing inst. */
450    Stats::Scalar renameSerializeStallCycles;
451    /** Stat for total number of cycles spent running normally. */
452    Stats::Scalar renameRunCycles;
453    /** Stat for total number of cycles spent unblocking. */
454    Stats::Scalar renameUnblockCycles;
455    /** Stat for total number of renamed instructions. */
456    Stats::Scalar renameRenamedInsts;
457    /** Stat for total number of squashed instructions that rename discards. */
458    Stats::Scalar renameSquashedInsts;
459    /** Stat for total number of times that the ROB starts a stall in rename. */
460    Stats::Scalar renameROBFullEvents;
461    /** Stat for total number of times that the IQ starts a stall in rename. */
462    Stats::Scalar renameIQFullEvents;
463    /** Stat for total number of times that the LSQ starts a stall in rename. */
464    Stats::Scalar renameLSQFullEvents;
465    /** Stat for total number of times that rename runs out of free registers
466     * to use to rename. */
467    Stats::Scalar renameFullRegistersEvents;
468    /** Stat for total number of renamed destination registers. */
469    Stats::Scalar renameRenamedOperands;
470    /** Stat for total number of source register rename lookups. */
471    Stats::Scalar renameRenameLookups;
472    /** Stat for total number of committed renaming mappings. */
473    Stats::Scalar renameCommittedMaps;
474    /** Stat for total number of mappings that were undone due to a squash. */
475    Stats::Scalar renameUndoneMaps;
476    /** Number of serialize instructions handled. */
477    Stats::Scalar renamedSerializing;
478    /** Number of instructions marked as temporarily serializing. */
479    Stats::Scalar renamedTempSerializing;
480    /** Number of instructions inserted into skid buffers. */
481    Stats::Scalar renameSkidInsts;
482};
483
484#endif // __CPU_O3_RENAME_HH__
485