rename.hh revision 2935 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_RENAME_HH__
32#define __CPU_O3_RENAME_HH__
33
34#include <list>
35
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38
39/**
40 * DefaultRename handles both single threaded and SMT rename. Its
41 * width is specified by the parameters; each cycle it tries to rename
42 * that many instructions. It holds onto the rename history of all
43 * instructions with destination registers, storing the
44 * arch. register, the new physical register, and the old physical
45 * register, to allow for undoing of mappings if squashing happens, or
46 * freeing up registers upon commit. Rename handles blocking if the
47 * ROB, IQ, or LSQ is going to be full. Rename also handles barriers,
48 * and does so by stalling on the instruction until the ROB is empty
49 * and there are no instructions in flight to the ROB.
50 */
51template<class Impl>
52class DefaultRename
53{
54  public:
55    // Typedefs from the Impl.
56    typedef typename Impl::CPUPol CPUPol;
57    typedef typename Impl::DynInstPtr DynInstPtr;
58    typedef typename Impl::O3CPU O3CPU;
59    typedef typename Impl::Params Params;
60
61    // Typedefs from the CPUPol
62    typedef typename CPUPol::DecodeStruct DecodeStruct;
63    typedef typename CPUPol::RenameStruct RenameStruct;
64    typedef typename CPUPol::TimeStruct TimeStruct;
65    typedef typename CPUPol::FreeList FreeList;
66    typedef typename CPUPol::RenameMap RenameMap;
67    // These are used only for initialization.
68    typedef typename CPUPol::IEW IEW;
69    typedef typename CPUPol::Commit Commit;
70
71    // Typedefs from the ISA.
72    typedef TheISA::RegIndex RegIndex;
73
74    // A list is used to queue the instructions.  Barrier insts must
75    // be added to the front of the list, which is the only reason for
76    // using a list instead of a queue. (Most other stages use a
77    // queue)
78    typedef std::list<DynInstPtr> InstQueue;
79    typedef typename std::list<DynInstPtr>::iterator ListIt;
80
81  public:
82    /** Overall rename status. Used to determine if the CPU can
83     * deschedule itself due to a lack of activity.
84     */
85    enum RenameStatus {
86        Active,
87        Inactive
88    };
89
90    /** Individual thread status. */
91    enum ThreadStatus {
92        Running,
93        Idle,
94        StartSquash,
95        Squashing,
96        Blocked,
97        Unblocking,
98        SerializeStall
99    };
100
101  private:
102    /** Rename status. */
103    RenameStatus _status;
104
105    /** Per-thread status. */
106    ThreadStatus renameStatus[Impl::MaxThreads];
107
108  public:
109    /** DefaultRename constructor. */
110    DefaultRename(Params *params);
111
112    /** Returns the name of rename. */
113    std::string name() const;
114
115    /** Registers statistics. */
116    void regStats();
117
118    /** Sets CPU pointer. */
119    void setCPU(O3CPU *cpu_ptr);
120
121    /** Sets the main backwards communication time buffer pointer. */
122    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
123
124    /** Sets pointer to time buffer used to communicate to the next stage. */
125    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
126
127    /** Sets pointer to time buffer coming from decode. */
128    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
129
130    /** Sets pointer to IEW stage. Used only for initialization. */
131    void setIEWStage(IEW *iew_stage)
132    { iew_ptr = iew_stage; }
133
134    /** Sets pointer to commit stage. Used only for initialization. */
135    void setCommitStage(Commit *commit_stage)
136    { commit_ptr = commit_stage; }
137
138  private:
139    /** Pointer to IEW stage. Used only for initialization. */
140    IEW *iew_ptr;
141
142    /** Pointer to commit stage. Used only for initialization. */
143    Commit *commit_ptr;
144
145  public:
146    /** Initializes variables for the stage. */
147    void initStage();
148
149    /** Sets pointer to list of active threads. */
150    void setActiveThreads(std::list<unsigned> *at_ptr);
151
152    /** Sets pointer to rename maps (per-thread structures). */
153    void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
154
155    /** Sets pointer to the free list. */
156    void setFreeList(FreeList *fl_ptr);
157
158    /** Sets pointer to the scoreboard. */
159    void setScoreboard(Scoreboard *_scoreboard);
160
161    /** Drains the rename stage. */
162    bool drain();
163
164    /** Resumes execution after a drain. */
165    void resume() { }
166
167    /** Switches out the rename stage. */
168    void switchOut();
169
170    /** Takes over from another CPU's thread. */
171    void takeOverFrom();
172
173    /** Squashes all instructions in a thread. */
174    void squash(const InstSeqNum &squash_seq_num, unsigned tid);
175
176    /** Ticks rename, which processes all input signals and attempts to rename
177     * as many instructions as possible.
178     */
179    void tick();
180
181    /** Debugging function used to dump history buffer of renamings. */
182    void dumpHistory();
183
184  private:
185    /** Determines what to do based on rename's current status.
186     * @param status_change rename() sets this variable if there was a status
187     * change (ie switching from blocking to unblocking).
188     * @param tid Thread id to rename instructions from.
189     */
190    void rename(bool &status_change, unsigned tid);
191
192    /** Renames instructions for the given thread. Also handles serializing
193     * instructions.
194     */
195    void renameInsts(unsigned tid);
196
197    /** Inserts unused instructions from a given thread into the skid buffer,
198     * to be renamed once rename unblocks.
199     */
200    void skidInsert(unsigned tid);
201
202    /** Separates instructions from decode into individual lists of instructions
203     * sorted by thread.
204     */
205    void sortInsts();
206
207    /** Returns if all of the skid buffers are empty. */
208    bool skidsEmpty();
209
210    /** Updates overall rename status based on all of the threads' statuses. */
211    void updateStatus();
212
213    /** Switches rename to blocking, and signals back that rename has become
214     * blocked.
215     * @return Returns true if there is a status change.
216     */
217    bool block(unsigned tid);
218
219    /** Switches rename to unblocking if the skid buffer is empty, and signals
220     * back that rename has unblocked.
221     * @return Returns true if there is a status change.
222     */
223    bool unblock(unsigned tid);
224
225    /** Executes actual squash, removing squashed instructions. */
226    void doSquash(const InstSeqNum &squash_seq_num, unsigned tid);
227
228    /** Removes a committed instruction's rename history. */
229    void removeFromHistory(InstSeqNum inst_seq_num, unsigned tid);
230
231    /** Renames the source registers of an instruction. */
232    inline void renameSrcRegs(DynInstPtr &inst, unsigned tid);
233
234    /** Renames the destination registers of an instruction. */
235    inline void renameDestRegs(DynInstPtr &inst, unsigned tid);
236
237    /** Calculates the number of free ROB entries for a specific thread. */
238    inline int calcFreeROBEntries(unsigned tid);
239
240    /** Calculates the number of free IQ entries for a specific thread. */
241    inline int calcFreeIQEntries(unsigned tid);
242
243    /** Calculates the number of free LSQ entries for a specific thread. */
244    inline int calcFreeLSQEntries(unsigned tid);
245
246    /** Returns the number of valid instructions coming from decode. */
247    unsigned validInsts();
248
249    /** Reads signals telling rename to block/unblock. */
250    void readStallSignals(unsigned tid);
251
252    /** Checks if any stages are telling rename to block. */
253    bool checkStall(unsigned tid);
254
255    /** Gets the number of free entries for a specific thread. */
256    void readFreeEntries(unsigned tid);
257
258    /** Checks the signals and updates the status. */
259    bool checkSignalsAndUpdate(unsigned tid);
260
261    /** Either serializes on the next instruction available in the InstQueue,
262     * or records that it must serialize on the next instruction to enter
263     * rename.
264     * @param inst_list The list of younger, unprocessed instructions for the
265     * thread that has the serializeAfter instruction.
266     * @param tid The thread id.
267     */
268    void serializeAfter(InstQueue &inst_list, unsigned tid);
269
270    /** Holds the information for each destination register rename. It holds
271     * the instruction's sequence number, the arch register, the old physical
272     * register for that arch. register, and the new physical register.
273     */
274    struct RenameHistory {
275        RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
276                      PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
277            : instSeqNum(_instSeqNum), archReg(_archReg),
278              newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
279        {
280        }
281
282        /** The sequence number of the instruction that renamed. */
283        InstSeqNum instSeqNum;
284        /** The architectural register index that was renamed. */
285        RegIndex archReg;
286        /** The new physical register that the arch. register is renamed to. */
287        PhysRegIndex newPhysReg;
288        /** The old physical register that the arch. register was renamed to. */
289        PhysRegIndex prevPhysReg;
290    };
291
292    /** A per-thread list of all destination register renames, used to either
293     * undo rename mappings or free old physical registers.
294     */
295    std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
296
297    /** Pointer to CPU. */
298    O3CPU *cpu;
299
300    /** Pointer to main time buffer used for backwards communication. */
301    TimeBuffer<TimeStruct> *timeBuffer;
302
303    /** Wire to get IEW's output from backwards time buffer. */
304    typename TimeBuffer<TimeStruct>::wire fromIEW;
305
306    /** Wire to get commit's output from backwards time buffer. */
307    typename TimeBuffer<TimeStruct>::wire fromCommit;
308
309    /** Wire to write infromation heading to previous stages. */
310    typename TimeBuffer<TimeStruct>::wire toDecode;
311
312    /** Rename instruction queue. */
313    TimeBuffer<RenameStruct> *renameQueue;
314
315    /** Wire to write any information heading to IEW. */
316    typename TimeBuffer<RenameStruct>::wire toIEW;
317
318    /** Decode instruction queue interface. */
319    TimeBuffer<DecodeStruct> *decodeQueue;
320
321    /** Wire to get decode's output from decode queue. */
322    typename TimeBuffer<DecodeStruct>::wire fromDecode;
323
324    /** Queue of all instructions coming from decode this cycle. */
325    InstQueue insts[Impl::MaxThreads];
326
327    /** Skid buffer between rename and decode. */
328    InstQueue skidBuffer[Impl::MaxThreads];
329
330    /** Rename map interface. */
331    RenameMap *renameMap[Impl::MaxThreads];
332
333    /** Free list interface. */
334    FreeList *freeList;
335
336    /** Pointer to the list of active threads. */
337    std::list<unsigned> *activeThreads;
338
339    /** Pointer to the scoreboard. */
340    Scoreboard *scoreboard;
341
342    /** Count of instructions in progress that have been sent off to the IQ
343     * and ROB, but are not yet included in their occupancy counts.
344     */
345    int instsInProgress[Impl::MaxThreads];
346
347    /** Variable that tracks if decode has written to the time buffer this
348     * cycle. Used to tell CPU if there is activity this cycle.
349     */
350    bool wroteToTimeBuffer;
351
352    /** Structures whose free entries impact the amount of instructions that
353     * can be renamed.
354     */
355    struct FreeEntries {
356        unsigned iqEntries;
357        unsigned lsqEntries;
358        unsigned robEntries;
359    };
360
361    /** Per-thread tracking of the number of free entries of back-end
362     * structures.
363     */
364    FreeEntries freeEntries[Impl::MaxThreads];
365
366    /** Records if the ROB is empty. In SMT mode the ROB may be dynamically
367     * partitioned between threads, so the ROB must tell rename when it is
368     * empty.
369     */
370    bool emptyROB[Impl::MaxThreads];
371
372    /** Source of possible stalls. */
373    struct Stalls {
374        bool iew;
375        bool commit;
376    };
377
378    /** Tracks which stages are telling decode to stall. */
379    Stalls stalls[Impl::MaxThreads];
380
381    /** The serialize instruction that rename has stalled on. */
382    DynInstPtr serializeInst[Impl::MaxThreads];
383
384    /** Records if rename needs to serialize on the next instruction for any
385     * thread.
386     */
387    bool serializeOnNextInst[Impl::MaxThreads];
388
389    /** Delay between iew and rename, in ticks. */
390    int iewToRenameDelay;
391
392    /** Delay between decode and rename, in ticks. */
393    int decodeToRenameDelay;
394
395    /** Delay between commit and rename, in ticks. */
396    unsigned commitToRenameDelay;
397
398    /** Rename width, in instructions. */
399    unsigned renameWidth;
400
401    /** Commit width, in instructions.  Used so rename knows how many
402     *  instructions might have freed registers in the previous cycle.
403     */
404    unsigned commitWidth;
405
406    /** The index of the instruction in the time buffer to IEW that rename is
407     * currently using.
408     */
409    unsigned toIEWIndex;
410
411    /** Whether or not rename needs to block this cycle. */
412    bool blockThisCycle;
413
414    /** The number of threads active in rename. */
415    unsigned numThreads;
416
417    /** The maximum skid buffer size. */
418    unsigned skidBufferMax;
419
420    /** Enum to record the source of a structure full stall.  Can come from
421     * either ROB, IQ, LSQ, and it is priortized in that order.
422     */
423    enum FullSource {
424        ROB,
425        IQ,
426        LSQ,
427        NONE
428    };
429
430    /** Function used to increment the stat that corresponds to the source of
431     * the stall.
432     */
433    inline void incrFullStat(const FullSource &source);
434
435    /** Stat for total number of cycles spent squashing. */
436    Stats::Scalar<> renameSquashCycles;
437    /** Stat for total number of cycles spent idle. */
438    Stats::Scalar<> renameIdleCycles;
439    /** Stat for total number of cycles spent blocking. */
440    Stats::Scalar<> renameBlockCycles;
441    /** Stat for total number of cycles spent stalling for a serializing inst. */
442    Stats::Scalar<> renameSerializeStallCycles;
443    /** Stat for total number of cycles spent running normally. */
444    Stats::Scalar<> renameRunCycles;
445    /** Stat for total number of cycles spent unblocking. */
446    Stats::Scalar<> renameUnblockCycles;
447    /** Stat for total number of renamed instructions. */
448    Stats::Scalar<> renameRenamedInsts;
449    /** Stat for total number of squashed instructions that rename discards. */
450    Stats::Scalar<> renameSquashedInsts;
451    /** Stat for total number of times that the ROB starts a stall in rename. */
452    Stats::Scalar<> renameROBFullEvents;
453    /** Stat for total number of times that the IQ starts a stall in rename. */
454    Stats::Scalar<> renameIQFullEvents;
455    /** Stat for total number of times that the LSQ starts a stall in rename. */
456    Stats::Scalar<> renameLSQFullEvents;
457    /** Stat for total number of times that rename runs out of free registers
458     * to use to rename. */
459    Stats::Scalar<> renameFullRegistersEvents;
460    /** Stat for total number of renamed destination registers. */
461    Stats::Scalar<> renameRenamedOperands;
462    /** Stat for total number of source register rename lookups. */
463    Stats::Scalar<> renameRenameLookups;
464    /** Stat for total number of committed renaming mappings. */
465    Stats::Scalar<> renameCommittedMaps;
466    /** Stat for total number of mappings that were undone due to a squash. */
467    Stats::Scalar<> renameUndoneMaps;
468    /** Number of serialize instructions handled. */
469    Stats::Scalar<> renamedSerializing;
470    /** Number of instructions marked as temporarily serializing. */
471    Stats::Scalar<> renamedTempSerializing;
472    /** Number of instructions inserted into skid buffers. */
473    Stats::Scalar<> renameSkidInsts;
474};
475
476#endif // __CPU_O3_RENAME_HH__
477