rename.hh revision 11246:93d2a1526103
16019Shines@cs.fsu.edu/* 210037SARM gem5 Developers * Copyright (c) 2012 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416735Sgblack@eecs.umich.edu * Authors: Kevin Lim 426735Sgblack@eecs.umich.edu */ 4310037SARM gem5 Developers 4410037SARM gem5 Developers#ifndef __CPU_O3_RENAME_HH__ 456019Shines@cs.fsu.edu#define __CPU_O3_RENAME_HH__ 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu#include <list> 4810037SARM gem5 Developers#include <utility> 4910037SARM gem5 Developers 5010037SARM gem5 Developers#include "base/statistics.hh" 5110037SARM gem5 Developers#include "config/the_isa.hh" 528229Snate@binkert.org#include "cpu/timebuf.hh" 538229Snate@binkert.org#include "sim/probe/probe.hh" 546019Shines@cs.fsu.edu 558232Snate@binkert.orgstruct DerivO3CPUParams; 568782Sgblack@eecs.umich.edu 576019Shines@cs.fsu.edu/** 586019Shines@cs.fsu.edu * DefaultRename handles both single threaded and SMT rename. Its 596019Shines@cs.fsu.edu * width is specified by the parameters; each cycle it tries to rename 606019Shines@cs.fsu.edu * that many instructions. It holds onto the rename history of all 6110037SARM gem5 Developers * instructions with destination registers, storing the 6210037SARM gem5 Developers * arch. register, the new physical register, and the old physical 6310037SARM gem5 Developers * register, to allow for undoing of mappings if squashing happens, or 6410037SARM gem5 Developers * freeing up registers upon commit. Rename handles blocking if the 6510037SARM gem5 Developers * ROB, IQ, or LSQ is going to be full. Rename also handles barriers, 6610037SARM gem5 Developers * and does so by stalling on the instruction until the ROB is empty 6710037SARM gem5 Developers * and there are no instructions in flight to the ROB. 6810037SARM gem5 Developers */ 6910037SARM gem5 Developerstemplate<class Impl> 7010037SARM gem5 Developersclass DefaultRename 7110037SARM gem5 Developers{ 7210037SARM gem5 Developers public: 7310037SARM gem5 Developers // Typedefs from the Impl. 7410037SARM gem5 Developers typedef typename Impl::CPUPol CPUPol; 7510037SARM gem5 Developers typedef typename Impl::DynInstPtr DynInstPtr; 7610037SARM gem5 Developers typedef typename Impl::O3CPU O3CPU; 7710037SARM gem5 Developers 7810037SARM gem5 Developers // Typedefs from the CPUPol 7910037SARM gem5 Developers typedef typename CPUPol::DecodeStruct DecodeStruct; 8010037SARM gem5 Developers typedef typename CPUPol::RenameStruct RenameStruct; 8110037SARM gem5 Developers typedef typename CPUPol::TimeStruct TimeStruct; 8210037SARM gem5 Developers typedef typename CPUPol::FreeList FreeList; 8310037SARM gem5 Developers typedef typename CPUPol::RenameMap RenameMap; 8410037SARM gem5 Developers // These are used only for initialization. 8510037SARM gem5 Developers typedef typename CPUPol::IEW IEW; 8610037SARM gem5 Developers typedef typename CPUPol::Commit Commit; 8710037SARM gem5 Developers 8810037SARM gem5 Developers // Typedefs from the ISA. 8910037SARM gem5 Developers typedef TheISA::RegIndex RegIndex; 9010037SARM gem5 Developers 9110037SARM gem5 Developers // A deque is used to queue the instructions. Barrier insts must 9210037SARM gem5 Developers // be added to the front of the queue, which is the only reason for 9310037SARM gem5 Developers // using a deque instead of a queue. (Most other stages use a 9410037SARM gem5 Developers // queue) 9510037SARM gem5 Developers typedef std::deque<DynInstPtr> InstQueue; 9610037SARM gem5 Developers 9710037SARM gem5 Developers public: 9810037SARM gem5 Developers /** Overall rename status. Used to determine if the CPU can 9910037SARM gem5 Developers * deschedule itself due to a lack of activity. 10010037SARM gem5 Developers */ 1016019Shines@cs.fsu.edu enum RenameStatus { 10210037SARM gem5 Developers Active, 10310037SARM gem5 Developers Inactive 10410037SARM gem5 Developers }; 1056019Shines@cs.fsu.edu 10610037SARM gem5 Developers /** Individual thread status. */ 10710037SARM gem5 Developers enum ThreadStatus { 10810037SARM gem5 Developers Running, 10910037SARM gem5 Developers Idle, 11010037SARM gem5 Developers StartSquash, 11110037SARM gem5 Developers Squashing, 11210037SARM gem5 Developers Blocked, 11310037SARM gem5 Developers Unblocking, 11410037SARM gem5 Developers SerializeStall 11510037SARM gem5 Developers }; 11610037SARM gem5 Developers 11710037SARM gem5 Developers private: 11810037SARM gem5 Developers /** Rename status. */ 11910037SARM gem5 Developers RenameStatus _status; 12010037SARM gem5 Developers 12110037SARM gem5 Developers /** Per-thread status. */ 12210037SARM gem5 Developers ThreadStatus renameStatus[Impl::MaxThreads]; 12310037SARM gem5 Developers 12410037SARM gem5 Developers /** Probe points. */ 12510037SARM gem5 Developers typedef typename std::pair<InstSeqNum, short int> SeqNumRegPair; 12610037SARM gem5 Developers /** To probe when register renaming for an instruction is complete */ 12710037SARM gem5 Developers ProbePointArg<DynInstPtr> *ppRename; 12810037SARM gem5 Developers /** 12910037SARM gem5 Developers * To probe when an instruction is squashed and the register mapping 13010037SARM gem5 Developers * for it needs to be undone 13110037SARM gem5 Developers */ 13210037SARM gem5 Developers ProbePointArg<SeqNumRegPair> *ppSquashInRename; 13310037SARM gem5 Developers 13410037SARM gem5 Developers public: 13510037SARM gem5 Developers /** DefaultRename constructor. */ 13610037SARM gem5 Developers DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params); 13710037SARM gem5 Developers 13810037SARM gem5 Developers /** Returns the name of rename. */ 13910037SARM gem5 Developers std::string name() const; 14010037SARM gem5 Developers 14110037SARM gem5 Developers /** Registers statistics. */ 14210037SARM gem5 Developers void regStats(); 14310037SARM gem5 Developers 14410037SARM gem5 Developers /** Registers probes. */ 14510037SARM gem5 Developers void regProbePoints(); 1466019Shines@cs.fsu.edu 14710037SARM gem5 Developers /** Sets the main backwards communication time buffer pointer. */ 14810037SARM gem5 Developers void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 14910037SARM gem5 Developers 1506019Shines@cs.fsu.edu /** Sets pointer to time buffer used to communicate to the next stage. */ 15110037SARM gem5 Developers void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 15210037SARM gem5 Developers 15310037SARM gem5 Developers /** Sets pointer to time buffer coming from decode. */ 15410037SARM gem5 Developers void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 15510037SARM gem5 Developers 15610037SARM gem5 Developers /** Sets pointer to IEW stage. Used only for initialization. */ 15710037SARM gem5 Developers void setIEWStage(IEW *iew_stage) 15810037SARM gem5 Developers { iew_ptr = iew_stage; } 15910037SARM gem5 Developers 16010037SARM gem5 Developers /** Sets pointer to commit stage. Used only for initialization. */ 16110037SARM gem5 Developers void setCommitStage(Commit *commit_stage) 16210037SARM gem5 Developers { commit_ptr = commit_stage; } 16310037SARM gem5 Developers 16410037SARM gem5 Developers private: 16510037SARM gem5 Developers /** Pointer to IEW stage. Used only for initialization. */ 16610037SARM gem5 Developers IEW *iew_ptr; 16710037SARM gem5 Developers 16810037SARM gem5 Developers /** Pointer to commit stage. Used only for initialization. */ 16910037SARM gem5 Developers Commit *commit_ptr; 17010037SARM gem5 Developers 17110037SARM gem5 Developers public: 17210037SARM gem5 Developers /** Initializes variables for the stage. */ 17310037SARM gem5 Developers void startupStage(); 17410037SARM gem5 Developers 17510037SARM gem5 Developers /** Sets pointer to list of active threads. */ 17610037SARM gem5 Developers void setActiveThreads(std::list<ThreadID> *at_ptr); 17710037SARM gem5 Developers 17810037SARM gem5 Developers /** Sets pointer to rename maps (per-thread structures). */ 17910037SARM gem5 Developers void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 18010037SARM gem5 Developers 18110037SARM gem5 Developers /** Sets pointer to the free list. */ 18210037SARM gem5 Developers void setFreeList(FreeList *fl_ptr); 18310037SARM gem5 Developers 18410037SARM gem5 Developers /** Sets pointer to the scoreboard. */ 18510037SARM gem5 Developers void setScoreboard(Scoreboard *_scoreboard); 18610037SARM gem5 Developers 18710037SARM gem5 Developers /** Perform sanity checks after a drain. */ 18810037SARM gem5 Developers void drainSanityCheck() const; 18910037SARM gem5 Developers 19010037SARM gem5 Developers /** Has the stage drained? */ 19110037SARM gem5 Developers bool isDrained() const; 1926019Shines@cs.fsu.edu 19310037SARM gem5 Developers /** Takes over from another CPU's thread. */ 19410037SARM gem5 Developers void takeOverFrom(); 19510037SARM gem5 Developers 1966019Shines@cs.fsu.edu /** Squashes all instructions in a thread. */ 19710037SARM gem5 Developers void squash(const InstSeqNum &squash_seq_num, ThreadID tid); 19810037SARM gem5 Developers 19910037SARM gem5 Developers /** Ticks rename, which processes all input signals and attempts to rename 20010037SARM gem5 Developers * as many instructions as possible. 20110037SARM gem5 Developers */ 20210037SARM gem5 Developers void tick(); 20310037SARM gem5 Developers 20410037SARM gem5 Developers /** Debugging function used to dump history buffer of renamings. */ 20510037SARM gem5 Developers void dumpHistory(); 20610037SARM gem5 Developers 20710037SARM gem5 Developers private: 20810037SARM gem5 Developers /** Reset this pipeline stage */ 20910037SARM gem5 Developers void resetStage(); 21010037SARM gem5 Developers 21110037SARM gem5 Developers /** Determines what to do based on rename's current status. 21210037SARM gem5 Developers * @param status_change rename() sets this variable if there was a status 21310037SARM gem5 Developers * change (ie switching from blocking to unblocking). 21410037SARM gem5 Developers * @param tid Thread id to rename instructions from. 21510037SARM gem5 Developers */ 21610037SARM gem5 Developers void rename(bool &status_change, ThreadID tid); 21710037SARM gem5 Developers 21810037SARM gem5 Developers /** Renames instructions for the given thread. Also handles serializing 21910037SARM gem5 Developers * instructions. 22010037SARM gem5 Developers */ 22110037SARM gem5 Developers void renameInsts(ThreadID tid); 22210037SARM gem5 Developers 22310037SARM gem5 Developers /** Inserts unused instructions from a given thread into the skid buffer, 22410037SARM gem5 Developers * to be renamed once rename unblocks. 22510037SARM gem5 Developers */ 22610037SARM gem5 Developers void skidInsert(ThreadID tid); 22710037SARM gem5 Developers 22810037SARM gem5 Developers /** Separates instructions from decode into individual lists of instructions 22910037SARM gem5 Developers * sorted by thread. 23010037SARM gem5 Developers */ 23110037SARM gem5 Developers void sortInsts(); 23210037SARM gem5 Developers 23310037SARM gem5 Developers /** Returns if all of the skid buffers are empty. */ 23410037SARM gem5 Developers bool skidsEmpty(); 23510037SARM gem5 Developers 23610037SARM gem5 Developers /** Updates overall rename status based on all of the threads' statuses. */ 23710037SARM gem5 Developers void updateStatus(); 23810037SARM gem5 Developers 23910037SARM gem5 Developers /** Switches rename to blocking, and signals back that rename has become 24010037SARM gem5 Developers * blocked. 24110037SARM gem5 Developers * @return Returns true if there is a status change. 24210037SARM gem5 Developers */ 24310037SARM gem5 Developers bool block(ThreadID tid); 24410037SARM gem5 Developers 24510037SARM gem5 Developers /** Switches rename to unblocking if the skid buffer is empty, and signals 24610037SARM gem5 Developers * back that rename has unblocked. 24710037SARM gem5 Developers * @return Returns true if there is a status change. 24810037SARM gem5 Developers */ 24910037SARM gem5 Developers bool unblock(ThreadID tid); 25010037SARM gem5 Developers 25110037SARM gem5 Developers /** Executes actual squash, removing squashed instructions. */ 25210037SARM gem5 Developers void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid); 25310037SARM gem5 Developers 25410037SARM gem5 Developers /** Removes a committed instruction's rename history. */ 25510037SARM gem5 Developers void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid); 25610037SARM gem5 Developers 25710037SARM gem5 Developers /** Renames the source registers of an instruction. */ 25810037SARM gem5 Developers inline void renameSrcRegs(DynInstPtr &inst, ThreadID tid); 25910037SARM gem5 Developers 26010037SARM gem5 Developers /** Renames the destination registers of an instruction. */ 26110037SARM gem5 Developers inline void renameDestRegs(DynInstPtr &inst, ThreadID tid); 26210037SARM gem5 Developers 26310037SARM gem5 Developers /** Calculates the number of free ROB entries for a specific thread. */ 26410037SARM gem5 Developers inline int calcFreeROBEntries(ThreadID tid); 26510037SARM gem5 Developers 26610037SARM gem5 Developers /** Calculates the number of free IQ entries for a specific thread. */ 26710037SARM gem5 Developers inline int calcFreeIQEntries(ThreadID tid); 26810037SARM gem5 Developers 26910037SARM gem5 Developers /** Calculates the number of free LQ entries for a specific thread. */ 27010037SARM gem5 Developers inline int calcFreeLQEntries(ThreadID tid); 27110037SARM gem5 Developers 27210037SARM gem5 Developers /** Calculates the number of free SQ entries for a specific thread. */ 27310037SARM gem5 Developers inline int calcFreeSQEntries(ThreadID tid); 27410037SARM gem5 Developers 27510037SARM gem5 Developers /** Returns the number of valid instructions coming from decode. */ 27610037SARM gem5 Developers unsigned validInsts(); 27710037SARM gem5 Developers 27810037SARM gem5 Developers /** Reads signals telling rename to block/unblock. */ 27910037SARM gem5 Developers void readStallSignals(ThreadID tid); 28010037SARM gem5 Developers 28110037SARM gem5 Developers /** Checks if any stages are telling rename to block. */ 28210037SARM gem5 Developers bool checkStall(ThreadID tid); 28310037SARM gem5 Developers 28410037SARM gem5 Developers /** Gets the number of free entries for a specific thread. */ 28510037SARM gem5 Developers void readFreeEntries(ThreadID tid); 28610037SARM gem5 Developers 28710037SARM gem5 Developers /** Checks the signals and updates the status. */ 28810037SARM gem5 Developers bool checkSignalsAndUpdate(ThreadID tid); 28910037SARM gem5 Developers 29010037SARM gem5 Developers /** Either serializes on the next instruction available in the InstQueue, 29110037SARM gem5 Developers * or records that it must serialize on the next instruction to enter 29210037SARM gem5 Developers * rename. 29310037SARM gem5 Developers * @param inst_list The list of younger, unprocessed instructions for the 29410037SARM gem5 Developers * thread that has the serializeAfter instruction. 2956019Shines@cs.fsu.edu * @param tid The thread id. 29610037SARM gem5 Developers */ 2977362Sgblack@eecs.umich.edu void serializeAfter(InstQueue &inst_list, ThreadID tid); 2986735Sgblack@eecs.umich.edu 29910037SARM gem5 Developers /** Holds the information for each destination register rename. It holds 3006019Shines@cs.fsu.edu * the instruction's sequence number, the arch register, the old physical 30110037SARM gem5 Developers * register for that arch. register, and the new physical register. 30210037SARM gem5 Developers */ 3037400SAli.Saidi@ARM.com struct RenameHistory { 3046735Sgblack@eecs.umich.edu RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 3056735Sgblack@eecs.umich.edu PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 30610037SARM gem5 Developers : instSeqNum(_instSeqNum), archReg(_archReg), 3076735Sgblack@eecs.umich.edu newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg) 30810037SARM gem5 Developers { 30910037SARM gem5 Developers } 31010037SARM gem5 Developers 31110037SARM gem5 Developers /** The sequence number of the instruction that renamed. */ 3127400SAli.Saidi@ARM.com InstSeqNum instSeqNum; 31310037SARM gem5 Developers /** The architectural register index that was renamed. */ 31410037SARM gem5 Developers RegIndex archReg; 31510037SARM gem5 Developers /** The new physical register that the arch. register is renamed to. */ 31610037SARM gem5 Developers PhysRegIndex newPhysReg; 31710037SARM gem5 Developers /** The old physical register that the arch. register was renamed to. */ 31810037SARM gem5 Developers PhysRegIndex prevPhysReg; 31910037SARM gem5 Developers }; 32010037SARM gem5 Developers 32110037SARM gem5 Developers /** A per-thread list of all destination register renames, used to either 32210037SARM gem5 Developers * undo rename mappings or free old physical registers. 32310037SARM gem5 Developers */ 32410037SARM gem5 Developers std::list<RenameHistory> historyBuffer[Impl::MaxThreads]; 32510037SARM gem5 Developers 32610037SARM gem5 Developers /** Pointer to CPU. */ 32710037SARM gem5 Developers O3CPU *cpu; 32810037SARM gem5 Developers 32910037SARM gem5 Developers /** Pointer to main time buffer used for backwards communication. */ 3306019Shines@cs.fsu.edu TimeBuffer<TimeStruct> *timeBuffer; 3316019Shines@cs.fsu.edu 33210037SARM gem5 Developers /** Wire to get IEW's output from backwards time buffer. */ 33310037SARM gem5 Developers typename TimeBuffer<TimeStruct>::wire fromIEW; 33410037SARM gem5 Developers 33510037SARM gem5 Developers /** Wire to get commit's output from backwards time buffer. */ 33610037SARM gem5 Developers typename TimeBuffer<TimeStruct>::wire fromCommit; 33710037SARM gem5 Developers 33810037SARM gem5 Developers /** Wire to write infromation heading to previous stages. */ 33910037SARM gem5 Developers typename TimeBuffer<TimeStruct>::wire toDecode; 34010037SARM gem5 Developers 34110037SARM gem5 Developers /** Rename instruction queue. */ 34210037SARM gem5 Developers TimeBuffer<RenameStruct> *renameQueue; 34310037SARM gem5 Developers 34410037SARM gem5 Developers /** Wire to write any information heading to IEW. */ 34510037SARM gem5 Developers typename TimeBuffer<RenameStruct>::wire toIEW; 34610037SARM gem5 Developers 34710037SARM gem5 Developers /** Decode instruction queue interface. */ 34810037SARM gem5 Developers TimeBuffer<DecodeStruct> *decodeQueue; 34910037SARM gem5 Developers 35010037SARM gem5 Developers /** Wire to get decode's output from decode queue. */ 35110037SARM gem5 Developers typename TimeBuffer<DecodeStruct>::wire fromDecode; 35210037SARM gem5 Developers 35310037SARM gem5 Developers /** Queue of all instructions coming from decode this cycle. */ 35410037SARM gem5 Developers InstQueue insts[Impl::MaxThreads]; 35510037SARM gem5 Developers 35610037SARM gem5 Developers /** Skid buffer between rename and decode. */ 35710037SARM gem5 Developers InstQueue skidBuffer[Impl::MaxThreads]; 35810037SARM gem5 Developers 35910037SARM gem5 Developers /** Rename map interface. */ 36010037SARM gem5 Developers RenameMap *renameMap[Impl::MaxThreads]; 36110037SARM gem5 Developers 36210037SARM gem5 Developers /** Free list interface. */ 36310037SARM gem5 Developers FreeList *freeList; 36410037SARM gem5 Developers 36510037SARM gem5 Developers /** Pointer to the list of active threads. */ 36610037SARM gem5 Developers std::list<ThreadID> *activeThreads; 36710037SARM gem5 Developers 36810037SARM gem5 Developers /** Pointer to the scoreboard. */ 36910037SARM gem5 Developers Scoreboard *scoreboard; 37010037SARM gem5 Developers 37110037SARM gem5 Developers /** Count of instructions in progress that have been sent off to the IQ 37210037SARM gem5 Developers * and ROB, but are not yet included in their occupancy counts. 37310037SARM gem5 Developers */ 37410037SARM gem5 Developers int instsInProgress[Impl::MaxThreads]; 37510037SARM gem5 Developers 37610037SARM gem5 Developers /** Count of Load instructions in progress that have been sent off to the IQ 37710037SARM gem5 Developers * and ROB, but are not yet included in their occupancy counts. 37810037SARM gem5 Developers */ 37910037SARM gem5 Developers int loadsInProgress[Impl::MaxThreads]; 38010037SARM gem5 Developers 38110037SARM gem5 Developers /** Count of Store instructions in progress that have been sent off to the IQ 38210037SARM gem5 Developers * and ROB, but are not yet included in their occupancy counts. 38310037SARM gem5 Developers */ 38410037SARM gem5 Developers int storesInProgress[Impl::MaxThreads]; 38510037SARM gem5 Developers 38610037SARM gem5 Developers /** Variable that tracks if decode has written to the time buffer this 38710037SARM gem5 Developers * cycle. Used to tell CPU if there is activity this cycle. 38810037SARM gem5 Developers */ 38910037SARM gem5 Developers bool wroteToTimeBuffer; 39010037SARM gem5 Developers 39110037SARM gem5 Developers /** Structures whose free entries impact the amount of instructions that 39210037SARM gem5 Developers * can be renamed. 39310037SARM gem5 Developers */ 39410037SARM gem5 Developers struct FreeEntries { 39510037SARM gem5 Developers unsigned iqEntries; 39610037SARM gem5 Developers unsigned robEntries; 39710037SARM gem5 Developers unsigned lqEntries; 39810037SARM gem5 Developers unsigned sqEntries; 39910037SARM gem5 Developers }; 40010037SARM gem5 Developers 40110037SARM gem5 Developers /** Per-thread tracking of the number of free entries of back-end 40210037SARM gem5 Developers * structures. 40310037SARM gem5 Developers */ 40410037SARM gem5 Developers FreeEntries freeEntries[Impl::MaxThreads]; 40510037SARM gem5 Developers 40610037SARM gem5 Developers /** Records if the ROB is empty. In SMT mode the ROB may be dynamically 40710037SARM gem5 Developers * partitioned between threads, so the ROB must tell rename when it is 40810037SARM gem5 Developers * empty. 40910037SARM gem5 Developers */ 41010037SARM gem5 Developers bool emptyROB[Impl::MaxThreads]; 41110037SARM gem5 Developers 41210037SARM gem5 Developers /** Source of possible stalls. */ 41310037SARM gem5 Developers struct Stalls { 41410037SARM gem5 Developers bool iew; 41510037SARM gem5 Developers bool commit; 41610037SARM gem5 Developers }; 41710037SARM gem5 Developers 41810037SARM gem5 Developers /** Tracks which stages are telling decode to stall. */ 41910037SARM gem5 Developers Stalls stalls[Impl::MaxThreads]; 42010037SARM gem5 Developers 42110037SARM gem5 Developers /** The serialize instruction that rename has stalled on. */ 42210037SARM gem5 Developers DynInstPtr serializeInst[Impl::MaxThreads]; 42310037SARM gem5 Developers 42410037SARM gem5 Developers /** Records if rename needs to serialize on the next instruction for any 42510037SARM gem5 Developers * thread. 42610037SARM gem5 Developers */ 42710037SARM gem5 Developers bool serializeOnNextInst[Impl::MaxThreads]; 42810037SARM gem5 Developers 4297678Sgblack@eecs.umich.edu /** Delay between iew and rename, in ticks. */ 4306019Shines@cs.fsu.edu int iewToRenameDelay; 43110037SARM gem5 Developers 43210037SARM gem5 Developers /** Delay between decode and rename, in ticks. */ 43310037SARM gem5 Developers int decodeToRenameDelay; 43410037SARM gem5 Developers 43510037SARM gem5 Developers /** Delay between commit and rename, in ticks. */ 43610037SARM gem5 Developers unsigned commitToRenameDelay; 43710037SARM gem5 Developers 43810037SARM gem5 Developers /** Rename width, in instructions. */ 43910037SARM gem5 Developers unsigned renameWidth; 44010037SARM gem5 Developers 44110037SARM gem5 Developers /** Commit width, in instructions. Used so rename knows how many 44210037SARM gem5 Developers * instructions might have freed registers in the previous cycle. 44310037SARM gem5 Developers */ 44410037SARM gem5 Developers unsigned commitWidth; 44510037SARM gem5 Developers 44610037SARM gem5 Developers /** The index of the instruction in the time buffer to IEW that rename is 44710037SARM gem5 Developers * currently using. 44810037SARM gem5 Developers */ 44910037SARM gem5 Developers unsigned toIEWIndex; 45010037SARM gem5 Developers 45110037SARM gem5 Developers /** Whether or not rename needs to block this cycle. */ 45210037SARM gem5 Developers bool blockThisCycle; 45310037SARM gem5 Developers 45410037SARM gem5 Developers /** Whether or not rename needs to resume a serialize instruction 45510037SARM gem5 Developers * after squashing. */ 45610037SARM gem5 Developers bool resumeSerialize; 45710037SARM gem5 Developers 45810037SARM gem5 Developers /** Whether or not rename needs to resume clearing out the skidbuffer 45910037SARM gem5 Developers * after squashing. */ 46010037SARM gem5 Developers bool resumeUnblocking; 4616735Sgblack@eecs.umich.edu 4628782Sgblack@eecs.umich.edu /** The number of threads active in rename. */ 4638782Sgblack@eecs.umich.edu ThreadID numThreads; 4646735Sgblack@eecs.umich.edu 4656019Shines@cs.fsu.edu /** The maximum skid buffer size. */ 4666735Sgblack@eecs.umich.edu unsigned skidBufferMax; 46710037SARM gem5 Developers 4688303SAli.Saidi@ARM.com PhysRegIndex maxPhysicalRegs; 4698303SAli.Saidi@ARM.com 4708303SAli.Saidi@ARM.com /** Enum to record the source of a structure full stall. Can come from 4718303SAli.Saidi@ARM.com * either ROB, IQ, LSQ, and it is priortized in that order. 4728303SAli.Saidi@ARM.com */ 4738303SAli.Saidi@ARM.com enum FullSource { 4747720Sgblack@eecs.umich.edu ROB, 4758205SAli.Saidi@ARM.com IQ, 4768205SAli.Saidi@ARM.com LQ, 4778205SAli.Saidi@ARM.com SQ, 4786735Sgblack@eecs.umich.edu NONE 47910037SARM gem5 Developers }; 48010037SARM gem5 Developers 48110037SARM gem5 Developers /** Function used to increment the stat that corresponds to the source of 48210037SARM gem5 Developers * the stall. 48310037SARM gem5 Developers */ 48410037SARM gem5 Developers inline void incrFullStat(const FullSource &source); 48510037SARM gem5 Developers 48610037SARM gem5 Developers /** Stat for total number of cycles spent squashing. */ 48710037SARM gem5 Developers Stats::Scalar renameSquashCycles; 48810037SARM gem5 Developers /** Stat for total number of cycles spent idle. */ 48910037SARM gem5 Developers Stats::Scalar renameIdleCycles; 49010037SARM gem5 Developers /** Stat for total number of cycles spent blocking. */ 49110037SARM gem5 Developers Stats::Scalar renameBlockCycles; 49210037SARM gem5 Developers /** Stat for total number of cycles spent stalling for a serializing inst. */ 49310037SARM gem5 Developers Stats::Scalar renameSerializeStallCycles; 49410037SARM gem5 Developers /** Stat for total number of cycles spent running normally. */ 49510037SARM gem5 Developers Stats::Scalar renameRunCycles; 49610037SARM gem5 Developers /** Stat for total number of cycles spent unblocking. */ 49710037SARM gem5 Developers Stats::Scalar renameUnblockCycles; 49810037SARM gem5 Developers /** Stat for total number of renamed instructions. */ 49910037SARM gem5 Developers Stats::Scalar renameRenamedInsts; 50010037SARM gem5 Developers /** Stat for total number of squashed instructions that rename discards. */ 50110037SARM gem5 Developers Stats::Scalar renameSquashedInsts; 50210037SARM gem5 Developers /** Stat for total number of times that the ROB starts a stall in rename. */ 50310037SARM gem5 Developers Stats::Scalar renameROBFullEvents; 50410037SARM gem5 Developers /** Stat for total number of times that the IQ starts a stall in rename. */ 50510037SARM gem5 Developers Stats::Scalar renameIQFullEvents; 50610037SARM gem5 Developers /** Stat for total number of times that the LQ starts a stall in rename. */ 50710037SARM gem5 Developers Stats::Scalar renameLQFullEvents; 50810037SARM gem5 Developers /** Stat for total number of times that the SQ starts a stall in rename. */ 50910037SARM gem5 Developers Stats::Scalar renameSQFullEvents; 51010037SARM gem5 Developers /** Stat for total number of times that rename runs out of free registers 51110037SARM gem5 Developers * to use to rename. */ 51210037SARM gem5 Developers Stats::Scalar renameFullRegistersEvents; 51310037SARM gem5 Developers /** Stat for total number of renamed destination registers. */ 51410037SARM gem5 Developers Stats::Scalar renameRenamedOperands; 51510037SARM gem5 Developers /** Stat for total number of source register rename lookups. */ 51610037SARM gem5 Developers Stats::Scalar renameRenameLookups; 51710037SARM gem5 Developers Stats::Scalar intRenameLookups; 51810037SARM gem5 Developers Stats::Scalar fpRenameLookups; 51910037SARM gem5 Developers /** Stat for total number of committed renaming mappings. */ 52010037SARM gem5 Developers Stats::Scalar renameCommittedMaps; 52110037SARM gem5 Developers /** Stat for total number of mappings that were undone due to a squash. */ 52210037SARM gem5 Developers Stats::Scalar renameUndoneMaps; 52310037SARM gem5 Developers /** Number of serialize instructions handled. */ 52410037SARM gem5 Developers Stats::Scalar renamedSerializing; 52510037SARM gem5 Developers /** Number of instructions marked as temporarily serializing. */ 52610037SARM gem5 Developers Stats::Scalar renamedTempSerializing; 5276735Sgblack@eecs.umich.edu /** Number of instructions inserted into skid buffers. */ 5286735Sgblack@eecs.umich.edu Stats::Scalar renameSkidInsts; 5296735Sgblack@eecs.umich.edu}; 53010037SARM gem5 Developers 5318518Sgeoffrey.blake@arm.com#endif // __CPU_O3_RENAME_HH__ 5328518Sgeoffrey.blake@arm.com