rename.hh revision 10239:592f0bb6bd6f
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * Copyright (c) 2013 Advanced Micro Devices, Inc. 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_O3_RENAME_HH__ 45#define __CPU_O3_RENAME_HH__ 46 47#include <list> 48 49#include "base/statistics.hh" 50#include "config/the_isa.hh" 51#include "cpu/timebuf.hh" 52 53struct DerivO3CPUParams; 54 55/** 56 * DefaultRename handles both single threaded and SMT rename. Its 57 * width is specified by the parameters; each cycle it tries to rename 58 * that many instructions. It holds onto the rename history of all 59 * instructions with destination registers, storing the 60 * arch. register, the new physical register, and the old physical 61 * register, to allow for undoing of mappings if squashing happens, or 62 * freeing up registers upon commit. Rename handles blocking if the 63 * ROB, IQ, or LSQ is going to be full. Rename also handles barriers, 64 * and does so by stalling on the instruction until the ROB is empty 65 * and there are no instructions in flight to the ROB. 66 */ 67template<class Impl> 68class DefaultRename 69{ 70 public: 71 // Typedefs from the Impl. 72 typedef typename Impl::CPUPol CPUPol; 73 typedef typename Impl::DynInstPtr DynInstPtr; 74 typedef typename Impl::O3CPU O3CPU; 75 76 // Typedefs from the CPUPol 77 typedef typename CPUPol::DecodeStruct DecodeStruct; 78 typedef typename CPUPol::RenameStruct RenameStruct; 79 typedef typename CPUPol::TimeStruct TimeStruct; 80 typedef typename CPUPol::FreeList FreeList; 81 typedef typename CPUPol::RenameMap RenameMap; 82 // These are used only for initialization. 83 typedef typename CPUPol::IEW IEW; 84 typedef typename CPUPol::Commit Commit; 85 86 // Typedefs from the ISA. 87 typedef TheISA::RegIndex RegIndex; 88 89 // A list is used to queue the instructions. Barrier insts must 90 // be added to the front of the list, which is the only reason for 91 // using a list instead of a queue. (Most other stages use a 92 // queue) 93 typedef std::list<DynInstPtr> InstQueue; 94 typedef typename std::list<DynInstPtr>::iterator ListIt; 95 96 public: 97 /** Overall rename status. Used to determine if the CPU can 98 * deschedule itself due to a lack of activity. 99 */ 100 enum RenameStatus { 101 Active, 102 Inactive 103 }; 104 105 /** Individual thread status. */ 106 enum ThreadStatus { 107 Running, 108 Idle, 109 StartSquash, 110 Squashing, 111 Blocked, 112 Unblocking, 113 SerializeStall 114 }; 115 116 private: 117 /** Rename status. */ 118 RenameStatus _status; 119 120 /** Per-thread status. */ 121 ThreadStatus renameStatus[Impl::MaxThreads]; 122 123 public: 124 /** DefaultRename constructor. */ 125 DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params); 126 127 /** Returns the name of rename. */ 128 std::string name() const; 129 130 /** Registers statistics. */ 131 void regStats(); 132 133 /** Sets the main backwards communication time buffer pointer. */ 134 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 135 136 /** Sets pointer to time buffer used to communicate to the next stage. */ 137 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 138 139 /** Sets pointer to time buffer coming from decode. */ 140 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 141 142 /** Sets pointer to IEW stage. Used only for initialization. */ 143 void setIEWStage(IEW *iew_stage) 144 { iew_ptr = iew_stage; } 145 146 /** Sets pointer to commit stage. Used only for initialization. */ 147 void setCommitStage(Commit *commit_stage) 148 { commit_ptr = commit_stage; } 149 150 private: 151 /** Pointer to IEW stage. Used only for initialization. */ 152 IEW *iew_ptr; 153 154 /** Pointer to commit stage. Used only for initialization. */ 155 Commit *commit_ptr; 156 157 public: 158 /** Initializes variables for the stage. */ 159 void startupStage(); 160 161 /** Sets pointer to list of active threads. */ 162 void setActiveThreads(std::list<ThreadID> *at_ptr); 163 164 /** Sets pointer to rename maps (per-thread structures). */ 165 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 166 167 /** Sets pointer to the free list. */ 168 void setFreeList(FreeList *fl_ptr); 169 170 /** Sets pointer to the scoreboard. */ 171 void setScoreboard(Scoreboard *_scoreboard); 172 173 /** Perform sanity checks after a drain. */ 174 void drainSanityCheck() const; 175 176 /** Has the stage drained? */ 177 bool isDrained() const; 178 179 /** Takes over from another CPU's thread. */ 180 void takeOverFrom(); 181 182 /** Squashes all instructions in a thread. */ 183 void squash(const InstSeqNum &squash_seq_num, ThreadID tid); 184 185 /** Ticks rename, which processes all input signals and attempts to rename 186 * as many instructions as possible. 187 */ 188 void tick(); 189 190 /** Debugging function used to dump history buffer of renamings. */ 191 void dumpHistory(); 192 193 private: 194 /** Reset this pipeline stage */ 195 void resetStage(); 196 197 /** Determines what to do based on rename's current status. 198 * @param status_change rename() sets this variable if there was a status 199 * change (ie switching from blocking to unblocking). 200 * @param tid Thread id to rename instructions from. 201 */ 202 void rename(bool &status_change, ThreadID tid); 203 204 /** Renames instructions for the given thread. Also handles serializing 205 * instructions. 206 */ 207 void renameInsts(ThreadID tid); 208 209 /** Inserts unused instructions from a given thread into the skid buffer, 210 * to be renamed once rename unblocks. 211 */ 212 void skidInsert(ThreadID tid); 213 214 /** Separates instructions from decode into individual lists of instructions 215 * sorted by thread. 216 */ 217 void sortInsts(); 218 219 /** Returns if all of the skid buffers are empty. */ 220 bool skidsEmpty(); 221 222 /** Updates overall rename status based on all of the threads' statuses. */ 223 void updateStatus(); 224 225 /** Switches rename to blocking, and signals back that rename has become 226 * blocked. 227 * @return Returns true if there is a status change. 228 */ 229 bool block(ThreadID tid); 230 231 /** Switches rename to unblocking if the skid buffer is empty, and signals 232 * back that rename has unblocked. 233 * @return Returns true if there is a status change. 234 */ 235 bool unblock(ThreadID tid); 236 237 /** Executes actual squash, removing squashed instructions. */ 238 void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid); 239 240 /** Removes a committed instruction's rename history. */ 241 void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid); 242 243 /** Renames the source registers of an instruction. */ 244 inline void renameSrcRegs(DynInstPtr &inst, ThreadID tid); 245 246 /** Renames the destination registers of an instruction. */ 247 inline void renameDestRegs(DynInstPtr &inst, ThreadID tid); 248 249 /** Calculates the number of free ROB entries for a specific thread. */ 250 inline int calcFreeROBEntries(ThreadID tid); 251 252 /** Calculates the number of free IQ entries for a specific thread. */ 253 inline int calcFreeIQEntries(ThreadID tid); 254 255 /** Calculates the number of free LQ entries for a specific thread. */ 256 inline int calcFreeLQEntries(ThreadID tid); 257 258 /** Calculates the number of free SQ entries for a specific thread. */ 259 inline int calcFreeSQEntries(ThreadID tid); 260 261 /** Returns the number of valid instructions coming from decode. */ 262 unsigned validInsts(); 263 264 /** Reads signals telling rename to block/unblock. */ 265 void readStallSignals(ThreadID tid); 266 267 /** Checks if any stages are telling rename to block. */ 268 bool checkStall(ThreadID tid); 269 270 /** Gets the number of free entries for a specific thread. */ 271 void readFreeEntries(ThreadID tid); 272 273 /** Checks the signals and updates the status. */ 274 bool checkSignalsAndUpdate(ThreadID tid); 275 276 /** Either serializes on the next instruction available in the InstQueue, 277 * or records that it must serialize on the next instruction to enter 278 * rename. 279 * @param inst_list The list of younger, unprocessed instructions for the 280 * thread that has the serializeAfter instruction. 281 * @param tid The thread id. 282 */ 283 void serializeAfter(InstQueue &inst_list, ThreadID tid); 284 285 /** Holds the information for each destination register rename. It holds 286 * the instruction's sequence number, the arch register, the old physical 287 * register for that arch. register, and the new physical register. 288 */ 289 struct RenameHistory { 290 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 291 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 292 : instSeqNum(_instSeqNum), archReg(_archReg), 293 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg) 294 { 295 } 296 297 /** The sequence number of the instruction that renamed. */ 298 InstSeqNum instSeqNum; 299 /** The architectural register index that was renamed. */ 300 RegIndex archReg; 301 /** The new physical register that the arch. register is renamed to. */ 302 PhysRegIndex newPhysReg; 303 /** The old physical register that the arch. register was renamed to. */ 304 PhysRegIndex prevPhysReg; 305 }; 306 307 /** A per-thread list of all destination register renames, used to either 308 * undo rename mappings or free old physical registers. 309 */ 310 std::list<RenameHistory> historyBuffer[Impl::MaxThreads]; 311 312 /** Pointer to CPU. */ 313 O3CPU *cpu; 314 315 /** Pointer to main time buffer used for backwards communication. */ 316 TimeBuffer<TimeStruct> *timeBuffer; 317 318 /** Wire to get IEW's output from backwards time buffer. */ 319 typename TimeBuffer<TimeStruct>::wire fromIEW; 320 321 /** Wire to get commit's output from backwards time buffer. */ 322 typename TimeBuffer<TimeStruct>::wire fromCommit; 323 324 /** Wire to write infromation heading to previous stages. */ 325 typename TimeBuffer<TimeStruct>::wire toDecode; 326 327 /** Rename instruction queue. */ 328 TimeBuffer<RenameStruct> *renameQueue; 329 330 /** Wire to write any information heading to IEW. */ 331 typename TimeBuffer<RenameStruct>::wire toIEW; 332 333 /** Decode instruction queue interface. */ 334 TimeBuffer<DecodeStruct> *decodeQueue; 335 336 /** Wire to get decode's output from decode queue. */ 337 typename TimeBuffer<DecodeStruct>::wire fromDecode; 338 339 /** Queue of all instructions coming from decode this cycle. */ 340 InstQueue insts[Impl::MaxThreads]; 341 342 /** Skid buffer between rename and decode. */ 343 InstQueue skidBuffer[Impl::MaxThreads]; 344 345 /** Rename map interface. */ 346 RenameMap *renameMap[Impl::MaxThreads]; 347 348 /** Free list interface. */ 349 FreeList *freeList; 350 351 /** Pointer to the list of active threads. */ 352 std::list<ThreadID> *activeThreads; 353 354 /** Pointer to the scoreboard. */ 355 Scoreboard *scoreboard; 356 357 /** Count of instructions in progress that have been sent off to the IQ 358 * and ROB, but are not yet included in their occupancy counts. 359 */ 360 int instsInProgress[Impl::MaxThreads]; 361 362 /** Count of Load instructions in progress that have been sent off to the IQ 363 * and ROB, but are not yet included in their occupancy counts. 364 */ 365 int loadsInProgress[Impl::MaxThreads]; 366 367 /** Count of Store instructions in progress that have been sent off to the IQ 368 * and ROB, but are not yet included in their occupancy counts. 369 */ 370 int storesInProgress[Impl::MaxThreads]; 371 372 /** Variable that tracks if decode has written to the time buffer this 373 * cycle. Used to tell CPU if there is activity this cycle. 374 */ 375 bool wroteToTimeBuffer; 376 377 /** Structures whose free entries impact the amount of instructions that 378 * can be renamed. 379 */ 380 struct FreeEntries { 381 unsigned iqEntries; 382 unsigned robEntries; 383 unsigned lqEntries; 384 unsigned sqEntries; 385 }; 386 387 /** Per-thread tracking of the number of free entries of back-end 388 * structures. 389 */ 390 FreeEntries freeEntries[Impl::MaxThreads]; 391 392 /** Records if the ROB is empty. In SMT mode the ROB may be dynamically 393 * partitioned between threads, so the ROB must tell rename when it is 394 * empty. 395 */ 396 bool emptyROB[Impl::MaxThreads]; 397 398 /** Source of possible stalls. */ 399 struct Stalls { 400 bool iew; 401 bool commit; 402 }; 403 404 /** Tracks which stages are telling decode to stall. */ 405 Stalls stalls[Impl::MaxThreads]; 406 407 /** The serialize instruction that rename has stalled on. */ 408 DynInstPtr serializeInst[Impl::MaxThreads]; 409 410 /** Records if rename needs to serialize on the next instruction for any 411 * thread. 412 */ 413 bool serializeOnNextInst[Impl::MaxThreads]; 414 415 /** Delay between iew and rename, in ticks. */ 416 int iewToRenameDelay; 417 418 /** Delay between decode and rename, in ticks. */ 419 int decodeToRenameDelay; 420 421 /** Delay between commit and rename, in ticks. */ 422 unsigned commitToRenameDelay; 423 424 /** Rename width, in instructions. */ 425 unsigned renameWidth; 426 427 /** Commit width, in instructions. Used so rename knows how many 428 * instructions might have freed registers in the previous cycle. 429 */ 430 unsigned commitWidth; 431 432 /** The index of the instruction in the time buffer to IEW that rename is 433 * currently using. 434 */ 435 unsigned toIEWIndex; 436 437 /** Whether or not rename needs to block this cycle. */ 438 bool blockThisCycle; 439 440 /** Whether or not rename needs to resume a serialize instruction 441 * after squashing. */ 442 bool resumeSerialize; 443 444 /** Whether or not rename needs to resume clearing out the skidbuffer 445 * after squashing. */ 446 bool resumeUnblocking; 447 448 /** The number of threads active in rename. */ 449 ThreadID numThreads; 450 451 /** The maximum skid buffer size. */ 452 unsigned skidBufferMax; 453 454 PhysRegIndex maxPhysicalRegs; 455 456 /** Enum to record the source of a structure full stall. Can come from 457 * either ROB, IQ, LSQ, and it is priortized in that order. 458 */ 459 enum FullSource { 460 ROB, 461 IQ, 462 LQ, 463 SQ, 464 NONE 465 }; 466 467 /** Function used to increment the stat that corresponds to the source of 468 * the stall. 469 */ 470 inline void incrFullStat(const FullSource &source); 471 472 /** Stat for total number of cycles spent squashing. */ 473 Stats::Scalar renameSquashCycles; 474 /** Stat for total number of cycles spent idle. */ 475 Stats::Scalar renameIdleCycles; 476 /** Stat for total number of cycles spent blocking. */ 477 Stats::Scalar renameBlockCycles; 478 /** Stat for total number of cycles spent stalling for a serializing inst. */ 479 Stats::Scalar renameSerializeStallCycles; 480 /** Stat for total number of cycles spent running normally. */ 481 Stats::Scalar renameRunCycles; 482 /** Stat for total number of cycles spent unblocking. */ 483 Stats::Scalar renameUnblockCycles; 484 /** Stat for total number of renamed instructions. */ 485 Stats::Scalar renameRenamedInsts; 486 /** Stat for total number of squashed instructions that rename discards. */ 487 Stats::Scalar renameSquashedInsts; 488 /** Stat for total number of times that the ROB starts a stall in rename. */ 489 Stats::Scalar renameROBFullEvents; 490 /** Stat for total number of times that the IQ starts a stall in rename. */ 491 Stats::Scalar renameIQFullEvents; 492 /** Stat for total number of times that the LQ starts a stall in rename. */ 493 Stats::Scalar renameLQFullEvents; 494 /** Stat for total number of times that the SQ starts a stall in rename. */ 495 Stats::Scalar renameSQFullEvents; 496 /** Stat for total number of times that rename runs out of free registers 497 * to use to rename. */ 498 Stats::Scalar renameFullRegistersEvents; 499 /** Stat for total number of renamed destination registers. */ 500 Stats::Scalar renameRenamedOperands; 501 /** Stat for total number of source register rename lookups. */ 502 Stats::Scalar renameRenameLookups; 503 Stats::Scalar intRenameLookups; 504 Stats::Scalar fpRenameLookups; 505 /** Stat for total number of committed renaming mappings. */ 506 Stats::Scalar renameCommittedMaps; 507 /** Stat for total number of mappings that were undone due to a squash. */ 508 Stats::Scalar renameUndoneMaps; 509 /** Number of serialize instructions handled. */ 510 Stats::Scalar renamedSerializing; 511 /** Number of instructions marked as temporarily serializing. */ 512 Stats::Scalar renamedTempSerializing; 513 /** Number of instructions inserted into skid buffers. */ 514 Stats::Scalar renameSkidInsts; 515}; 516 517#endif // __CPU_O3_RENAME_HH__ 518