rename.hh revision 1461
1// Todo: 2// Fix up trap and barrier handling. 3// May want to have different statuses to differentiate the different stall 4// conditions. 5 6#ifndef __CPU_BETA_CPU_SIMPLE_RENAME_HH__ 7#define __CPU_BETA_CPU_SIMPLE_RENAME_HH__ 8 9#include <list> 10 11#include "base/statistics.hh" 12#include "base/timebuf.hh" 13 14// Will need rename maps for both the int reg file and fp reg file. 15// Or change rename map class to handle both. (RegFile handles both.) 16template<class Impl> 17class SimpleRename 18{ 19 public: 20 // Typedefs from the Impl. 21 typedef typename Impl::ISA ISA; 22 typedef typename Impl::CPUPol CPUPol; 23 typedef typename Impl::DynInstPtr DynInstPtr; 24 typedef typename Impl::FullCPU FullCPU; 25 typedef typename Impl::Params Params; 26 27 typedef typename CPUPol::FetchStruct FetchStruct; 28 typedef typename CPUPol::DecodeStruct DecodeStruct; 29 typedef typename CPUPol::RenameStruct RenameStruct; 30 typedef typename CPUPol::TimeStruct TimeStruct; 31 32 // Typedefs from the CPUPol 33 typedef typename CPUPol::FreeList FreeList; 34 typedef typename CPUPol::RenameMap RenameMap; 35 36 // Typedefs from the ISA. 37 typedef typename ISA::Addr Addr; 38 39 public: 40 // Rename will block if ROB becomes full or issue queue becomes full, 41 // or there are no free registers to rename to. 42 // Only case where rename squashes is if IEW squashes. 43 enum Status { 44 Running, 45 Idle, 46 Squashing, 47 Blocked, 48 Unblocking, 49 BarrierStall 50 }; 51 52 private: 53 Status _status; 54 55 public: 56 SimpleRename(Params ¶ms); 57 58 void regStats(); 59 60 void setCPU(FullCPU *cpu_ptr); 61 62 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 63 64 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 65 66 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 67 68 void setRenameMap(RenameMap *rm_ptr); 69 70 void setFreeList(FreeList *fl_ptr); 71 72 void dumpHistory(); 73 74 void tick(); 75 76 void rename(); 77 78 void squash(); 79 80 private: 81 void block(); 82 83 inline void unblock(); 84 85 void doSquash(); 86 87 void removeFromHistory(InstSeqNum inst_seq_num); 88 89 inline void renameSrcRegs(DynInstPtr &inst); 90 91 inline void renameDestRegs(DynInstPtr &inst); 92 93 inline int calcFreeROBEntries(); 94 95 inline int calcFreeIQEntries(); 96 97 /** Holds the previous information for each rename. 98 * Note that often times the inst may have been deleted, so only access 99 * the pointer for the address and do not dereference it. 100 */ 101 struct RenameHistory { 102 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 103 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 104 : instSeqNum(_instSeqNum), archReg(_archReg), 105 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg), 106 placeHolder(false) 107 { 108 } 109 110 /** Constructor used specifically for cases where a place holder 111 * rename history entry is being made. 112 */ 113 RenameHistory(InstSeqNum _instSeqNum) 114 : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0), 115 prevPhysReg(0), placeHolder(true) 116 { 117 } 118 119 InstSeqNum instSeqNum; 120 RegIndex archReg; 121 PhysRegIndex newPhysReg; 122 PhysRegIndex prevPhysReg; 123 bool placeHolder; 124 }; 125 126 std::list<RenameHistory> historyBuffer; 127 128 /** CPU interface. */ 129 FullCPU *cpu; 130 131 // Interfaces to objects outside of rename. 132 /** Time buffer interface. */ 133 TimeBuffer<TimeStruct> *timeBuffer; 134 135 /** Wire to get IEW's output from backwards time buffer. */ 136 typename TimeBuffer<TimeStruct>::wire fromIEW; 137 138 /** Wire to get commit's output from backwards time buffer. */ 139 typename TimeBuffer<TimeStruct>::wire fromCommit; 140 141 /** Wire to write infromation heading to previous stages. */ 142 // Might not be the best name as not only decode will read it. 143 typename TimeBuffer<TimeStruct>::wire toDecode; 144 145 /** Rename instruction queue. */ 146 TimeBuffer<RenameStruct> *renameQueue; 147 148 /** Wire to write any information heading to IEW. */ 149 typename TimeBuffer<RenameStruct>::wire toIEW; 150 151 /** Decode instruction queue interface. */ 152 TimeBuffer<DecodeStruct> *decodeQueue; 153 154 /** Wire to get decode's output from decode queue. */ 155 typename TimeBuffer<DecodeStruct>::wire fromDecode; 156 157 /** Skid buffer between rename and decode. */ 158 std::queue<DecodeStruct> skidBuffer; 159 160 /** Rename map interface. */ 161 SimpleRenameMap *renameMap; 162 163 /** Free list interface. */ 164 FreeList *freeList; 165 166 /** Delay between iew and rename, in ticks. */ 167 int iewToRenameDelay; 168 169 /** Delay between decode and rename, in ticks. */ 170 int decodeToRenameDelay; 171 172 /** Delay between commit and rename, in ticks. */ 173 unsigned commitToRenameDelay; 174 175 /** Rename width, in instructions. */ 176 unsigned renameWidth; 177 178 /** Commit width, in instructions. Used so rename knows how many 179 * instructions might have freed registers in the previous cycle. 180 */ 181 unsigned commitWidth; 182 183 /** The instruction that rename is currently on. It needs to have 184 * persistent state so that when a stall occurs in the middle of a 185 * group of instructions, it can restart at the proper instruction. 186 */ 187 unsigned numInst; 188 189 Stats::Scalar<> renameSquashCycles; 190 Stats::Scalar<> renameIdleCycles; 191 Stats::Scalar<> renameBlockCycles; 192 Stats::Scalar<> renameUnblockCycles; 193 Stats::Scalar<> renameRenamedInsts; 194 Stats::Scalar<> renameSquashedInsts; 195 Stats::Scalar<> renameROBFullEvents; 196 Stats::Scalar<> renameIQFullEvents; 197 Stats::Scalar<> renameFullRegistersEvents; 198 Stats::Scalar<> renameRenamedOperands; 199 Stats::Scalar<> renameRenameLookups; 200 Stats::Scalar<> renameHBPlaceHolders; 201 Stats::Scalar<> renameCommittedMaps; 202 Stats::Scalar<> renameUndoneMaps; 203 Stats::Scalar<> renameValidUndoneMaps; 204}; 205 206#endif // __CPU_BETA_CPU_SIMPLE_RENAME_HH__ 207