rename.hh revision 1061
17732SAli.Saidi@ARM.com// Todo: 27732SAli.Saidi@ARM.com// Fix up trap and barrier handling. 37732SAli.Saidi@ARM.com// May want to have different statuses to differentiate the different stall 47732SAli.Saidi@ARM.com// conditions. 57732SAli.Saidi@ARM.com 67732SAli.Saidi@ARM.com#ifndef __SIMPLE_RENAME_HH__ 77732SAli.Saidi@ARM.com#define __SIMPLE_RENAME_HH__ 87732SAli.Saidi@ARM.com 97732SAli.Saidi@ARM.com#include <list> 107732SAli.Saidi@ARM.com 117732SAli.Saidi@ARM.com#include "base/timebuf.hh" 127732SAli.Saidi@ARM.com 137732SAli.Saidi@ARM.com// Will need rename maps for both the int reg file and fp reg file. 147732SAli.Saidi@ARM.com// Or change rename map class to handle both. (RegFile handles both.) 157732SAli.Saidi@ARM.comtemplate<class Impl> 167732SAli.Saidi@ARM.comclass SimpleRename 177732SAli.Saidi@ARM.com{ 187732SAli.Saidi@ARM.com public: 197732SAli.Saidi@ARM.com // Typedefs from the Impl. 207732SAli.Saidi@ARM.com typedef typename Impl::ISA ISA; 217732SAli.Saidi@ARM.com typedef typename Impl::CPUPol CPUPol; 227732SAli.Saidi@ARM.com typedef typename Impl::DynInstPtr DynInstPtr; 237732SAli.Saidi@ARM.com typedef typename Impl::FullCPU FullCPU; 247732SAli.Saidi@ARM.com typedef typename Impl::Params Params; 257732SAli.Saidi@ARM.com 267732SAli.Saidi@ARM.com typedef typename CPUPol::FetchStruct FetchStruct; 277732SAli.Saidi@ARM.com typedef typename CPUPol::DecodeStruct DecodeStruct; 287732SAli.Saidi@ARM.com typedef typename CPUPol::RenameStruct RenameStruct; 297732SAli.Saidi@ARM.com typedef typename CPUPol::TimeStruct TimeStruct; 307732SAli.Saidi@ARM.com 317732SAli.Saidi@ARM.com // Typedefs from the CPUPol 327732SAli.Saidi@ARM.com typedef typename CPUPol::FreeList FreeList; 337732SAli.Saidi@ARM.com typedef typename CPUPol::RenameMap RenameMap; 347732SAli.Saidi@ARM.com 357732SAli.Saidi@ARM.com // Typedefs from the ISA. 367732SAli.Saidi@ARM.com typedef typename ISA::Addr Addr; 377732SAli.Saidi@ARM.com 387732SAli.Saidi@ARM.com public: 397732SAli.Saidi@ARM.com // Rename will block if ROB becomes full or issue queue becomes full, 407732SAli.Saidi@ARM.com // or there are no free registers to rename to. 419554Sandreas.hansson@arm.com // Only case where rename squashes is if IEW squashes. 429554Sandreas.hansson@arm.com enum Status { 439554Sandreas.hansson@arm.com Running, 448204SAli.Saidi@ARM.com Idle, 458204SAli.Saidi@ARM.com Squashing, 468204SAli.Saidi@ARM.com Blocked, 478204SAli.Saidi@ARM.com Unblocking, 488204SAli.Saidi@ARM.com BarrierStall 498204SAli.Saidi@ARM.com }; 508204SAli.Saidi@ARM.com 518204SAli.Saidi@ARM.com private: 528204SAli.Saidi@ARM.com Status _status; 538204SAli.Saidi@ARM.com 548204SAli.Saidi@ARM.com public: 558204SAli.Saidi@ARM.com SimpleRename(Params ¶ms); 568204SAli.Saidi@ARM.com 577732SAli.Saidi@ARM.com void setCPU(FullCPU *cpu_ptr); 587732SAli.Saidi@ARM.com 597732SAli.Saidi@ARM.com void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 607732SAli.Saidi@ARM.com 617732SAli.Saidi@ARM.com void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 627732SAli.Saidi@ARM.com 637732SAli.Saidi@ARM.com void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 647732SAli.Saidi@ARM.com 657732SAli.Saidi@ARM.com void setRenameMap(RenameMap *rm_ptr); 667732SAli.Saidi@ARM.com 677732SAli.Saidi@ARM.com void setFreeList(FreeList *fl_ptr); 687732SAli.Saidi@ARM.com 697732SAli.Saidi@ARM.com void dumpHistory(); 708204SAli.Saidi@ARM.com 717732SAli.Saidi@ARM.com void tick(); 727732SAli.Saidi@ARM.com 737732SAli.Saidi@ARM.com void rename(); 747732SAli.Saidi@ARM.com 757732SAli.Saidi@ARM.com void squash(); 767732SAli.Saidi@ARM.com 777732SAli.Saidi@ARM.com private: 788142SAli.Saidi@ARM.com void block(); 797732SAli.Saidi@ARM.com 807732SAli.Saidi@ARM.com inline void unblock(); 818204SAli.Saidi@ARM.com 827732SAli.Saidi@ARM.com void doSquash(); 837732SAli.Saidi@ARM.com 847732SAli.Saidi@ARM.com void removeFromHistory(InstSeqNum inst_seq_num); 857732SAli.Saidi@ARM.com 867732SAli.Saidi@ARM.com inline void renameSrcRegs(DynInstPtr &inst); 877732SAli.Saidi@ARM.com 887732SAli.Saidi@ARM.com inline void renameDestRegs(DynInstPtr &inst); 897732SAli.Saidi@ARM.com 908142SAli.Saidi@ARM.com inline int calcFreeROBEntries(); 917732SAli.Saidi@ARM.com 927732SAli.Saidi@ARM.com inline int calcFreeIQEntries(); 938204SAli.Saidi@ARM.com 947732SAli.Saidi@ARM.com /** Holds the previous information for each rename. 957732SAli.Saidi@ARM.com * Note that often times the inst may have been deleted, so only access 967732SAli.Saidi@ARM.com * the pointer for the address and do not dereference it. 977732SAli.Saidi@ARM.com */ 987732SAli.Saidi@ARM.com struct RenameHistory { 997732SAli.Saidi@ARM.com RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 1007732SAli.Saidi@ARM.com PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 1017732SAli.Saidi@ARM.com : instSeqNum(_instSeqNum), archReg(_archReg), 1028142SAli.Saidi@ARM.com newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg), 1037732SAli.Saidi@ARM.com placeHolder(false) 1047732SAli.Saidi@ARM.com { 1058204SAli.Saidi@ARM.com } 1068204SAli.Saidi@ARM.com 1078204SAli.Saidi@ARM.com /** Constructor used specifically for cases where a place holder 1087732SAli.Saidi@ARM.com * rename history entry is being made. 1097732SAli.Saidi@ARM.com */ 1107732SAli.Saidi@ARM.com RenameHistory(InstSeqNum _instSeqNum) 1117732SAli.Saidi@ARM.com : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0), 1127732SAli.Saidi@ARM.com prevPhysReg(0), placeHolder(true) 1137732SAli.Saidi@ARM.com { 1147732SAli.Saidi@ARM.com } 1157732SAli.Saidi@ARM.com 1167732SAli.Saidi@ARM.com InstSeqNum instSeqNum; 1177732SAli.Saidi@ARM.com RegIndex archReg; 1188204SAli.Saidi@ARM.com PhysRegIndex newPhysReg; 1198204SAli.Saidi@ARM.com PhysRegIndex prevPhysReg; 1208204SAli.Saidi@ARM.com bool placeHolder; 1218204SAli.Saidi@ARM.com }; 1228204SAli.Saidi@ARM.com 1238204SAli.Saidi@ARM.com std::list<RenameHistory> historyBuffer; 1247732SAli.Saidi@ARM.com 1258204SAli.Saidi@ARM.com /** CPU interface. */ 1267732SAli.Saidi@ARM.com FullCPU *cpu; 1277732SAli.Saidi@ARM.com 1287732SAli.Saidi@ARM.com // Interfaces to objects outside of rename. 1297732SAli.Saidi@ARM.com /** Time buffer interface. */ 1307732SAli.Saidi@ARM.com TimeBuffer<TimeStruct> *timeBuffer; 1317732SAli.Saidi@ARM.com 1328204SAli.Saidi@ARM.com /** Wire to get IEW's output from backwards time buffer. */ 1338204SAli.Saidi@ARM.com typename TimeBuffer<TimeStruct>::wire fromIEW; 1348204SAli.Saidi@ARM.com 1358204SAli.Saidi@ARM.com /** Wire to get commit's output from backwards time buffer. */ 1367732SAli.Saidi@ARM.com typename TimeBuffer<TimeStruct>::wire fromCommit; 1378204SAli.Saidi@ARM.com 1388204SAli.Saidi@ARM.com /** Wire to write infromation heading to previous stages. */ 1398204SAli.Saidi@ARM.com // Might not be the best name as not only decode will read it. 1407732SAli.Saidi@ARM.com typename TimeBuffer<TimeStruct>::wire toDecode; 1417732SAli.Saidi@ARM.com 1427732SAli.Saidi@ARM.com /** Rename instruction queue. */ 1437732SAli.Saidi@ARM.com TimeBuffer<RenameStruct> *renameQueue; 1447732SAli.Saidi@ARM.com 1457732SAli.Saidi@ARM.com /** Wire to write any information heading to IEW. */ 1467732SAli.Saidi@ARM.com typename TimeBuffer<RenameStruct>::wire toIEW; 1477732SAli.Saidi@ARM.com 1487732SAli.Saidi@ARM.com /** Decode instruction queue interface. */ 1497732SAli.Saidi@ARM.com TimeBuffer<DecodeStruct> *decodeQueue; 1507732SAli.Saidi@ARM.com 1517732SAli.Saidi@ARM.com /** Wire to get decode's output from decode queue. */ 1527732SAli.Saidi@ARM.com typename TimeBuffer<DecodeStruct>::wire fromDecode; 1537732SAli.Saidi@ARM.com 1547732SAli.Saidi@ARM.com /** Skid buffer between rename and decode. */ 1557732SAli.Saidi@ARM.com std::queue<DecodeStruct> skidBuffer; 1567732SAli.Saidi@ARM.com 1577732SAli.Saidi@ARM.com /** Rename map interface. */ 1587732SAli.Saidi@ARM.com SimpleRenameMap *renameMap; 1597732SAli.Saidi@ARM.com 1607732SAli.Saidi@ARM.com /** Free list interface. */ 1617732SAli.Saidi@ARM.com FreeList *freeList; 1627732SAli.Saidi@ARM.com 1637732SAli.Saidi@ARM.com /** Delay between iew and rename, in ticks. */ 1647732SAli.Saidi@ARM.com int iewToRenameDelay; 1657732SAli.Saidi@ARM.com 1667732SAli.Saidi@ARM.com /** Delay between decode and rename, in ticks. */ 1677732SAli.Saidi@ARM.com int decodeToRenameDelay; 1687732SAli.Saidi@ARM.com 1697732SAli.Saidi@ARM.com /** Delay between commit and rename, in ticks. */ 1707732SAli.Saidi@ARM.com unsigned commitToRenameDelay; 1718204SAli.Saidi@ARM.com 1728204SAli.Saidi@ARM.com /** Rename width, in instructions. */ 1738204SAli.Saidi@ARM.com unsigned renameWidth; 1747732SAli.Saidi@ARM.com 1758204SAli.Saidi@ARM.com /** Commit width, in instructions. Used so rename knows how many 1768204SAli.Saidi@ARM.com * instructions might have freed registers in the previous cycle. 1778204SAli.Saidi@ARM.com */ 1787732SAli.Saidi@ARM.com unsigned commitWidth; 1797732SAli.Saidi@ARM.com 1807732SAli.Saidi@ARM.com /** The instruction that rename is currently on. It needs to have 1817732SAli.Saidi@ARM.com * persistent state so that when a stall occurs in the middle of a 1827732SAli.Saidi@ARM.com * group of instructions, it can restart at the proper instruction. 1837732SAli.Saidi@ARM.com */ 1847732SAli.Saidi@ARM.com unsigned numInst; 1857732SAli.Saidi@ARM.com}; 1867732SAli.Saidi@ARM.com 1877732SAli.Saidi@ARM.com#endif // __SIMPLE_RENAME_HH__ 1887732SAli.Saidi@ARM.com