rename.hh revision 1060
16892SBrad.Beckmann@amd.com// Todo: 26892SBrad.Beckmann@amd.com// Figure out rename map for reg vs fp (probably just have one rename map). 36892SBrad.Beckmann@amd.com// In simple case, there is no renaming, so have this stage do basically 46892SBrad.Beckmann@amd.com// nothing. 56892SBrad.Beckmann@amd.com// Fix up trap and barrier handling. Fix up squashing too, as it's too 66892SBrad.Beckmann@amd.com// dependent upon the iew stage continually telling it to squash. 76892SBrad.Beckmann@amd.com// Have commit send back information whenever a branch has committed. This 86892SBrad.Beckmann@amd.com// way the history buffer can be cleared beyond the point where the branch 96892SBrad.Beckmann@amd.com// was. 106892SBrad.Beckmann@amd.com 116892SBrad.Beckmann@amd.com#ifndef __SIMPLE_RENAME_HH__ 126892SBrad.Beckmann@amd.com#define __SIMPLE_RENAME_HH__ 136892SBrad.Beckmann@amd.com 146892SBrad.Beckmann@amd.com//Will want to include: time buffer, structs, free list, rename map 156892SBrad.Beckmann@amd.com#include <list> 166892SBrad.Beckmann@amd.com 176892SBrad.Beckmann@amd.com#include "base/timebuf.hh" 186892SBrad.Beckmann@amd.com#include "cpu/beta_cpu/comm.hh" 196892SBrad.Beckmann@amd.com#include "cpu/beta_cpu/rename_map.hh" 206892SBrad.Beckmann@amd.com#include "cpu/beta_cpu/free_list.hh" 216892SBrad.Beckmann@amd.com 226892SBrad.Beckmann@amd.comusing namespace std; 236892SBrad.Beckmann@amd.com 246892SBrad.Beckmann@amd.com// Will need rename maps for both the int reg file and fp reg file. 256892SBrad.Beckmann@amd.com// Or change rename map class to handle both. (RegFile handles both.) 266892SBrad.Beckmann@amd.comtemplate<class Impl> 276892SBrad.Beckmann@amd.comclass SimpleRename 286892SBrad.Beckmann@amd.com{ 296892SBrad.Beckmann@amd.com public: 307563SBrad.Beckmann@amd.com // Typedefs from the Impl. 316892SBrad.Beckmann@amd.com typedef typename Impl::ISA ISA; 326892SBrad.Beckmann@amd.com typedef typename Impl::CPUPol CPUPol; 336892SBrad.Beckmann@amd.com typedef typename Impl::DynInst DynInst; 346892SBrad.Beckmann@amd.com typedef typename Impl::FullCPU FullCPU; 357538SBrad.Beckmann@amd.com typedef typename Impl::Params Params; 367538SBrad.Beckmann@amd.com 377538SBrad.Beckmann@amd.com typedef typename Impl::FetchStruct FetchStruct; 387538SBrad.Beckmann@amd.com typedef typename Impl::DecodeStruct DecodeStruct; 397538SBrad.Beckmann@amd.com typedef typename Impl::RenameStruct RenameStruct; 407538SBrad.Beckmann@amd.com typedef typename Impl::TimeStruct TimeStruct; 417661Snate@binkert.org 427538SBrad.Beckmann@amd.com // Typedefs from the CPUPol 438612Stushar@csail.mit.edu typedef typename CPUPol::FreeList FreeList; 448612Stushar@csail.mit.edu typedef typename CPUPol::RenameMap RenameMap; 457538SBrad.Beckmann@amd.com 467538SBrad.Beckmann@amd.com // Typedefs from the ISA. 477917SBrad.Beckmann@amd.com typedef typename ISA::Addr Addr; 487563SBrad.Beckmann@amd.com 497563SBrad.Beckmann@amd.com public: 507538SBrad.Beckmann@amd.com // Rename will block if ROB becomes full or issue queue becomes full, 517538SBrad.Beckmann@amd.com // or there are no free registers to rename to. 527538SBrad.Beckmann@amd.com // Only case where rename squashes is if IEW squashes. 537538SBrad.Beckmann@amd.com enum Status { 547538SBrad.Beckmann@amd.com Running, 557566SBrad.Beckmann@amd.com Idle, 567566SBrad.Beckmann@amd.com Squashing, 577809Snilay@cs.wisc.edu Blocked, 587809Snilay@cs.wisc.edu Unblocking, 597809Snilay@cs.wisc.edu BarrierStall 607809Snilay@cs.wisc.edu }; 618638Sgloh 628638Sgloh private: 637538SBrad.Beckmann@amd.com Status _status; 647538SBrad.Beckmann@amd.com 657538SBrad.Beckmann@amd.com public: 667538SBrad.Beckmann@amd.com SimpleRename(Params ¶ms); 677541SBrad.Beckmann@amd.com 686892SBrad.Beckmann@amd.com void setCPU(FullCPU *cpu_ptr); 698638Sgloh 708690Snilay@cs.wisc.edu void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 718690Snilay@cs.wisc.edu 728436SBrad.Beckmann@amd.com void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 738436SBrad.Beckmann@amd.com 747032SBrad.Beckmann@amd.com void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 757032SBrad.Beckmann@amd.com 766923SBrad.Beckmann@amd.com void setRenameMap(RenameMap *rm_ptr); 776893SBrad.Beckmann@amd.com 788436SBrad.Beckmann@amd.com void setFreeList(FreeList *fl_ptr); 798436SBrad.Beckmann@amd.com 807557SBrad.Beckmann@amd.com void dumpHistory(); 816923SBrad.Beckmann@amd.com 826923SBrad.Beckmann@amd.com void tick(); 837557SBrad.Beckmann@amd.com 848257SBrad.Beckmann@amd.com void rename(); 858257SBrad.Beckmann@amd.com 868257SBrad.Beckmann@amd.com void squash(); 878257SBrad.Beckmann@amd.com 888257SBrad.Beckmann@amd.com private: 898257SBrad.Beckmann@amd.com void block(); 908257SBrad.Beckmann@amd.com 918257SBrad.Beckmann@amd.com inline void unblock(); 928257SBrad.Beckmann@amd.com 938257SBrad.Beckmann@amd.com void doSquash(); 948257SBrad.Beckmann@amd.com 958257SBrad.Beckmann@amd.com void removeFromHistory(InstSeqNum inst_seq_num); 968257SBrad.Beckmann@amd.com 978257SBrad.Beckmann@amd.com /** Holds the previous information for each rename. 988257SBrad.Beckmann@amd.com * Note that often times the inst may have been deleted, so only access 998257SBrad.Beckmann@amd.com * the pointer for the address and do not dereference it. 1008258SBrad.Beckmann@amd.com */ 1018258SBrad.Beckmann@amd.com struct RenameHistory { 1028257SBrad.Beckmann@amd.com RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 1038257SBrad.Beckmann@amd.com PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 1046892SBrad.Beckmann@amd.com : instSeqNum(_instSeqNum), archReg(_archReg), 1057032SBrad.Beckmann@amd.com newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg), 1067032SBrad.Beckmann@amd.com placeHolder(false) 1076892SBrad.Beckmann@amd.com { 1087032SBrad.Beckmann@amd.com } 1097032SBrad.Beckmann@amd.com 1108257SBrad.Beckmann@amd.com /** Constructor used specifically for cases where a place holder 1118257SBrad.Beckmann@amd.com * rename history entry is being made. 1128257SBrad.Beckmann@amd.com */ 1137557SBrad.Beckmann@amd.com RenameHistory(InstSeqNum _instSeqNum) 1147032SBrad.Beckmann@amd.com : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0), 1157032SBrad.Beckmann@amd.com prevPhysReg(0), placeHolder(true) 1167557SBrad.Beckmann@amd.com { 1178257SBrad.Beckmann@amd.com } 1188612Stushar@csail.mit.edu 1198612Stushar@csail.mit.edu InstSeqNum instSeqNum; 1208612Stushar@csail.mit.edu RegIndex archReg; 1218612Stushar@csail.mit.edu PhysRegIndex newPhysReg; 1228612Stushar@csail.mit.edu PhysRegIndex prevPhysReg; 1238612Stushar@csail.mit.edu bool placeHolder; 1248612Stushar@csail.mit.edu }; 1256892SBrad.Beckmann@amd.com 1266903SBrad.Beckmann@amd.com list<RenameHistory> historyBuffer; 1277563SBrad.Beckmann@amd.com 1287025SBrad.Beckmann@amd.com /** CPU interface. */ 1297025SBrad.Beckmann@amd.com FullCPU *cpu; 1307025SBrad.Beckmann@amd.com 1317025SBrad.Beckmann@amd.com // Interfaces to objects outside of rename. 1327563SBrad.Beckmann@amd.com /** Time buffer interface. */ 1336903SBrad.Beckmann@amd.com TimeBuffer<TimeStruct> *timeBuffer; 1346903SBrad.Beckmann@amd.com 1357563SBrad.Beckmann@amd.com /** Wire to get IEW's output from backwards time buffer. */ 1367563SBrad.Beckmann@amd.com typename TimeBuffer<TimeStruct>::wire fromIEW; 1377563SBrad.Beckmann@amd.com 1387563SBrad.Beckmann@amd.com /** Wire to get commit's output from backwards time buffer. */ 1397563SBrad.Beckmann@amd.com typename TimeBuffer<TimeStruct>::wire fromCommit; 1407563SBrad.Beckmann@amd.com 1417563SBrad.Beckmann@amd.com /** Wire to write infromation heading to previous stages. */ 1427663SBrad.Beckmann@amd.com // Might not be the best name as not only decode will read it. 1437663SBrad.Beckmann@amd.com typename TimeBuffer<TimeStruct>::wire toDecode; 1447663SBrad.Beckmann@amd.com 1457663SBrad.Beckmann@amd.com /** Rename instruction queue. */ 1467663SBrad.Beckmann@amd.com TimeBuffer<RenameStruct> *renameQueue; 1477563SBrad.Beckmann@amd.com 1486903SBrad.Beckmann@amd.com /** Wire to write any information heading to IEW. */ 1496903SBrad.Beckmann@amd.com typename TimeBuffer<RenameStruct>::wire toIEW; 1507563SBrad.Beckmann@amd.com 1517563SBrad.Beckmann@amd.com /** Decode instruction queue interface. */ 1527541SBrad.Beckmann@amd.com TimeBuffer<DecodeStruct> *decodeQueue; 1537541SBrad.Beckmann@amd.com 1546905SBrad.Beckmann@amd.com /** Wire to get decode's output from decode queue. */ 1556892SBrad.Beckmann@amd.com typename TimeBuffer<DecodeStruct>::wire fromDecode; 1568436SBrad.Beckmann@amd.com 1578436SBrad.Beckmann@amd.com /** Skid buffer between rename and decode. */ 1588436SBrad.Beckmann@amd.com queue<DecodeStruct> skidBuffer; 1598436SBrad.Beckmann@amd.com 1608436SBrad.Beckmann@amd.com /** Rename map interface. */ 1618322Ssteve.reinhardt@amd.com SimpleRenameMap *renameMap; 1627809Snilay@cs.wisc.edu 163 /** Free list interface. */ 164 FreeList *freeList; 165 166 /** Delay between iew and rename, in ticks. */ 167 int iewToRenameDelay; 168 169 /** Delay between decode and rename, in ticks. */ 170 int decodeToRenameDelay; 171 172 /** Delay between commit and rename, in ticks. */ 173 unsigned commitToRenameDelay; 174 175 /** Rename width, in instructions. */ 176 unsigned renameWidth; 177 178 /** Commit width, in instructions. Used so rename knows how many 179 * instructions might have freed registers in the previous cycle. 180 */ 181 unsigned commitWidth; 182}; 183 184#endif // __SIMPLE_RENAME_HH__ 185