regfile.hh revision 8793:5f25086326ac 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Gabe Black
30 */
31
32#ifndef __CPU_O3_REGFILE_HH__
33#define __CPU_O3_REGFILE_HH__
34
35#include <vector>
36
37#include "arch/isa_traits.hh"
38#include "arch/kernel_stats.hh"
39#include "arch/types.hh"
40#include "base/trace.hh"
41#include "config/full_system.hh"
42#include "config/the_isa.hh"
43#include "cpu/o3/comm.hh"
44#include "debug/IEW.hh"
45
46/**
47 * Simple physical register file class.
48 * Right now this is specific to Alpha until we decide if/how to make things
49 * generic enough to support other ISAs.
50 */
51template <class Impl>
52class PhysRegFile
53{
54  protected:
55    typedef TheISA::IntReg IntReg;
56    typedef TheISA::FloatReg FloatReg;
57    typedef TheISA::FloatRegBits FloatRegBits;
58
59    typedef union {
60        FloatReg d;
61        FloatRegBits q;
62    } PhysFloatReg;
63
64    // Note that most of the definitions of the IntReg, FloatReg, etc. exist
65    // within the Impl/ISA class and not within this PhysRegFile class.
66
67    // Will make these registers public for now, but they probably should
68    // be private eventually with some accessor functions.
69  public:
70    typedef typename Impl::O3CPU O3CPU;
71
72    /**
73     * Constructs a physical register file with the specified amount of
74     * integer and floating point registers.
75     */
76    PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
77                unsigned _numPhysicalFloatRegs);
78
79    //Everything below should be pretty well identical to the normal
80    //register file that exists within AlphaISA class.
81    //The duplication is unfortunate but it's better than having
82    //different ways to access certain registers.
83
84    /** Reads an integer register. */
85    uint64_t readIntReg(PhysRegIndex reg_idx)
86    {
87        assert(reg_idx < numPhysicalIntRegs);
88
89        DPRINTF(IEW, "RegFile: Access to int register %i, has data "
90                "%#x\n", int(reg_idx), intRegFile[reg_idx]);
91        return intRegFile[reg_idx];
92    }
93
94    /** Reads a floating point register (double precision). */
95    FloatReg readFloatReg(PhysRegIndex reg_idx)
96    {
97        // Remove the base Float reg dependency.
98        reg_idx = reg_idx - numPhysicalIntRegs;
99
100        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
101
102        FloatReg floatReg = floatRegFile[reg_idx].d;
103
104        DPRINTF(IEW, "RegFile: Access to float register %i, has "
105                "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
106
107        return floatReg;
108    }
109
110    FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
111    {
112        // Remove the base Float reg dependency.
113        reg_idx = reg_idx - numPhysicalIntRegs;
114
115        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
116
117        FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
118
119        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
120                "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
121
122        return floatRegBits;
123    }
124
125    /** Sets an integer register to the given value. */
126    void setIntReg(PhysRegIndex reg_idx, uint64_t val)
127    {
128        assert(reg_idx < numPhysicalIntRegs);
129
130        DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
131                int(reg_idx), val);
132
133        if (reg_idx != TheISA::ZeroReg)
134            intRegFile[reg_idx] = val;
135    }
136
137    /** Sets a double precision floating point register to the given value. */
138    void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
139    {
140        // Remove the base Float reg dependency.
141        reg_idx = reg_idx - numPhysicalIntRegs;
142
143        assert(reg_idx < numPhysicalFloatRegs);
144
145        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
146                int(reg_idx), (uint64_t)val);
147
148#if THE_ISA == ALPHA_ISA
149        if (reg_idx != TheISA::ZeroReg)
150#endif
151            floatRegFile[reg_idx].d = val;
152    }
153
154    void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
155    {
156        // Remove the base Float reg dependency.
157        reg_idx = reg_idx - numPhysicalIntRegs;
158
159        assert(reg_idx < numPhysicalFloatRegs);
160
161        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
162                int(reg_idx), (uint64_t)val);
163
164        floatRegFile[reg_idx].q = val;
165    }
166
167  public:
168    /** (signed) integer register file. */
169    IntReg *intRegFile;
170
171    /** Floating point register file. */
172    PhysFloatReg *floatRegFile;
173
174  private:
175    int intrflag;                       // interrupt flag
176
177  private:
178    /** CPU pointer. */
179    O3CPU *cpu;
180
181  public:
182    /** Number of physical integer registers. */
183    unsigned numPhysicalIntRegs;
184    /** Number of physical floating point registers. */
185    unsigned numPhysicalFloatRegs;
186};
187
188template <class Impl>
189PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
190                               unsigned _numPhysicalFloatRegs)
191    : cpu(_cpu), numPhysicalIntRegs(_numPhysicalIntRegs),
192      numPhysicalFloatRegs(_numPhysicalFloatRegs)
193{
194    intRegFile = new IntReg[numPhysicalIntRegs];
195    floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
196
197    memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
198    memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
199}
200
201#endif
202