regfile.hh revision 8232:b28d06a175be 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Gabe Black
30 */
31
32#ifndef __CPU_O3_REGFILE_HH__
33#define __CPU_O3_REGFILE_HH__
34
35#include <vector>
36
37#include "arch/isa_traits.hh"
38#include "arch/types.hh"
39#include "base/trace.hh"
40#include "config/full_system.hh"
41#include "config/the_isa.hh"
42#include "cpu/o3/comm.hh"
43#include "debug/IEW.hh"
44
45#if FULL_SYSTEM
46#include "arch/kernel_stats.hh"
47#endif
48
49/**
50 * Simple physical register file class.
51 * Right now this is specific to Alpha until we decide if/how to make things
52 * generic enough to support other ISAs.
53 */
54template <class Impl>
55class PhysRegFile
56{
57  protected:
58    typedef TheISA::IntReg IntReg;
59    typedef TheISA::FloatReg FloatReg;
60    typedef TheISA::FloatRegBits FloatRegBits;
61
62    typedef union {
63        FloatReg d;
64        FloatRegBits q;
65    } PhysFloatReg;
66
67    // Note that most of the definitions of the IntReg, FloatReg, etc. exist
68    // within the Impl/ISA class and not within this PhysRegFile class.
69
70    // Will make these registers public for now, but they probably should
71    // be private eventually with some accessor functions.
72  public:
73    typedef typename Impl::O3CPU O3CPU;
74
75    /**
76     * Constructs a physical register file with the specified amount of
77     * integer and floating point registers.
78     */
79    PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
80                unsigned _numPhysicalFloatRegs);
81
82    //Everything below should be pretty well identical to the normal
83    //register file that exists within AlphaISA class.
84    //The duplication is unfortunate but it's better than having
85    //different ways to access certain registers.
86
87    /** Reads an integer register. */
88    uint64_t readIntReg(PhysRegIndex reg_idx)
89    {
90        assert(reg_idx < numPhysicalIntRegs);
91
92        DPRINTF(IEW, "RegFile: Access to int register %i, has data "
93                "%#x\n", int(reg_idx), intRegFile[reg_idx]);
94        return intRegFile[reg_idx];
95    }
96
97    /** Reads a floating point register (double precision). */
98    FloatReg readFloatReg(PhysRegIndex reg_idx)
99    {
100        // Remove the base Float reg dependency.
101        reg_idx = reg_idx - numPhysicalIntRegs;
102
103        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
104
105        FloatReg floatReg = floatRegFile[reg_idx].d;
106
107        DPRINTF(IEW, "RegFile: Access to float register %i, has "
108                "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
109
110        return floatReg;
111    }
112
113    FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
114    {
115        // Remove the base Float reg dependency.
116        reg_idx = reg_idx - numPhysicalIntRegs;
117
118        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
119
120        FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
121
122        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
123                "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
124
125        return floatRegBits;
126    }
127
128    /** Sets an integer register to the given value. */
129    void setIntReg(PhysRegIndex reg_idx, uint64_t val)
130    {
131        assert(reg_idx < numPhysicalIntRegs);
132
133        DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
134                int(reg_idx), val);
135
136        if (reg_idx != TheISA::ZeroReg)
137            intRegFile[reg_idx] = val;
138    }
139
140    /** Sets a double precision floating point register to the given value. */
141    void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
142    {
143        // Remove the base Float reg dependency.
144        reg_idx = reg_idx - numPhysicalIntRegs;
145
146        assert(reg_idx < numPhysicalFloatRegs);
147
148        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
149                int(reg_idx), (uint64_t)val);
150
151#if THE_ISA == ALPHA_ISA
152        if (reg_idx != TheISA::ZeroReg)
153#endif
154            floatRegFile[reg_idx].d = val;
155    }
156
157    void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
158    {
159        // Remove the base Float reg dependency.
160        reg_idx = reg_idx - numPhysicalIntRegs;
161
162        assert(reg_idx < numPhysicalFloatRegs);
163
164        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
165                int(reg_idx), (uint64_t)val);
166
167        floatRegFile[reg_idx].q = val;
168    }
169
170  public:
171    /** (signed) integer register file. */
172    IntReg *intRegFile;
173
174    /** Floating point register file. */
175    PhysFloatReg *floatRegFile;
176
177#if FULL_SYSTEM
178  private:
179    int intrflag;                       // interrupt flag
180#endif
181
182  private:
183    /** CPU pointer. */
184    O3CPU *cpu;
185
186  public:
187    /** Number of physical integer registers. */
188    unsigned numPhysicalIntRegs;
189    /** Number of physical floating point registers. */
190    unsigned numPhysicalFloatRegs;
191};
192
193template <class Impl>
194PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
195                               unsigned _numPhysicalFloatRegs)
196    : cpu(_cpu), numPhysicalIntRegs(_numPhysicalIntRegs),
197      numPhysicalFloatRegs(_numPhysicalFloatRegs)
198{
199    intRegFile = new IntReg[numPhysicalIntRegs];
200    floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
201
202    memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
203    memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
204}
205
206#endif
207