regfile.hh revision 6313:95f69a436c82 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Gabe Black
30 */
31
32#ifndef __CPU_O3_REGFILE_HH__
33#define __CPU_O3_REGFILE_HH__
34
35#include "arch/isa_traits.hh"
36#include "arch/regfile.hh"
37#include "arch/types.hh"
38#include "base/trace.hh"
39#include "config/full_system.hh"
40#include "cpu/o3/comm.hh"
41
42#if FULL_SYSTEM
43#include "arch/kernel_stats.hh"
44#endif
45
46#include <vector>
47
48/**
49 * Simple physical register file class.
50 * Right now this is specific to Alpha until we decide if/how to make things
51 * generic enough to support other ISAs.
52 */
53template <class Impl>
54class PhysRegFile
55{
56  protected:
57    typedef TheISA::IntReg IntReg;
58    typedef TheISA::FloatReg FloatReg;
59    typedef TheISA::FloatRegBits FloatRegBits;
60
61    typedef union {
62        FloatReg d;
63        FloatRegBits q;
64    } PhysFloatReg;
65
66    // Note that most of the definitions of the IntReg, FloatReg, etc. exist
67    // within the Impl/ISA class and not within this PhysRegFile class.
68
69    // Will make these registers public for now, but they probably should
70    // be private eventually with some accessor functions.
71  public:
72    typedef typename Impl::O3CPU O3CPU;
73
74    /**
75     * Constructs a physical register file with the specified amount of
76     * integer and floating point registers.
77     */
78    PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
79                unsigned _numPhysicalFloatRegs);
80
81    //Everything below should be pretty well identical to the normal
82    //register file that exists within AlphaISA class.
83    //The duplication is unfortunate but it's better than having
84    //different ways to access certain registers.
85
86    /** Reads an integer register. */
87    uint64_t readIntReg(PhysRegIndex reg_idx)
88    {
89        assert(reg_idx < numPhysicalIntRegs);
90
91        DPRINTF(IEW, "RegFile: Access to int register %i, has data "
92                "%#x\n", int(reg_idx), intRegFile[reg_idx]);
93        return intRegFile[reg_idx];
94    }
95
96    FloatReg readFloatReg(PhysRegIndex reg_idx, int width)
97    {
98        // Remove the base Float reg dependency.
99        reg_idx = reg_idx - numPhysicalIntRegs;
100
101        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
102
103        FloatReg floatReg = floatRegFile[reg_idx].d;
104
105        DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
106                "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
107
108        return floatReg;
109    }
110
111    /** Reads a floating point register (double precision). */
112    FloatReg readFloatReg(PhysRegIndex reg_idx)
113    {
114        // Remove the base Float reg dependency.
115        reg_idx = reg_idx - numPhysicalIntRegs;
116
117        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
118
119        FloatReg floatReg = floatRegFile[reg_idx].d;
120
121        DPRINTF(IEW, "RegFile: Access to float register %i, has "
122                "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
123
124        return floatReg;
125    }
126
127    /** Reads a floating point register as an integer. */
128    FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
129    {
130        // Remove the base Float reg dependency.
131        reg_idx = reg_idx - numPhysicalIntRegs;
132
133        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
134
135        FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
136
137        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
138                "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
139
140        return floatRegBits;
141    }
142
143    FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
144    {
145        // Remove the base Float reg dependency.
146        reg_idx = reg_idx - numPhysicalIntRegs;
147
148        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
149
150        FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
151
152        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
153                "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
154
155        return floatRegBits;
156    }
157
158    /** Sets an integer register to the given value. */
159    void setIntReg(PhysRegIndex reg_idx, uint64_t val)
160    {
161        assert(reg_idx < numPhysicalIntRegs);
162
163        DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
164                int(reg_idx), val);
165
166        if (reg_idx != TheISA::ZeroReg)
167            intRegFile[reg_idx] = val;
168    }
169
170    /** Sets a single precision floating point register to the given value. */
171    void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
172    {
173        // Remove the base Float reg dependency.
174        reg_idx = reg_idx - numPhysicalIntRegs;
175
176        assert(reg_idx < numPhysicalFloatRegs);
177
178        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
179                int(reg_idx), (uint64_t)val);
180
181#if THE_ISA == ALPHA_ISA
182        if (reg_idx != TheISA::ZeroReg)
183#endif
184            floatRegFile[reg_idx].d = val;
185    }
186
187    /** Sets a double precision floating point register to the given value. */
188    void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
189    {
190        // Remove the base Float reg dependency.
191        reg_idx = reg_idx - numPhysicalIntRegs;
192
193        assert(reg_idx < numPhysicalFloatRegs);
194
195        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
196                int(reg_idx), (uint64_t)val);
197
198#if THE_ISA == ALPHA_ISA
199        if (reg_idx != TheISA::ZeroReg)
200#endif
201            floatRegFile[reg_idx].d = val;
202    }
203
204    /** Sets a floating point register to the given integer value. */
205    void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
206    {
207        // Remove the base Float reg dependency.
208        reg_idx = reg_idx - numPhysicalIntRegs;
209
210        assert(reg_idx < numPhysicalFloatRegs);
211
212        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
213                int(reg_idx), (uint64_t)val);
214
215        floatRegFile[reg_idx].q = val;
216    }
217
218    void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
219    {
220        // Remove the base Float reg dependency.
221        reg_idx = reg_idx - numPhysicalIntRegs;
222
223        assert(reg_idx < numPhysicalFloatRegs);
224
225        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
226                int(reg_idx), (uint64_t)val);
227
228        floatRegFile[reg_idx].q = val;
229    }
230
231  public:
232    /** (signed) integer register file. */
233    IntReg *intRegFile;
234
235    /** Floating point register file. */
236    PhysFloatReg *floatRegFile;
237
238#if FULL_SYSTEM
239  private:
240    int intrflag;                       // interrupt flag
241#endif
242
243  private:
244    /** CPU pointer. */
245    O3CPU *cpu;
246
247  public:
248    /** Number of physical integer registers. */
249    unsigned numPhysicalIntRegs;
250    /** Number of physical floating point registers. */
251    unsigned numPhysicalFloatRegs;
252};
253
254template <class Impl>
255PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
256                               unsigned _numPhysicalFloatRegs)
257    : cpu(_cpu), numPhysicalIntRegs(_numPhysicalIntRegs),
258      numPhysicalFloatRegs(_numPhysicalFloatRegs)
259{
260    intRegFile = new IntReg[numPhysicalIntRegs];
261    floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
262
263    memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
264    memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
265}
266
267#endif
268