regfile.hh revision 6221:58a3c04e6344
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Gabe Black 30 */ 31 32#ifndef __CPU_O3_REGFILE_HH__ 33#define __CPU_O3_REGFILE_HH__ 34 35#include "arch/isa_traits.hh" 36#include "arch/regfile.hh" 37#include "arch/types.hh" 38#include "base/trace.hh" 39#include "config/full_system.hh" 40#include "cpu/o3/comm.hh" 41 42#if FULL_SYSTEM 43#include "arch/kernel_stats.hh" 44#endif 45 46#include <vector> 47 48/** 49 * Simple physical register file class. 50 * Right now this is specific to Alpha until we decide if/how to make things 51 * generic enough to support other ISAs. 52 */ 53template <class Impl> 54class PhysRegFile 55{ 56 protected: 57 typedef TheISA::IntReg IntReg; 58 typedef TheISA::FloatReg FloatReg; 59 typedef TheISA::FloatRegBits FloatRegBits; 60 typedef TheISA::MiscRegFile MiscRegFile; 61 typedef TheISA::MiscReg MiscReg; 62 63 typedef union { 64 FloatReg d; 65 FloatRegBits q; 66 } PhysFloatReg; 67 68 // Note that most of the definitions of the IntReg, FloatReg, etc. exist 69 // within the Impl/ISA class and not within this PhysRegFile class. 70 71 // Will make these registers public for now, but they probably should 72 // be private eventually with some accessor functions. 73 public: 74 typedef typename Impl::O3CPU O3CPU; 75 76 /** 77 * Constructs a physical register file with the specified amount of 78 * integer and floating point registers. 79 */ 80 PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs, 81 unsigned _numPhysicalFloatRegs); 82 83 //Everything below should be pretty well identical to the normal 84 //register file that exists within AlphaISA class. 85 //The duplication is unfortunate but it's better than having 86 //different ways to access certain registers. 87 88 /** Reads an integer register. */ 89 uint64_t readIntReg(PhysRegIndex reg_idx) 90 { 91 assert(reg_idx < numPhysicalIntRegs); 92 93 DPRINTF(IEW, "RegFile: Access to int register %i, has data " 94 "%#x\n", int(reg_idx), intRegFile[reg_idx]); 95 return intRegFile[reg_idx]; 96 } 97 98 FloatReg readFloatReg(PhysRegIndex reg_idx, int width) 99 { 100 // Remove the base Float reg dependency. 101 reg_idx = reg_idx - numPhysicalIntRegs; 102 103 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 104 105 FloatReg floatReg = floatRegFile[reg_idx].d; 106 107 DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " 108 "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); 109 110 return floatReg; 111 } 112 113 /** Reads a floating point register (double precision). */ 114 FloatReg readFloatReg(PhysRegIndex reg_idx) 115 { 116 // Remove the base Float reg dependency. 117 reg_idx = reg_idx - numPhysicalIntRegs; 118 119 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 120 121 FloatReg floatReg = floatRegFile[reg_idx].d; 122 123 DPRINTF(IEW, "RegFile: Access to float register %i, has " 124 "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); 125 126 return floatReg; 127 } 128 129 /** Reads a floating point register as an integer. */ 130 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) 131 { 132 // Remove the base Float reg dependency. 133 reg_idx = reg_idx - numPhysicalIntRegs; 134 135 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 136 137 FloatRegBits floatRegBits = floatRegFile[reg_idx].q; 138 139 DPRINTF(IEW, "RegFile: Access to float register %i as int, " 140 "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 141 142 return floatRegBits; 143 } 144 145 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) 146 { 147 // Remove the base Float reg dependency. 148 reg_idx = reg_idx - numPhysicalIntRegs; 149 150 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 151 152 FloatRegBits floatRegBits = floatRegFile[reg_idx].q; 153 154 DPRINTF(IEW, "RegFile: Access to float register %i as int, " 155 "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 156 157 return floatRegBits; 158 } 159 160 /** Sets an integer register to the given value. */ 161 void setIntReg(PhysRegIndex reg_idx, uint64_t val) 162 { 163 assert(reg_idx < numPhysicalIntRegs); 164 165 DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 166 int(reg_idx), val); 167 168 if (reg_idx != TheISA::ZeroReg) 169 intRegFile[reg_idx] = val; 170 } 171 172 /** Sets a single precision floating point register to the given value. */ 173 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) 174 { 175 // Remove the base Float reg dependency. 176 reg_idx = reg_idx - numPhysicalIntRegs; 177 178 assert(reg_idx < numPhysicalFloatRegs); 179 180 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 181 int(reg_idx), (uint64_t)val); 182 183#if THE_ISA == ALPHA_ISA 184 if (reg_idx != TheISA::ZeroReg) 185#endif 186 floatRegFile[reg_idx].d = val; 187 } 188 189 /** Sets a double precision floating point register to the given value. */ 190 void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 191 { 192 // Remove the base Float reg dependency. 193 reg_idx = reg_idx - numPhysicalIntRegs; 194 195 assert(reg_idx < numPhysicalFloatRegs); 196 197 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 198 int(reg_idx), (uint64_t)val); 199 200#if THE_ISA == ALPHA_ISA 201 if (reg_idx != TheISA::ZeroReg) 202#endif 203 floatRegFile[reg_idx].d = val; 204 } 205 206 /** Sets a floating point register to the given integer value. */ 207 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) 208 { 209 // Remove the base Float reg dependency. 210 reg_idx = reg_idx - numPhysicalIntRegs; 211 212 assert(reg_idx < numPhysicalFloatRegs); 213 214 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 215 int(reg_idx), (uint64_t)val); 216 217 floatRegFile[reg_idx].q = val; 218 } 219 220 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 221 { 222 // Remove the base Float reg dependency. 223 reg_idx = reg_idx - numPhysicalIntRegs; 224 225 assert(reg_idx < numPhysicalFloatRegs); 226 227 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 228 int(reg_idx), (uint64_t)val); 229 230 floatRegFile[reg_idx].q = val; 231 } 232 233 MiscReg 234 readMiscRegNoEffect(int misc_reg, ThreadID tid) 235 { 236 return miscRegs[tid].readRegNoEffect(misc_reg); 237 } 238 239 MiscReg 240 readMiscReg(int misc_reg, ThreadID tid) 241 { 242 return miscRegs[tid].readReg(misc_reg, cpu->tcBase(tid)); 243 } 244 245 void 246 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) 247 { 248 miscRegs[tid].setRegNoEffect(misc_reg, val); 249 } 250 251 void 252 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid) 253 { 254 miscRegs[tid].setReg(misc_reg, val, cpu->tcBase(tid)); 255 } 256 257 public: 258 /** (signed) integer register file. */ 259 IntReg *intRegFile; 260 261 /** Floating point register file. */ 262 PhysFloatReg *floatRegFile; 263 264 /** Miscellaneous register file. */ 265 MiscRegFile miscRegs[Impl::MaxThreads]; 266 267#if FULL_SYSTEM 268 private: 269 int intrflag; // interrupt flag 270#endif 271 272 private: 273 /** CPU pointer. */ 274 O3CPU *cpu; 275 276 public: 277 /** Number of physical integer registers. */ 278 unsigned numPhysicalIntRegs; 279 /** Number of physical floating point registers. */ 280 unsigned numPhysicalFloatRegs; 281}; 282 283template <class Impl> 284PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs, 285 unsigned _numPhysicalFloatRegs) 286 : cpu(_cpu), numPhysicalIntRegs(_numPhysicalIntRegs), 287 numPhysicalFloatRegs(_numPhysicalFloatRegs) 288{ 289 intRegFile = new IntReg[numPhysicalIntRegs]; 290 floatRegFile = new PhysFloatReg[numPhysicalFloatRegs]; 291 292 for (int i = 0; i < Impl::MaxThreads; ++i) { 293 miscRegs[i].clear(); 294 } 295 296 memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs); 297 memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs); 298} 299 300#endif 301