regfile.hh revision 2632:1bb2f91485ea
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_O3_CPU_REGFILE_HH__ 30#define __CPU_O3_CPU_REGFILE_HH__ 31 32// @todo: Destructor 33 34#include "arch/isa_traits.hh" 35#include "arch/faults.hh" 36#include "base/trace.hh" 37#include "config/full_system.hh" 38#include "cpu/o3/comm.hh" 39 40#if FULL_SYSTEM 41#include "kern/kernel_stats.hh" 42 43#endif 44 45// This really only depends on the ISA, and not the Impl. It might be nicer 46// to see if I can make it depend on nothing... 47// Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA, 48// and should go in the AlphaFullCPU. 49 50template <class Impl> 51class PhysRegFile 52{ 53 protected: 54 typedef TheISA::IntReg IntReg; 55 typedef TheISA::FloatReg FloatReg; 56 typedef TheISA::MiscRegFile MiscRegFile; 57 typedef TheISA::MiscReg MiscReg; 58 59 //Note that most of the definitions of the IntReg, FloatReg, etc. exist 60 //within the Impl/ISA class and not within this PhysRegFile class. 61 62 //Will need some way to allow stuff like swap_palshadow to access the 63 //correct registers. Might require code changes to swap_palshadow and 64 //other execution contexts. 65 66 //Will make these registers public for now, but they probably should 67 //be private eventually with some accessor functions. 68 public: 69 typedef typename Impl::FullCPU FullCPU; 70 71 PhysRegFile(unsigned _numPhysicalIntRegs, 72 unsigned _numPhysicalFloatRegs); 73 74 //Everything below should be pretty well identical to the normal 75 //register file that exists within AlphaISA class. 76 //The duplication is unfortunate but it's better than having 77 //different ways to access certain registers. 78 79 //Add these in later when everything else is in place 80// void serialize(std::ostream &os); 81// void unserialize(Checkpoint *cp, const std::string §ion); 82 83 uint64_t readIntReg(PhysRegIndex reg_idx) 84 { 85 assert(reg_idx < numPhysicalIntRegs); 86 87 DPRINTF(IEW, "RegFile: Access to int register %i, has data " 88 "%i\n", int(reg_idx), intRegFile[reg_idx]); 89 return intRegFile[reg_idx]; 90 } 91 92 FloatReg readFloatReg(PhysRegIndex reg_idx, int width) 93 { 94 // Remove the base Float reg dependency. 95 reg_idx = reg_idx - numPhysicalIntRegs; 96 97 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 98 99 FloatReg floatReg = floatRegFile.readReg(reg_idx, width); 100 101 DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " 102 "data %8.8d\n", int(reg_idx), (double)floatReg); 103 104 return floatReg; 105 } 106 107 FloatReg readFloatReg(PhysRegIndex reg_idx) 108 { 109 // Remove the base Float reg dependency. 110 reg_idx = reg_idx - numPhysicalIntRegs; 111 112 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 113 114 FloatReg floatReg = floatRegFile.readReg(reg_idx); 115 116 DPRINTF(IEW, "RegFile: Access to float register %i, has " 117 "data %8.8d\n", int(reg_idx), (double)floatReg); 118 119 return floatReg; 120 } 121 122 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) 123 { 124 // Remove the base Float reg dependency. 125 reg_idx = reg_idx - numPhysicalIntRegs; 126 127 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 128 129 FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx, width); 130 131 DPRINTF(IEW, "RegFile: Access to %d byte float register %i as int, " 132 "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits); 133 134 return floatRegBits; 135 } 136 137 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) 138 { 139 // Remove the base Float reg dependency. 140 reg_idx = reg_idx - numPhysicalIntRegs; 141 142 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 143 144 FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx); 145 146 DPRINTF(IEW, "RegFile: Access to float register %i as int, " 147 "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits); 148 149 return floatRegBits; 150 } 151 152 void setIntReg(PhysRegIndex reg_idx, uint64_t val) 153 { 154 assert(reg_idx < numPhysicalIntRegs); 155 156 DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n", 157 int(reg_idx), val); 158 159 intRegFile[reg_idx] = val; 160 } 161 162 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) 163 { 164 // Remove the base Float reg dependency. 165 reg_idx = reg_idx - numPhysicalIntRegs; 166 167 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 168 169 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n", 170 int(reg_idx), (double)val); 171 172 floatRegFile.setReg(reg_idx, val, width); 173 } 174 175 void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 176 { 177 // Remove the base Float reg dependency. 178 reg_idx = reg_idx - numPhysicalIntRegs; 179 180 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 181 182 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n", 183 int(reg_idx), (double)val); 184 185 floatRegFile.setReg(reg_idx, val); 186 } 187 188 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) 189 { 190 // Remove the base Float reg dependency. 191 reg_idx = reg_idx - numPhysicalIntRegs; 192 193 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 194 195 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 196 int(reg_idx), (uint64_t)val); 197 198 floatRegFile.setRegBits(reg_idx, val, width); 199 } 200 201 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 202 { 203 // Remove the base Float reg dependency. 204 reg_idx = reg_idx - numPhysicalIntRegs; 205 206 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 207 208 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 209 int(reg_idx), (uint64_t)val); 210 211 floatRegFile.setRegBits(reg_idx, val); 212 } 213 214 uint64_t readPC() 215 { 216 return pc; 217 } 218 219 void setPC(uint64_t val) 220 { 221 pc = val; 222 } 223 224 void setNextPC(uint64_t val) 225 { 226 npc = val; 227 } 228 229 //Consider leaving this stuff and below in some implementation specific 230 //file as opposed to the general register file. Or have a derived class. 231 MiscReg readMiscReg(int misc_reg) 232 { 233 // Dummy function for now. 234 // @todo: Fix this once proxy XC is used. 235 return 0; 236 } 237 238 Fault setMiscReg(int misc_reg, const MiscReg &val) 239 { 240 // Dummy function for now. 241 // @todo: Fix this once proxy XC is used. 242 return NoFault; 243 } 244 245#if FULL_SYSTEM 246 int readIntrFlag() { return intrflag; } 247 void setIntrFlag(int val) { intrflag = val; } 248#endif 249 250 // These should be private eventually, but will be public for now 251 // so that I can hack around the initregs issue. 252 public: 253 /** (signed) integer register file. */ 254 IntReg *intRegFile; 255 256 /** Floating point register file. */ 257 FloatReg *floatRegFile; 258 259 /** Miscellaneous register file. */ 260 MiscRegFile miscRegs; 261 262 /** Program counter. */ 263 Addr pc; 264 265 /** Next-cycle program counter. */ 266 Addr npc; 267 268#if FULL_SYSTEM 269 private: 270 // This is ISA specifc stuff; remove it eventually once ISAImpl is used 271// IntReg palregs[NumIntRegs]; // PAL shadow registers 272 int intrflag; // interrupt flag 273 bool pal_shadow; // using pal_shadow registers 274#endif 275 276 private: 277 FullCPU *cpu; 278 279 public: 280 void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } 281 282 unsigned numPhysicalIntRegs; 283 unsigned numPhysicalFloatRegs; 284}; 285 286template <class Impl> 287PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, 288 unsigned _numPhysicalFloatRegs) 289 : numPhysicalIntRegs(_numPhysicalIntRegs), 290 numPhysicalFloatRegs(_numPhysicalFloatRegs) 291{ 292 intRegFile = new IntReg[numPhysicalIntRegs]; 293 floatRegFile = new FloatReg[numPhysicalFloatRegs]; 294 295 memset(intRegFile, 0, sizeof(*intRegFile)); 296 memset(floatRegFile, 0, sizeof(*floatRegFile)); 297} 298 299#endif // __CPU_O3_CPU_REGFILE_HH__ 300