regfile.hh revision 13622:ba31c2a23eca 
1/*
2 * Copyright (c) 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Gabe Black
43 */
44
45#ifndef __CPU_O3_REGFILE_HH__
46#define __CPU_O3_REGFILE_HH__
47
48#include <vector>
49
50#include "arch/isa_traits.hh"
51#include "arch/kernel_stats.hh"
52#include "arch/types.hh"
53#include "base/trace.hh"
54#include "config/the_isa.hh"
55#include "cpu/o3/comm.hh"
56#include "debug/IEW.hh"
57#include "enums/VecRegRenameMode.hh"
58
59class UnifiedFreeList;
60
61/**
62 * Simple physical register file class.
63 */
64class PhysRegFile
65{
66  private:
67
68    using VecElem = TheISA::VecElem;
69    using VecRegContainer = TheISA::VecRegContainer;
70    using PhysIds = std::vector<PhysRegId>;
71    using VecMode = Enums::VecRegRenameMode;
72    using VecPredRegContainer = TheISA::VecPredRegContainer;
73  public:
74    using IdRange = std::pair<PhysIds::const_iterator,
75                              PhysIds::const_iterator>;
76  private:
77    static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
78
79    /** Integer register file. */
80    std::vector<RegVal> intRegFile;
81    std::vector<PhysRegId> intRegIds;
82
83    /** Floating point register file. */
84    std::vector<RegVal> floatRegFile;
85    std::vector<PhysRegId> floatRegIds;
86
87    /** Vector register file. */
88    std::vector<VecRegContainer> vectorRegFile;
89    std::vector<PhysRegId> vecRegIds;
90    std::vector<PhysRegId> vecElemIds;
91
92    /** Predicate register file. */
93    std::vector<VecPredRegContainer> vecPredRegFile;
94    std::vector<PhysRegId> vecPredRegIds;
95
96    /** Condition-code register file. */
97    std::vector<RegVal> ccRegFile;
98    std::vector<PhysRegId> ccRegIds;
99
100    /** Misc Reg Ids */
101    std::vector<PhysRegId> miscRegIds;
102
103    /**
104     * Number of physical general purpose registers
105     */
106    unsigned numPhysicalIntRegs;
107
108    /**
109     * Number of physical floating point registers
110     */
111    unsigned numPhysicalFloatRegs;
112
113    /**
114     * Number of physical vector registers
115     */
116    unsigned numPhysicalVecRegs;
117
118    /**
119     * Number of physical vector element registers
120     */
121    unsigned numPhysicalVecElemRegs;
122
123    /**
124     * Number of physical predicate registers
125     */
126    unsigned numPhysicalVecPredRegs;
127
128    /**
129     * Number of physical CC registers
130     */
131    unsigned numPhysicalCCRegs;
132
133    /** Total number of physical registers. */
134    unsigned totalNumRegs;
135
136    /** Mode in which vector registers are addressed. */
137    VecMode vecMode;
138
139  public:
140    /**
141     * Constructs a physical register file with the specified amount of
142     * integer and floating point registers.
143     */
144    PhysRegFile(unsigned _numPhysicalIntRegs,
145                unsigned _numPhysicalFloatRegs,
146                unsigned _numPhysicalVecRegs,
147                unsigned _numPhysicalVecPredRegs,
148                unsigned _numPhysicalCCRegs,
149                VecMode vmode
150                );
151
152    /**
153     * Destructor to free resources
154     */
155    ~PhysRegFile() {}
156
157    /** Initialize the free list */
158    void initFreeList(UnifiedFreeList *freeList);
159
160    /** @return the number of integer physical registers. */
161    unsigned numIntPhysRegs() const { return numPhysicalIntRegs; }
162
163    /** @return the number of floating-point physical registers. */
164    unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; }
165    /** @return the number of vector physical registers. */
166    unsigned numVecPhysRegs() const { return numPhysicalVecRegs; }
167    /** @return the number of predicate physical registers. */
168    unsigned numPredPhysRegs() const { return numPhysicalVecPredRegs; }
169
170    /** @return the number of vector physical registers. */
171    unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; }
172
173    /** @return the number of condition-code physical registers. */
174    unsigned numCCPhysRegs() const { return numPhysicalCCRegs; }
175
176    /** @return the total number of physical registers. */
177    unsigned totalNumPhysRegs() const { return totalNumRegs; }
178
179    /** Gets a misc register PhysRegIdPtr. */
180    PhysRegIdPtr getMiscRegId(RegIndex reg_idx) {
181        return &miscRegIds[reg_idx];
182    }
183
184    /** Reads an integer register. */
185    RegVal
186    readIntReg(PhysRegIdPtr phys_reg) const
187    {
188        assert(phys_reg->isIntPhysReg());
189
190        DPRINTF(IEW, "RegFile: Access to int register %i, has data "
191                "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]);
192        return intRegFile[phys_reg->index()];
193    }
194
195    RegVal
196    readFloatReg(PhysRegIdPtr phys_reg) const
197    {
198        assert(phys_reg->isFloatPhysReg());
199
200        RegVal floatRegBits = floatRegFile[phys_reg->index()];
201
202        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
203                "has data %#x\n", phys_reg->index(), floatRegBits);
204
205        return floatRegBits;
206    }
207
208    /** Reads a vector register. */
209    const VecRegContainer &
210    readVecReg(PhysRegIdPtr phys_reg) const
211    {
212        assert(phys_reg->isVectorPhysReg());
213
214        DPRINTF(IEW, "RegFile: Access to vector register %i, has "
215                "data %s\n", int(phys_reg->index()),
216                vectorRegFile[phys_reg->index()].print());
217
218        return vectorRegFile[phys_reg->index()];
219    }
220
221    /** Reads a vector register for modification. */
222    VecRegContainer &
223    getWritableVecReg(PhysRegIdPtr phys_reg)
224    {
225        /* const_cast for not duplicating code above. */
226        return const_cast<VecRegContainer&>(readVecReg(phys_reg));
227    }
228
229    /** Reads a vector register lane. */
230    template <typename VecElem, int LaneIdx>
231    VecLaneT<VecElem, true>
232    readVecLane(PhysRegIdPtr phys_reg) const
233    {
234        return readVecReg(phys_reg).laneView<VecElem, LaneIdx>();
235    }
236
237    /** Reads a vector register lane. */
238    template <typename VecElem>
239    VecLaneT<VecElem, true>
240    readVecLane(PhysRegIdPtr phys_reg) const
241    {
242        return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex());
243    }
244
245    /** Get a vector register lane for modification. */
246    template <typename LD>
247    void
248    setVecLane(PhysRegIdPtr phys_reg, const LD& val)
249    {
250        assert(phys_reg->isVectorPhysReg());
251
252        DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n",
253                int(phys_reg->index()), phys_reg->elemIndex(), val);
254
255        vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>(
256                phys_reg->elemIndex()) = val;
257    }
258
259    /** Reads a vector element. */
260    const VecElem &
261    readVecElem(PhysRegIdPtr phys_reg) const
262    {
263        assert(phys_reg->isVectorPhysElem());
264        auto ret = vectorRegFile[phys_reg->index()].as<VecElem>();
265        const VecElem& val = ret[phys_reg->elemIndex()];
266        DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
267                " has data %#x\n", phys_reg->elemIndex(),
268                int(phys_reg->index()), val);
269
270        return val;
271    }
272
273    /** Reads a predicate register. */
274    const VecPredRegContainer& readVecPredReg(PhysRegIdPtr phys_reg) const
275    {
276        assert(phys_reg->isVecPredPhysReg());
277
278        DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
279                "data %s\n", int(phys_reg->index()),
280                vecPredRegFile[phys_reg->index()].print());
281
282        return vecPredRegFile[phys_reg->index()];
283    }
284
285    VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr phys_reg)
286    {
287        /* const_cast for not duplicating code above. */
288        return const_cast<VecPredRegContainer&>(readVecPredReg(phys_reg));
289    }
290
291    /** Reads a condition-code register. */
292    RegVal
293    readCCReg(PhysRegIdPtr phys_reg)
294    {
295        assert(phys_reg->isCCPhysReg());
296
297        DPRINTF(IEW, "RegFile: Access to cc register %i, has "
298                "data %#x\n", phys_reg->index(),
299                ccRegFile[phys_reg->index()]);
300
301        return ccRegFile[phys_reg->index()];
302    }
303
304    /** Sets an integer register to the given value. */
305    void
306    setIntReg(PhysRegIdPtr phys_reg, RegVal val)
307    {
308        assert(phys_reg->isIntPhysReg());
309
310        DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
311                phys_reg->index(), val);
312
313        if (!phys_reg->isZeroReg())
314            intRegFile[phys_reg->index()] = val;
315    }
316
317    void
318    setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
319    {
320        assert(phys_reg->isFloatPhysReg());
321
322        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
323                phys_reg->index(), (uint64_t)val);
324
325        if (!phys_reg->isZeroReg())
326            floatRegFile[phys_reg->index()] = val;
327    }
328
329    /** Sets a vector register to the given value. */
330    void
331    setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
332    {
333        assert(phys_reg->isVectorPhysReg());
334
335        DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
336                int(phys_reg->index()), val.print());
337
338        vectorRegFile[phys_reg->index()] = val;
339    }
340
341    /** Sets a vector register to the given value. */
342    void
343    setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
344    {
345        assert(phys_reg->isVectorPhysElem());
346
347        DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
348                " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val);
349
350        vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] =
351                val;
352    }
353
354    /** Sets a predicate register to the given value. */
355    void setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val)
356    {
357        assert(phys_reg->isVecPredPhysReg());
358
359        DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
360                int(phys_reg->index()), val.print());
361
362        vecPredRegFile[phys_reg->index()] = val;
363    }
364
365    /** Sets a condition-code register to the given value. */
366    void
367    setCCReg(PhysRegIdPtr phys_reg, RegVal val)
368    {
369        assert(phys_reg->isCCPhysReg());
370
371        DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
372                phys_reg->index(), (uint64_t)val);
373
374        ccRegFile[phys_reg->index()] = val;
375    }
376
377    /** Get the PhysRegIds of the elems of a vector register.
378     * Auxiliary function to transition from Full vector mode to Elem mode.
379     */
380    IdRange getRegElemIds(PhysRegIdPtr reg);
381
382    /**
383     * Get the PhysRegIds of the elems of all vector registers.
384     * Auxiliary function to transition from Full vector mode to Elem mode
385     * and to initialise the rename map.
386     */
387    IdRange getRegIds(RegClass cls);
388
389    /**
390     * Get the true physical register id.
391     * As many parts work with PhysRegIdPtr, we need to be able to produce
392     * the pointer out of just class and register idx.
393     */
394    PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
395};
396
397
398#endif //__CPU_O3_REGFILE_HH__
399