regfile.hh revision 13622
1955SN/A/* 2955SN/A * Copyright (c) 2016-2017 ARM Limited 311408Sandreas.sandberg@arm.com * All rights reserved 49812Sandreas.hansson@arm.com * 59812Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 69812Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 79812Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 89812Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 99812Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 109812Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 119812Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 129812Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 139812Sandreas.hansson@arm.com * 149812Sandreas.hansson@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 157816Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 165871Snate@binkert.org * All rights reserved. 171762SN/A * 18955SN/A * Redistribution and use in source and binary forms, with or without 19955SN/A * modification, are permitted provided that the following conditions are 20955SN/A * met: redistributions of source code must retain the above copyright 21955SN/A * notice, this list of conditions and the following disclaimer; 22955SN/A * redistributions in binary form must reproduce the above copyright 23955SN/A * notice, this list of conditions and the following disclaimer in the 24955SN/A * documentation and/or other materials provided with the distribution; 25955SN/A * neither the name of the copyright holders nor the names of its 26955SN/A * contributors may be used to endorse or promote products derived from 27955SN/A * this software without specific prior written permission. 28955SN/A * 29955SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30955SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31955SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32955SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33955SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34955SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35955SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36955SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37955SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38955SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39955SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40955SN/A * 41955SN/A * Authors: Kevin Lim 422665Ssaidi@eecs.umich.edu * Gabe Black 432665Ssaidi@eecs.umich.edu */ 445863Snate@binkert.org 45955SN/A#ifndef __CPU_O3_REGFILE_HH__ 46955SN/A#define __CPU_O3_REGFILE_HH__ 47955SN/A 48955SN/A#include <vector> 49955SN/A 508878Ssteve.reinhardt@amd.com#include "arch/isa_traits.hh" 512632Sstever@eecs.umich.edu#include "arch/kernel_stats.hh" 528878Ssteve.reinhardt@amd.com#include "arch/types.hh" 532632Sstever@eecs.umich.edu#include "base/trace.hh" 54955SN/A#include "config/the_isa.hh" 558878Ssteve.reinhardt@amd.com#include "cpu/o3/comm.hh" 562632Sstever@eecs.umich.edu#include "debug/IEW.hh" 572761Sstever@eecs.umich.edu#include "enums/VecRegRenameMode.hh" 582632Sstever@eecs.umich.edu 592632Sstever@eecs.umich.educlass UnifiedFreeList; 602632Sstever@eecs.umich.edu 612761Sstever@eecs.umich.edu/** 622761Sstever@eecs.umich.edu * Simple physical register file class. 632761Sstever@eecs.umich.edu */ 648878Ssteve.reinhardt@amd.comclass PhysRegFile 658878Ssteve.reinhardt@amd.com{ 662761Sstever@eecs.umich.edu private: 672761Sstever@eecs.umich.edu 682761Sstever@eecs.umich.edu using VecElem = TheISA::VecElem; 692761Sstever@eecs.umich.edu using VecRegContainer = TheISA::VecRegContainer; 702761Sstever@eecs.umich.edu using PhysIds = std::vector<PhysRegId>; 718878Ssteve.reinhardt@amd.com using VecMode = Enums::VecRegRenameMode; 728878Ssteve.reinhardt@amd.com using VecPredRegContainer = TheISA::VecPredRegContainer; 732632Sstever@eecs.umich.edu public: 742632Sstever@eecs.umich.edu using IdRange = std::pair<PhysIds::const_iterator, 758878Ssteve.reinhardt@amd.com PhysIds::const_iterator>; 768878Ssteve.reinhardt@amd.com private: 772632Sstever@eecs.umich.edu static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; 78955SN/A 79955SN/A /** Integer register file. */ 80955SN/A std::vector<RegVal> intRegFile; 815863Snate@binkert.org std::vector<PhysRegId> intRegIds; 825863Snate@binkert.org 835863Snate@binkert.org /** Floating point register file. */ 845863Snate@binkert.org std::vector<RegVal> floatRegFile; 855863Snate@binkert.org std::vector<PhysRegId> floatRegIds; 865863Snate@binkert.org 875863Snate@binkert.org /** Vector register file. */ 885863Snate@binkert.org std::vector<VecRegContainer> vectorRegFile; 895863Snate@binkert.org std::vector<PhysRegId> vecRegIds; 905863Snate@binkert.org std::vector<PhysRegId> vecElemIds; 915863Snate@binkert.org 928878Ssteve.reinhardt@amd.com /** Predicate register file. */ 935863Snate@binkert.org std::vector<VecPredRegContainer> vecPredRegFile; 945863Snate@binkert.org std::vector<PhysRegId> vecPredRegIds; 955863Snate@binkert.org 969812Sandreas.hansson@arm.com /** Condition-code register file. */ 979812Sandreas.hansson@arm.com std::vector<RegVal> ccRegFile; 985863Snate@binkert.org std::vector<PhysRegId> ccRegIds; 999812Sandreas.hansson@arm.com 1005863Snate@binkert.org /** Misc Reg Ids */ 1015863Snate@binkert.org std::vector<PhysRegId> miscRegIds; 1025863Snate@binkert.org 1039812Sandreas.hansson@arm.com /** 1049812Sandreas.hansson@arm.com * Number of physical general purpose registers 1055863Snate@binkert.org */ 1065863Snate@binkert.org unsigned numPhysicalIntRegs; 1078878Ssteve.reinhardt@amd.com 1085863Snate@binkert.org /** 1095863Snate@binkert.org * Number of physical floating point registers 1105863Snate@binkert.org */ 1116654Snate@binkert.org unsigned numPhysicalFloatRegs; 11210196SCurtis.Dunham@arm.com 113955SN/A /** 1145396Ssaidi@eecs.umich.edu * Number of physical vector registers 11511401Sandreas.sandberg@arm.com */ 1165863Snate@binkert.org unsigned numPhysicalVecRegs; 1175863Snate@binkert.org 1184202Sbinkertn@umich.edu /** 1195863Snate@binkert.org * Number of physical vector element registers 1205863Snate@binkert.org */ 1215863Snate@binkert.org unsigned numPhysicalVecElemRegs; 1225863Snate@binkert.org 123955SN/A /** 1246654Snate@binkert.org * Number of physical predicate registers 1255273Sstever@gmail.com */ 1265871Snate@binkert.org unsigned numPhysicalVecPredRegs; 1275273Sstever@gmail.com 1286655Snate@binkert.org /** 1298878Ssteve.reinhardt@amd.com * Number of physical CC registers 1306655Snate@binkert.org */ 1316655Snate@binkert.org unsigned numPhysicalCCRegs; 1329219Spower.jg@gmail.com 1336655Snate@binkert.org /** Total number of physical registers. */ 1345871Snate@binkert.org unsigned totalNumRegs; 1356654Snate@binkert.org 1368947Sandreas.hansson@arm.com /** Mode in which vector registers are addressed. */ 1375396Ssaidi@eecs.umich.edu VecMode vecMode; 1388120Sgblack@eecs.umich.edu 1398120Sgblack@eecs.umich.edu public: 1408120Sgblack@eecs.umich.edu /** 1418120Sgblack@eecs.umich.edu * Constructs a physical register file with the specified amount of 1428120Sgblack@eecs.umich.edu * integer and floating point registers. 1438120Sgblack@eecs.umich.edu */ 1448120Sgblack@eecs.umich.edu PhysRegFile(unsigned _numPhysicalIntRegs, 1458120Sgblack@eecs.umich.edu unsigned _numPhysicalFloatRegs, 1468879Ssteve.reinhardt@amd.com unsigned _numPhysicalVecRegs, 1478879Ssteve.reinhardt@amd.com unsigned _numPhysicalVecPredRegs, 1488879Ssteve.reinhardt@amd.com unsigned _numPhysicalCCRegs, 1498879Ssteve.reinhardt@amd.com VecMode vmode 1508879Ssteve.reinhardt@amd.com ); 1518879Ssteve.reinhardt@amd.com 1528879Ssteve.reinhardt@amd.com /** 1538879Ssteve.reinhardt@amd.com * Destructor to free resources 1548879Ssteve.reinhardt@amd.com */ 1558879Ssteve.reinhardt@amd.com ~PhysRegFile() {} 1568879Ssteve.reinhardt@amd.com 1578879Ssteve.reinhardt@amd.com /** Initialize the free list */ 1588879Ssteve.reinhardt@amd.com void initFreeList(UnifiedFreeList *freeList); 1598120Sgblack@eecs.umich.edu 1608120Sgblack@eecs.umich.edu /** @return the number of integer physical registers. */ 1618120Sgblack@eecs.umich.edu unsigned numIntPhysRegs() const { return numPhysicalIntRegs; } 1628120Sgblack@eecs.umich.edu 1638120Sgblack@eecs.umich.edu /** @return the number of floating-point physical registers. */ 1648120Sgblack@eecs.umich.edu unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; } 1658120Sgblack@eecs.umich.edu /** @return the number of vector physical registers. */ 1668120Sgblack@eecs.umich.edu unsigned numVecPhysRegs() const { return numPhysicalVecRegs; } 1678120Sgblack@eecs.umich.edu /** @return the number of predicate physical registers. */ 1688120Sgblack@eecs.umich.edu unsigned numPredPhysRegs() const { return numPhysicalVecPredRegs; } 1698120Sgblack@eecs.umich.edu 1708120Sgblack@eecs.umich.edu /** @return the number of vector physical registers. */ 1718120Sgblack@eecs.umich.edu unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; } 1728120Sgblack@eecs.umich.edu 1738879Ssteve.reinhardt@amd.com /** @return the number of condition-code physical registers. */ 1748879Ssteve.reinhardt@amd.com unsigned numCCPhysRegs() const { return numPhysicalCCRegs; } 1758879Ssteve.reinhardt@amd.com 1768879Ssteve.reinhardt@amd.com /** @return the total number of physical registers. */ 17710458Sandreas.hansson@arm.com unsigned totalNumPhysRegs() const { return totalNumRegs; } 17810458Sandreas.hansson@arm.com 17910458Sandreas.hansson@arm.com /** Gets a misc register PhysRegIdPtr. */ 1808879Ssteve.reinhardt@amd.com PhysRegIdPtr getMiscRegId(RegIndex reg_idx) { 1818879Ssteve.reinhardt@amd.com return &miscRegIds[reg_idx]; 1828879Ssteve.reinhardt@amd.com } 1838879Ssteve.reinhardt@amd.com 1849227Sandreas.hansson@arm.com /** Reads an integer register. */ 1859227Sandreas.hansson@arm.com RegVal 1868879Ssteve.reinhardt@amd.com readIntReg(PhysRegIdPtr phys_reg) const 1878879Ssteve.reinhardt@amd.com { 1888879Ssteve.reinhardt@amd.com assert(phys_reg->isIntPhysReg()); 1898879Ssteve.reinhardt@amd.com 19010453SAndrew.Bardsley@arm.com DPRINTF(IEW, "RegFile: Access to int register %i, has data " 19110453SAndrew.Bardsley@arm.com "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]); 19210453SAndrew.Bardsley@arm.com return intRegFile[phys_reg->index()]; 19310456SCurtis.Dunham@arm.com } 19410456SCurtis.Dunham@arm.com 19510456SCurtis.Dunham@arm.com RegVal 19610457Sandreas.hansson@arm.com readFloatReg(PhysRegIdPtr phys_reg) const 19710457Sandreas.hansson@arm.com { 19811342Sandreas.hansson@arm.com assert(phys_reg->isFloatPhysReg()); 19911342Sandreas.hansson@arm.com 2008120Sgblack@eecs.umich.edu RegVal floatRegBits = floatRegFile[phys_reg->index()]; 2018947Sandreas.hansson@arm.com 2027816Ssteve.reinhardt@amd.com DPRINTF(IEW, "RegFile: Access to float register %i as int, " 2035871Snate@binkert.org "has data %#x\n", phys_reg->index(), floatRegBits); 2045871Snate@binkert.org 2056121Snate@binkert.org return floatRegBits; 2065871Snate@binkert.org } 2075871Snate@binkert.org 2089926Sstan.czerniawski@arm.com /** Reads a vector register. */ 2099926Sstan.czerniawski@arm.com const VecRegContainer & 2109119Sandreas.hansson@arm.com readVecReg(PhysRegIdPtr phys_reg) const 21110068Sandreas.hansson@arm.com { 21210068Sandreas.hansson@arm.com assert(phys_reg->isVectorPhysReg()); 213955SN/A 2149416SAndreas.Sandberg@ARM.com DPRINTF(IEW, "RegFile: Access to vector register %i, has " 21511342Sandreas.hansson@arm.com "data %s\n", int(phys_reg->index()), 21611212Sjoseph.gross@amd.com vectorRegFile[phys_reg->index()].print()); 21711212Sjoseph.gross@amd.com 21811212Sjoseph.gross@amd.com return vectorRegFile[phys_reg->index()]; 21911212Sjoseph.gross@amd.com } 22011212Sjoseph.gross@amd.com 2219416SAndreas.Sandberg@ARM.com /** Reads a vector register for modification. */ 2229416SAndreas.Sandberg@ARM.com VecRegContainer & 2235871Snate@binkert.org getWritableVecReg(PhysRegIdPtr phys_reg) 22410584Sandreas.hansson@arm.com { 2259416SAndreas.Sandberg@ARM.com /* const_cast for not duplicating code above. */ 2269416SAndreas.Sandberg@ARM.com return const_cast<VecRegContainer&>(readVecReg(phys_reg)); 2275871Snate@binkert.org } 228955SN/A 22910671Sandreas.hansson@arm.com /** Reads a vector register lane. */ 23010671Sandreas.hansson@arm.com template <typename VecElem, int LaneIdx> 23110671Sandreas.hansson@arm.com VecLaneT<VecElem, true> 23210671Sandreas.hansson@arm.com readVecLane(PhysRegIdPtr phys_reg) const 2338881Smarc.orr@gmail.com { 2346121Snate@binkert.org return readVecReg(phys_reg).laneView<VecElem, LaneIdx>(); 2356121Snate@binkert.org } 2361533SN/A 2379239Sandreas.hansson@arm.com /** Reads a vector register lane. */ 2389239Sandreas.hansson@arm.com template <typename VecElem> 2399239Sandreas.hansson@arm.com VecLaneT<VecElem, true> 2409239Sandreas.hansson@arm.com readVecLane(PhysRegIdPtr phys_reg) const 2419239Sandreas.hansson@arm.com { 2429239Sandreas.hansson@arm.com return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex()); 2439239Sandreas.hansson@arm.com } 2449239Sandreas.hansson@arm.com 2459239Sandreas.hansson@arm.com /** Get a vector register lane for modification. */ 2469239Sandreas.hansson@arm.com template <typename LD> 2479239Sandreas.hansson@arm.com void 2489239Sandreas.hansson@arm.com setVecLane(PhysRegIdPtr phys_reg, const LD& val) 2496655Snate@binkert.org { 2506655Snate@binkert.org assert(phys_reg->isVectorPhysReg()); 2516655Snate@binkert.org 2526655Snate@binkert.org DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n", 2535871Snate@binkert.org int(phys_reg->index()), phys_reg->elemIndex(), val); 2545871Snate@binkert.org 2555863Snate@binkert.org vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>( 2565871Snate@binkert.org phys_reg->elemIndex()) = val; 2578878Ssteve.reinhardt@amd.com } 2585871Snate@binkert.org 2595871Snate@binkert.org /** Reads a vector element. */ 2605871Snate@binkert.org const VecElem & 2615863Snate@binkert.org readVecElem(PhysRegIdPtr phys_reg) const 2626121Snate@binkert.org { 2635863Snate@binkert.org assert(phys_reg->isVectorPhysElem()); 26411408Sandreas.sandberg@arm.com auto ret = vectorRegFile[phys_reg->index()].as<VecElem>(); 26511408Sandreas.sandberg@arm.com const VecElem& val = ret[phys_reg->elemIndex()]; 2668336Ssteve.reinhardt@amd.com DPRINTF(IEW, "RegFile: Access to element %d of vector register %i," 26711469SCurtis.Dunham@arm.com " has data %#x\n", phys_reg->elemIndex(), 26811469SCurtis.Dunham@arm.com int(phys_reg->index()), val); 2698336Ssteve.reinhardt@amd.com 2704678Snate@binkert.org return val; 27111887Sandreas.sandberg@arm.com } 27211887Sandreas.sandberg@arm.com 27311887Sandreas.sandberg@arm.com /** Reads a predicate register. */ 27411887Sandreas.sandberg@arm.com const VecPredRegContainer& readVecPredReg(PhysRegIdPtr phys_reg) const 27511887Sandreas.sandberg@arm.com { 27611887Sandreas.sandberg@arm.com assert(phys_reg->isVecPredPhysReg()); 27711887Sandreas.sandberg@arm.com 27811887Sandreas.sandberg@arm.com DPRINTF(IEW, "RegFile: Access to predicate register %i, has " 27911887Sandreas.sandberg@arm.com "data %s\n", int(phys_reg->index()), 28011887Sandreas.sandberg@arm.com vecPredRegFile[phys_reg->index()].print()); 28111887Sandreas.sandberg@arm.com 28211408Sandreas.sandberg@arm.com return vecPredRegFile[phys_reg->index()]; 28311401Sandreas.sandberg@arm.com } 28411401Sandreas.sandberg@arm.com 28511401Sandreas.sandberg@arm.com VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr phys_reg) 28611401Sandreas.sandberg@arm.com { 28711401Sandreas.sandberg@arm.com /* const_cast for not duplicating code above. */ 28811401Sandreas.sandberg@arm.com return const_cast<VecPredRegContainer&>(readVecPredReg(phys_reg)); 2898336Ssteve.reinhardt@amd.com } 2908336Ssteve.reinhardt@amd.com 2918336Ssteve.reinhardt@amd.com /** Reads a condition-code register. */ 2924678Snate@binkert.org RegVal 29311401Sandreas.sandberg@arm.com readCCReg(PhysRegIdPtr phys_reg) 2944678Snate@binkert.org { 2954678Snate@binkert.org assert(phys_reg->isCCPhysReg()); 29611401Sandreas.sandberg@arm.com 29711401Sandreas.sandberg@arm.com DPRINTF(IEW, "RegFile: Access to cc register %i, has " 2988336Ssteve.reinhardt@amd.com "data %#x\n", phys_reg->index(), 2994678Snate@binkert.org ccRegFile[phys_reg->index()]); 3008336Ssteve.reinhardt@amd.com 3018336Ssteve.reinhardt@amd.com return ccRegFile[phys_reg->index()]; 3028336Ssteve.reinhardt@amd.com } 3038336Ssteve.reinhardt@amd.com 3048336Ssteve.reinhardt@amd.com /** Sets an integer register to the given value. */ 3058336Ssteve.reinhardt@amd.com void 3065871Snate@binkert.org setIntReg(PhysRegIdPtr phys_reg, RegVal val) 3075871Snate@binkert.org { 3088336Ssteve.reinhardt@amd.com assert(phys_reg->isIntPhysReg()); 30911408Sandreas.sandberg@arm.com 31011408Sandreas.sandberg@arm.com DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 31111408Sandreas.sandberg@arm.com phys_reg->index(), val); 31211408Sandreas.sandberg@arm.com 31311408Sandreas.sandberg@arm.com if (!phys_reg->isZeroReg()) 31411408Sandreas.sandberg@arm.com intRegFile[phys_reg->index()] = val; 31511408Sandreas.sandberg@arm.com } 3168336Ssteve.reinhardt@amd.com 31711401Sandreas.sandberg@arm.com void 31811401Sandreas.sandberg@arm.com setFloatReg(PhysRegIdPtr phys_reg, RegVal val) 31911401Sandreas.sandberg@arm.com { 3205871Snate@binkert.org assert(phys_reg->isFloatPhysReg()); 3218336Ssteve.reinhardt@amd.com 3228336Ssteve.reinhardt@amd.com DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 32311401Sandreas.sandberg@arm.com phys_reg->index(), (uint64_t)val); 32411401Sandreas.sandberg@arm.com 32511401Sandreas.sandberg@arm.com if (!phys_reg->isZeroReg()) 32611401Sandreas.sandberg@arm.com floatRegFile[phys_reg->index()] = val; 32711401Sandreas.sandberg@arm.com } 3284678Snate@binkert.org 3295871Snate@binkert.org /** Sets a vector register to the given value. */ 3304678Snate@binkert.org void 33111401Sandreas.sandberg@arm.com setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) 33211401Sandreas.sandberg@arm.com { 33311401Sandreas.sandberg@arm.com assert(phys_reg->isVectorPhysReg()); 33411401Sandreas.sandberg@arm.com 33511401Sandreas.sandberg@arm.com DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n", 33611401Sandreas.sandberg@arm.com int(phys_reg->index()), val.print()); 33711401Sandreas.sandberg@arm.com 33811401Sandreas.sandberg@arm.com vectorRegFile[phys_reg->index()] = val; 33911401Sandreas.sandberg@arm.com } 34011401Sandreas.sandberg@arm.com 34111401Sandreas.sandberg@arm.com /** Sets a vector register to the given value. */ 34211401Sandreas.sandberg@arm.com void 34311450Sandreas.sandberg@arm.com setVecElem(PhysRegIdPtr phys_reg, const VecElem val) 34411450Sandreas.sandberg@arm.com { 34511450Sandreas.sandberg@arm.com assert(phys_reg->isVectorPhysElem()); 34611450Sandreas.sandberg@arm.com 34711450Sandreas.sandberg@arm.com DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to" 34811450Sandreas.sandberg@arm.com " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val); 34911450Sandreas.sandberg@arm.com 35011450Sandreas.sandberg@arm.com vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] = 35111450Sandreas.sandberg@arm.com val; 35211450Sandreas.sandberg@arm.com } 35311450Sandreas.sandberg@arm.com 35411401Sandreas.sandberg@arm.com /** Sets a predicate register to the given value. */ 35511450Sandreas.sandberg@arm.com void setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val) 35611450Sandreas.sandberg@arm.com { 35711450Sandreas.sandberg@arm.com assert(phys_reg->isVecPredPhysReg()); 35811401Sandreas.sandberg@arm.com 35911450Sandreas.sandberg@arm.com DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n", 36011401Sandreas.sandberg@arm.com int(phys_reg->index()), val.print()); 3618336Ssteve.reinhardt@amd.com 3628336Ssteve.reinhardt@amd.com vecPredRegFile[phys_reg->index()] = val; 3638336Ssteve.reinhardt@amd.com } 3648336Ssteve.reinhardt@amd.com 3658336Ssteve.reinhardt@amd.com /** Sets a condition-code register to the given value. */ 3668336Ssteve.reinhardt@amd.com void 3678336Ssteve.reinhardt@amd.com setCCReg(PhysRegIdPtr phys_reg, RegVal val) 3688336Ssteve.reinhardt@amd.com { 3698336Ssteve.reinhardt@amd.com assert(phys_reg->isCCPhysReg()); 3708336Ssteve.reinhardt@amd.com 37111401Sandreas.sandberg@arm.com DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n", 37211401Sandreas.sandberg@arm.com phys_reg->index(), (uint64_t)val); 3738336Ssteve.reinhardt@amd.com 3748336Ssteve.reinhardt@amd.com ccRegFile[phys_reg->index()] = val; 3758336Ssteve.reinhardt@amd.com } 3765871Snate@binkert.org 37711476Sandreas.sandberg@arm.com /** Get the PhysRegIds of the elems of a vector register. 37811476Sandreas.sandberg@arm.com * Auxiliary function to transition from Full vector mode to Elem mode. 37911476Sandreas.sandberg@arm.com */ 38011476Sandreas.sandberg@arm.com IdRange getRegElemIds(PhysRegIdPtr reg); 38111476Sandreas.sandberg@arm.com 38211476Sandreas.sandberg@arm.com /** 38311476Sandreas.sandberg@arm.com * Get the PhysRegIds of the elems of all vector registers. 38411476Sandreas.sandberg@arm.com * Auxiliary function to transition from Full vector mode to Elem mode 38511476Sandreas.sandberg@arm.com * and to initialise the rename map. 38611887Sandreas.sandberg@arm.com */ 38711887Sandreas.sandberg@arm.com IdRange getRegIds(RegClass cls); 38811887Sandreas.sandberg@arm.com 38911408Sandreas.sandberg@arm.com /** 39011887Sandreas.sandberg@arm.com * Get the true physical register id. 39111887Sandreas.sandberg@arm.com * As many parts work with PhysRegIdPtr, we need to be able to produce 39211887Sandreas.sandberg@arm.com * the pointer out of just class and register idx. 39311887Sandreas.sandberg@arm.com */ 39411887Sandreas.sandberg@arm.com PhysRegIdPtr getTrueId(PhysRegIdPtr reg); 39511887Sandreas.sandberg@arm.com}; 39611926Sgabeblack@google.com 39711926Sgabeblack@google.com 39811926Sgabeblack@google.com#endif //__CPU_O3_REGFILE_HH__ 39911926Sgabeblack@google.com