regfile.hh revision 13501:ce73744918e7 
1/*
2 * Copyright (c) 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Gabe Black
43 */
44
45#ifndef __CPU_O3_REGFILE_HH__
46#define __CPU_O3_REGFILE_HH__
47
48#include <vector>
49
50#include "arch/isa_traits.hh"
51#include "arch/kernel_stats.hh"
52#include "arch/types.hh"
53#include "base/trace.hh"
54#include "config/the_isa.hh"
55#include "cpu/o3/comm.hh"
56#include "debug/IEW.hh"
57#include "enums/VecRegRenameMode.hh"
58
59class UnifiedFreeList;
60
61/**
62 * Simple physical register file class.
63 */
64class PhysRegFile
65{
66  private:
67
68    typedef TheISA::IntReg IntReg;
69    typedef TheISA::FloatReg FloatReg;
70    typedef TheISA::FloatRegBits FloatRegBits;
71    typedef TheISA::CCReg CCReg;
72    using VecElem = TheISA::VecElem;
73    using VecRegContainer = TheISA::VecRegContainer;
74    using PhysIds = std::vector<PhysRegId>;
75    using VecMode = Enums::VecRegRenameMode;
76  public:
77    using IdRange = std::pair<PhysIds::const_iterator,
78                              PhysIds::const_iterator>;
79  private:
80    static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
81
82    /** Integer register file. */
83    std::vector<IntReg> intRegFile;
84    std::vector<PhysRegId> intRegIds;
85
86    /** Floating point register file. */
87    std::vector<FloatRegBits> floatRegFile;
88    std::vector<PhysRegId> floatRegIds;
89
90    /** Vector register file. */
91    std::vector<VecRegContainer> vectorRegFile;
92    std::vector<PhysRegId> vecRegIds;
93    std::vector<PhysRegId> vecElemIds;
94
95    /** Condition-code register file. */
96    std::vector<CCReg> ccRegFile;
97    std::vector<PhysRegId> ccRegIds;
98
99    /** Misc Reg Ids */
100    std::vector<PhysRegId> miscRegIds;
101
102    /**
103     * Number of physical general purpose registers
104     */
105    unsigned numPhysicalIntRegs;
106
107    /**
108     * Number of physical floating point registers
109     */
110    unsigned numPhysicalFloatRegs;
111
112    /**
113     * Number of physical vector registers
114     */
115    unsigned numPhysicalVecRegs;
116
117    /**
118     * Number of physical vector element registers
119     */
120    unsigned numPhysicalVecElemRegs;
121
122    /**
123     * Number of physical CC registers
124     */
125    unsigned numPhysicalCCRegs;
126
127    /** Total number of physical registers. */
128    unsigned totalNumRegs;
129
130    /** Mode in which vector registers are addressed. */
131    VecMode vecMode;
132
133  public:
134    /**
135     * Constructs a physical register file with the specified amount of
136     * integer and floating point registers.
137     */
138    PhysRegFile(unsigned _numPhysicalIntRegs,
139                unsigned _numPhysicalFloatRegs,
140                unsigned _numPhysicalVecRegs,
141                unsigned _numPhysicalCCRegs,
142                VecMode vmode
143                );
144
145    /**
146     * Destructor to free resources
147     */
148    ~PhysRegFile() {}
149
150    /** Initialize the free list */
151    void initFreeList(UnifiedFreeList *freeList);
152
153    /** @return the number of integer physical registers. */
154    unsigned numIntPhysRegs() const { return numPhysicalIntRegs; }
155
156    /** @return the number of floating-point physical registers. */
157    unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; }
158    /** @return the number of vector physical registers. */
159    unsigned numVecPhysRegs() const { return numPhysicalVecRegs; }
160
161    /** @return the number of vector physical registers. */
162    unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; }
163
164    /** @return the number of condition-code physical registers. */
165    unsigned numCCPhysRegs() const { return numPhysicalCCRegs; }
166
167    /** @return the total number of physical registers. */
168    unsigned totalNumPhysRegs() const { return totalNumRegs; }
169
170    /** Gets a misc register PhysRegIdPtr. */
171    PhysRegIdPtr getMiscRegId(RegIndex reg_idx) {
172        return &miscRegIds[reg_idx];
173    }
174
175    /** Reads an integer register. */
176    uint64_t readIntReg(PhysRegIdPtr phys_reg) const
177    {
178        assert(phys_reg->isIntPhysReg());
179
180        DPRINTF(IEW, "RegFile: Access to int register %i, has data "
181                "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]);
182        return intRegFile[phys_reg->index()];
183    }
184
185    FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg) const
186    {
187        assert(phys_reg->isFloatPhysReg());
188
189        FloatRegBits floatRegBits = floatRegFile[phys_reg->index()];
190
191        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
192                "has data %#x\n", phys_reg->index(),
193                (uint64_t)floatRegBits);
194
195        return floatRegBits;
196    }
197
198    /** Reads a vector register. */
199    const VecRegContainer& readVecReg(PhysRegIdPtr phys_reg) const
200    {
201        assert(phys_reg->isVectorPhysReg());
202
203        DPRINTF(IEW, "RegFile: Access to vector register %i, has "
204                "data %s\n", int(phys_reg->index()),
205                vectorRegFile[phys_reg->index()].as<VecElem>().print());
206
207        return vectorRegFile[phys_reg->index()];
208    }
209
210    /** Reads a vector register for modification. */
211    VecRegContainer& getWritableVecReg(PhysRegIdPtr phys_reg)
212    {
213        /* const_cast for not duplicating code above. */
214        return const_cast<VecRegContainer&>(readVecReg(phys_reg));
215    }
216
217    /** Reads a vector register lane. */
218    template <typename VecElem, int LaneIdx>
219    VecLaneT<VecElem, true>
220    readVecLane(PhysRegIdPtr phys_reg) const
221    {
222        return readVecReg(phys_reg).laneView<VecElem, LaneIdx>();
223    }
224
225    /** Reads a vector register lane. */
226    template <typename VecElem>
227    VecLaneT<VecElem, true>
228    readVecLane(PhysRegIdPtr phys_reg) const
229    {
230        return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex());
231    }
232
233    /** Get a vector register lane for modification. */
234    template <typename LD>
235    void
236    setVecLane(PhysRegIdPtr phys_reg, const LD& val)
237    {
238        assert(phys_reg->isVectorPhysReg());
239
240        DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n",
241                int(phys_reg->index()), phys_reg->elemIndex(), val);
242
243        vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>(
244                phys_reg->elemIndex()) = val;
245    }
246
247    /** Reads a vector element. */
248    const VecElem& readVecElem(PhysRegIdPtr phys_reg) const
249    {
250        assert(phys_reg->isVectorPhysElem());
251        auto ret = vectorRegFile[phys_reg->index()].as<VecElem>();
252        const VecElem& val = ret[phys_reg->elemIndex()];
253        DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
254                " has data %#x\n", phys_reg->elemIndex(),
255                int(phys_reg->index()), val);
256
257        return val;
258    }
259
260    /** Reads a condition-code register. */
261    CCReg readCCReg(PhysRegIdPtr phys_reg)
262    {
263        assert(phys_reg->isCCPhysReg());
264
265        DPRINTF(IEW, "RegFile: Access to cc register %i, has "
266                "data %#x\n", phys_reg->index(),
267                ccRegFile[phys_reg->index()]);
268
269        return ccRegFile[phys_reg->index()];
270    }
271
272    /** Sets an integer register to the given value. */
273    void setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
274    {
275        assert(phys_reg->isIntPhysReg());
276
277        DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
278                phys_reg->index(), val);
279
280        if (!phys_reg->isZeroReg())
281            intRegFile[phys_reg->index()] = val;
282    }
283
284    void setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
285    {
286        assert(phys_reg->isFloatPhysReg());
287
288        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
289                phys_reg->index(), (uint64_t)val);
290
291        if (!phys_reg->isZeroReg())
292            floatRegFile[phys_reg->index()] = val;
293    }
294
295    /** Sets a vector register to the given value. */
296    void setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
297    {
298        assert(phys_reg->isVectorPhysReg());
299
300        DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
301                int(phys_reg->index()), val.print());
302
303        vectorRegFile[phys_reg->index()] = val;
304    }
305
306    /** Sets a vector register to the given value. */
307    void setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
308    {
309        assert(phys_reg->isVectorPhysElem());
310
311        DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
312                " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val);
313
314        vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] =
315                val;
316    }
317
318    /** Sets a condition-code register to the given value. */
319    void setCCReg(PhysRegIdPtr phys_reg, CCReg val)
320    {
321        assert(phys_reg->isCCPhysReg());
322
323        DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
324                phys_reg->index(), (uint64_t)val);
325
326        ccRegFile[phys_reg->index()] = val;
327    }
328
329    /** Get the PhysRegIds of the elems of a vector register.
330     * Auxiliary function to transition from Full vector mode to Elem mode.
331     */
332    IdRange getRegElemIds(PhysRegIdPtr reg);
333
334    /**
335     * Get the PhysRegIds of the elems of all vector registers.
336     * Auxiliary function to transition from Full vector mode to Elem mode
337     * and to initialise the rename map.
338     */
339    IdRange getRegIds(RegClass cls);
340
341     /**
342      * Get the true physical register id.
343      * As many parts work with PhysRegIdPtr, we need to be able to produce
344      * the pointer out of just class and register idx.
345      */
346     PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
347};
348
349
350#endif //__CPU_O3_REGFILE_HH__
351