regfile.hh revision 13500:6e0a2a7c6d8c 
1/*
2 * Copyright (c) 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Gabe Black
43 */
44
45#ifndef __CPU_O3_REGFILE_HH__
46#define __CPU_O3_REGFILE_HH__
47
48#include <vector>
49
50#include "arch/isa_traits.hh"
51#include "arch/kernel_stats.hh"
52#include "arch/types.hh"
53#include "base/trace.hh"
54#include "config/the_isa.hh"
55#include "cpu/o3/comm.hh"
56#include "debug/IEW.hh"
57#include "enums/VecRegRenameMode.hh"
58
59class UnifiedFreeList;
60
61/**
62 * Simple physical register file class.
63 */
64class PhysRegFile
65{
66  private:
67
68    typedef TheISA::IntReg IntReg;
69    typedef TheISA::FloatReg FloatReg;
70    typedef TheISA::FloatRegBits FloatRegBits;
71    typedef TheISA::CCReg CCReg;
72    using VecElem = TheISA::VecElem;
73    using VecRegContainer = TheISA::VecRegContainer;
74    using PhysIds = std::vector<PhysRegId>;
75    using VecMode = Enums::VecRegRenameMode;
76  public:
77    using IdRange = std::pair<PhysIds::const_iterator,
78                              PhysIds::const_iterator>;
79  private:
80    static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
81
82    typedef union {
83        FloatReg d;
84        FloatRegBits q;
85    } PhysFloatReg;
86
87    /** Integer register file. */
88    std::vector<IntReg> intRegFile;
89    std::vector<PhysRegId> intRegIds;
90
91    /** Floating point register file. */
92    std::vector<PhysFloatReg> floatRegFile;
93    std::vector<PhysRegId> floatRegIds;
94
95    /** Vector register file. */
96    std::vector<VecRegContainer> vectorRegFile;
97    std::vector<PhysRegId> vecRegIds;
98    std::vector<PhysRegId> vecElemIds;
99
100    /** Condition-code register file. */
101    std::vector<CCReg> ccRegFile;
102    std::vector<PhysRegId> ccRegIds;
103
104    /** Misc Reg Ids */
105    std::vector<PhysRegId> miscRegIds;
106
107    /**
108     * Number of physical general purpose registers
109     */
110    unsigned numPhysicalIntRegs;
111
112    /**
113     * Number of physical floating point registers
114     */
115    unsigned numPhysicalFloatRegs;
116
117    /**
118     * Number of physical vector registers
119     */
120    unsigned numPhysicalVecRegs;
121
122    /**
123     * Number of physical vector element registers
124     */
125    unsigned numPhysicalVecElemRegs;
126
127    /**
128     * Number of physical CC registers
129     */
130    unsigned numPhysicalCCRegs;
131
132    /** Total number of physical registers. */
133    unsigned totalNumRegs;
134
135    /** Mode in which vector registers are addressed. */
136    VecMode vecMode;
137
138  public:
139    /**
140     * Constructs a physical register file with the specified amount of
141     * integer and floating point registers.
142     */
143    PhysRegFile(unsigned _numPhysicalIntRegs,
144                unsigned _numPhysicalFloatRegs,
145                unsigned _numPhysicalVecRegs,
146                unsigned _numPhysicalCCRegs,
147                VecMode vmode
148                );
149
150    /**
151     * Destructor to free resources
152     */
153    ~PhysRegFile() {}
154
155    /** Initialize the free list */
156    void initFreeList(UnifiedFreeList *freeList);
157
158    /** @return the number of integer physical registers. */
159    unsigned numIntPhysRegs() const { return numPhysicalIntRegs; }
160
161    /** @return the number of floating-point physical registers. */
162    unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; }
163    /** @return the number of vector physical registers. */
164    unsigned numVecPhysRegs() const { return numPhysicalVecRegs; }
165
166    /** @return the number of vector physical registers. */
167    unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; }
168
169    /** @return the number of condition-code physical registers. */
170    unsigned numCCPhysRegs() const { return numPhysicalCCRegs; }
171
172    /** @return the total number of physical registers. */
173    unsigned totalNumPhysRegs() const { return totalNumRegs; }
174
175    /** Gets a misc register PhysRegIdPtr. */
176    PhysRegIdPtr getMiscRegId(RegIndex reg_idx) {
177        return &miscRegIds[reg_idx];
178    }
179
180    /** Reads an integer register. */
181    uint64_t readIntReg(PhysRegIdPtr phys_reg) const
182    {
183        assert(phys_reg->isIntPhysReg());
184
185        DPRINTF(IEW, "RegFile: Access to int register %i, has data "
186                "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]);
187        return intRegFile[phys_reg->index()];
188    }
189
190    FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg) const
191    {
192        assert(phys_reg->isFloatPhysReg());
193
194        FloatRegBits floatRegBits = floatRegFile[phys_reg->index()].q;
195
196        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
197                "has data %#x\n", phys_reg->index(),
198                (uint64_t)floatRegBits);
199
200        return floatRegBits;
201    }
202
203    /** Reads a vector register. */
204    const VecRegContainer& readVecReg(PhysRegIdPtr phys_reg) const
205    {
206        assert(phys_reg->isVectorPhysReg());
207
208        DPRINTF(IEW, "RegFile: Access to vector register %i, has "
209                "data %s\n", int(phys_reg->index()),
210                vectorRegFile[phys_reg->index()].as<VecElem>().print());
211
212        return vectorRegFile[phys_reg->index()];
213    }
214
215    /** Reads a vector register for modification. */
216    VecRegContainer& getWritableVecReg(PhysRegIdPtr phys_reg)
217    {
218        /* const_cast for not duplicating code above. */
219        return const_cast<VecRegContainer&>(readVecReg(phys_reg));
220    }
221
222    /** Reads a vector register lane. */
223    template <typename VecElem, int LaneIdx>
224    VecLaneT<VecElem, true>
225    readVecLane(PhysRegIdPtr phys_reg) const
226    {
227        return readVecReg(phys_reg).laneView<VecElem, LaneIdx>();
228    }
229
230    /** Reads a vector register lane. */
231    template <typename VecElem>
232    VecLaneT<VecElem, true>
233    readVecLane(PhysRegIdPtr phys_reg) const
234    {
235        return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex());
236    }
237
238    /** Get a vector register lane for modification. */
239    template <typename LD>
240    void
241    setVecLane(PhysRegIdPtr phys_reg, const LD& val)
242    {
243        assert(phys_reg->isVectorPhysReg());
244
245        DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n",
246                int(phys_reg->index()), phys_reg->elemIndex(), val);
247
248        vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>(
249                phys_reg->elemIndex()) = val;
250    }
251
252    /** Reads a vector element. */
253    const VecElem& readVecElem(PhysRegIdPtr phys_reg) const
254    {
255        assert(phys_reg->isVectorPhysElem());
256        auto ret = vectorRegFile[phys_reg->index()].as<VecElem>();
257        const VecElem& val = ret[phys_reg->elemIndex()];
258        DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
259                " has data %#x\n", phys_reg->elemIndex(),
260                int(phys_reg->index()), val);
261
262        return val;
263    }
264
265    /** Reads a condition-code register. */
266    CCReg readCCReg(PhysRegIdPtr phys_reg)
267    {
268        assert(phys_reg->isCCPhysReg());
269
270        DPRINTF(IEW, "RegFile: Access to cc register %i, has "
271                "data %#x\n", phys_reg->index(),
272                ccRegFile[phys_reg->index()]);
273
274        return ccRegFile[phys_reg->index()];
275    }
276
277    /** Sets an integer register to the given value. */
278    void setIntReg(PhysRegIdPtr phys_reg, uint64_t val)
279    {
280        assert(phys_reg->isIntPhysReg());
281
282        DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
283                phys_reg->index(), val);
284
285        if (!phys_reg->isZeroReg())
286            intRegFile[phys_reg->index()] = val;
287    }
288
289    void setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
290    {
291        assert(phys_reg->isFloatPhysReg());
292
293        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
294                phys_reg->index(), (uint64_t)val);
295
296        if (!phys_reg->isZeroReg())
297            floatRegFile[phys_reg->index()].q = val;
298    }
299
300    /** Sets a vector register to the given value. */
301    void setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
302    {
303        assert(phys_reg->isVectorPhysReg());
304
305        DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
306                int(phys_reg->index()), val.print());
307
308        vectorRegFile[phys_reg->index()] = val;
309    }
310
311    /** Sets a vector register to the given value. */
312    void setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
313    {
314        assert(phys_reg->isVectorPhysElem());
315
316        DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
317                " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val);
318
319        vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] =
320                val;
321    }
322
323    /** Sets a condition-code register to the given value. */
324    void setCCReg(PhysRegIdPtr phys_reg, CCReg val)
325    {
326        assert(phys_reg->isCCPhysReg());
327
328        DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
329                phys_reg->index(), (uint64_t)val);
330
331        ccRegFile[phys_reg->index()] = val;
332    }
333
334    /** Get the PhysRegIds of the elems of a vector register.
335     * Auxiliary function to transition from Full vector mode to Elem mode.
336     */
337    IdRange getRegElemIds(PhysRegIdPtr reg);
338
339    /**
340     * Get the PhysRegIds of the elems of all vector registers.
341     * Auxiliary function to transition from Full vector mode to Elem mode
342     * and to initialise the rename map.
343     */
344    IdRange getRegIds(RegClass cls);
345
346     /**
347      * Get the true physical register id.
348      * As many parts work with PhysRegIdPtr, we need to be able to produce
349      * the pointer out of just class and register idx.
350      */
351     PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
352};
353
354
355#endif //__CPU_O3_REGFILE_HH__
356