regfile.hh revision 10934:5af8f40d8f2c 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 *          Gabe Black
31 */
32
33#ifndef __CPU_O3_REGFILE_HH__
34#define __CPU_O3_REGFILE_HH__
35
36#include <vector>
37
38#include "arch/isa_traits.hh"
39#include "arch/kernel_stats.hh"
40#include "arch/types.hh"
41#include "base/trace.hh"
42#include "config/the_isa.hh"
43#include "cpu/o3/comm.hh"
44#include "debug/IEW.hh"
45
46class UnifiedFreeList;
47
48/**
49 * Simple physical register file class.
50 */
51class PhysRegFile
52{
53  private:
54
55    typedef TheISA::IntReg IntReg;
56    typedef TheISA::FloatReg FloatReg;
57    typedef TheISA::FloatRegBits FloatRegBits;
58    typedef TheISA::CCReg CCReg;
59    typedef TheISA::VectorReg VectorReg;
60
61    typedef union {
62        FloatReg d;
63        FloatRegBits q;
64    } PhysFloatReg;
65
66    /** Integer register file. */
67    std::vector<IntReg> intRegFile;
68
69    /** Floating point register file. */
70    std::vector<PhysFloatReg> floatRegFile;
71
72    /** Condition-code register file. */
73    std::vector<CCReg> ccRegFile;
74
75    /** Vector register file. */
76    std::vector<VectorReg> vectorRegFile;
77
78    /**
79     * The first floating-point physical register index.  The physical
80     * register file has a single continuous index space, with the
81     * initial indices mapping to the integer registers, followed
82     * immediately by the floating-point registers.  Thus the first
83     * floating-point index is equal to the number of integer
84     * registers.
85     *
86     * Note that this internal organizational detail on how physical
87     * register file indices are ordered should *NOT* be exposed
88     * outside of this class.  Other classes can use the is*PhysReg()
89     * methods to map from a physical register index to a class
90     * without knowing the internal structure of the index map.
91     */
92    unsigned baseFloatRegIndex;
93
94    /**
95     * The first condition-code physical register index.  The
96     * condition-code registers follow the floating-point registers.
97     */
98    unsigned baseCCRegIndex;
99
100    /**
101     * The first vector physical register index.  The vector registers follow
102     * the condition-code registers.
103     */
104    unsigned baseVectorRegIndex;
105
106    /** Total number of physical registers. */
107    unsigned totalNumRegs;
108
109  public:
110    /**
111     * Constructs a physical register file with the specified amount of
112     * integer and floating point registers.
113     */
114    PhysRegFile(unsigned _numPhysicalIntRegs,
115                unsigned _numPhysicalFloatRegs,
116                unsigned _numPhysicalCCRegs,
117                unsigned _numPhysicalVectorRegs);
118
119    /**
120     * Destructor to free resources
121     */
122    ~PhysRegFile() {}
123
124    /** Initialize the free list */
125    void initFreeList(UnifiedFreeList *freeList);
126
127    /** @return the number of integer physical registers. */
128    unsigned numIntPhysRegs() const { return baseFloatRegIndex; }
129
130    /** @return the number of floating-point physical registers. */
131    unsigned numFloatPhysRegs() const
132    { return baseCCRegIndex - baseFloatRegIndex; }
133
134    /** @return the number of condition-code physical registers. */
135    unsigned numCCPhysRegs() const
136    { return baseVectorRegIndex - baseCCRegIndex; }
137
138    /** @return the number of vector physical registers. */
139    unsigned numVectorPhysRegs() const
140    { return totalNumRegs - baseVectorRegIndex; }
141
142    /** @return the total number of physical registers. */
143    unsigned totalNumPhysRegs() const { return totalNumRegs; }
144
145    /**
146     * @return true if the specified physical register index
147     * corresponds to an integer physical register.
148     */
149    bool isIntPhysReg(PhysRegIndex reg_idx) const
150    {
151        return 0 <= reg_idx && reg_idx < baseFloatRegIndex;
152    }
153
154    /**
155     * @return true if the specified physical register index
156     * corresponds to a floating-point physical register.
157     */
158    bool isFloatPhysReg(PhysRegIndex reg_idx) const
159    {
160        return (baseFloatRegIndex <= reg_idx && reg_idx < baseCCRegIndex);
161    }
162
163    /**
164     * Return true if the specified physical register index
165     * corresponds to a condition-code physical register.
166     */
167    bool isCCPhysReg(PhysRegIndex reg_idx)
168    {
169        return (baseCCRegIndex <= reg_idx && reg_idx < baseVectorRegIndex);
170    }
171
172    /**
173     * @return true if the specified physical register index
174     * corresponds to a vector physical register.
175     */
176    bool isVectorPhysReg(PhysRegIndex reg_idx) const
177    {
178        return baseVectorRegIndex <= reg_idx && reg_idx < totalNumRegs;
179    }
180
181    /** Reads an integer register. */
182    uint64_t readIntReg(PhysRegIndex reg_idx) const
183    {
184        assert(isIntPhysReg(reg_idx));
185
186        DPRINTF(IEW, "RegFile: Access to int register %i, has data "
187                "%#x\n", int(reg_idx), intRegFile[reg_idx]);
188        return intRegFile[reg_idx];
189    }
190
191    /** Reads a floating point register (double precision). */
192    FloatReg readFloatReg(PhysRegIndex reg_idx) const
193    {
194        assert(isFloatPhysReg(reg_idx));
195
196        // Remove the base Float reg dependency.
197        PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex;
198
199        DPRINTF(IEW, "RegFile: Access to float register %i, has "
200                "data %#x\n", int(reg_idx), floatRegFile[reg_offset].q);
201
202        return floatRegFile[reg_offset].d;
203    }
204
205    FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) const
206    {
207        assert(isFloatPhysReg(reg_idx));
208
209        // Remove the base Float reg dependency.
210        PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex;
211
212        FloatRegBits floatRegBits = floatRegFile[reg_offset].q;
213
214        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
215                "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
216
217        return floatRegBits;
218    }
219
220    /** Reads a condition-code register. */
221    CCReg readCCReg(PhysRegIndex reg_idx)
222    {
223        assert(isCCPhysReg(reg_idx));
224
225        // Remove the base CC reg dependency.
226        PhysRegIndex reg_offset = reg_idx - baseCCRegIndex;
227
228        DPRINTF(IEW, "RegFile: Access to cc register %i, has "
229                "data %#x\n", int(reg_idx), ccRegFile[reg_offset]);
230
231        return ccRegFile[reg_offset];
232    }
233
234    /** Reads a vector register. */
235    const VectorReg &readVectorReg(PhysRegIndex reg_idx) const
236    {
237        assert(isVectorPhysReg(reg_idx));
238
239        // Remove the base vector reg dependency.
240        PhysRegIndex reg_offset = reg_idx - baseVectorRegIndex;
241
242        DPRINTF(IEW, "RegFile: Access to vector register %i\n", int(reg_idx));
243        return vectorRegFile[reg_offset];
244    }
245
246    /** Sets an integer register to the given value. */
247    void setIntReg(PhysRegIndex reg_idx, uint64_t val)
248    {
249        assert(isIntPhysReg(reg_idx));
250
251        DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
252                int(reg_idx), val);
253
254        if (reg_idx != TheISA::ZeroReg)
255            intRegFile[reg_idx] = val;
256    }
257
258    /** Sets a double precision floating point register to the given value. */
259    void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
260    {
261        assert(isFloatPhysReg(reg_idx));
262
263        // Remove the base Float reg dependency.
264        PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex;
265
266        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
267                int(reg_idx), (uint64_t)val);
268
269#if THE_ISA == ALPHA_ISA
270        if (reg_offset != TheISA::ZeroReg)
271#endif
272            floatRegFile[reg_offset].d = val;
273    }
274
275    void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
276    {
277        assert(isFloatPhysReg(reg_idx));
278
279        // Remove the base Float reg dependency.
280        PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex;
281
282        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
283                int(reg_idx), (uint64_t)val);
284
285        floatRegFile[reg_offset].q = val;
286    }
287
288    /** Sets a condition-code register to the given value. */
289    void setCCReg(PhysRegIndex reg_idx, CCReg val)
290    {
291        assert(isCCPhysReg(reg_idx));
292
293        // Remove the base CC reg dependency.
294        PhysRegIndex reg_offset = reg_idx - baseCCRegIndex;
295
296        DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
297                int(reg_idx), (uint64_t)val);
298
299        ccRegFile[reg_offset] = val;
300    }
301
302    /** Sets a vector register to the given value. */
303    void setVectorReg(PhysRegIndex reg_idx, const VectorReg &val)
304    {
305        assert(isVectorPhysReg(reg_idx));
306        // Remove the base vector reg dependency.
307        PhysRegIndex reg_offset = reg_idx - baseVectorRegIndex;
308        DPRINTF(IEW, "RegFile: Setting vector register %i\n", int(reg_idx));
309        vectorRegFile[reg_offset] = val;
310    }
311};
312
313
314#endif //__CPU_O3_REGFILE_HH__
315