regfile.hh revision 9920
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 39915Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * Redistribution and use in source and binary forms, with or without 71689SN/A * modification, are permitted provided that the following conditions are 81689SN/A * met: redistributions of source code must retain the above copyright 91689SN/A * notice, this list of conditions and the following disclaimer; 101689SN/A * redistributions in binary form must reproduce the above copyright 111689SN/A * notice, this list of conditions and the following disclaimer in the 121689SN/A * documentation and/or other materials provided with the distribution; 131689SN/A * neither the name of the copyright holders nor the names of its 141689SN/A * contributors may be used to endorse or promote products derived from 151689SN/A * this software without specific prior written permission. 161689SN/A * 171689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 302665Ssaidi@eecs.umich.edu * Gabe Black 311689SN/A */ 321689SN/A 332292SN/A#ifndef __CPU_O3_REGFILE_HH__ 342292SN/A#define __CPU_O3_REGFILE_HH__ 351060SN/A 366658Snate@binkert.org#include <vector> 376658Snate@binkert.org 382165SN/A#include "arch/isa_traits.hh" 398793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 402669Sktlim@umich.edu#include "arch/types.hh" 411681SN/A#include "base/trace.hh" 426658Snate@binkert.org#include "config/the_isa.hh" 431717SN/A#include "cpu/o3/comm.hh" 448232Snate@binkert.org#include "debug/IEW.hh" 451060SN/A 469919Ssteve.reinhardt@amd.comclass UnifiedFreeList; 479919Ssteve.reinhardt@amd.com 482292SN/A/** 492292SN/A * Simple physical register file class. 502292SN/A */ 511060SN/Aclass PhysRegFile 521060SN/A{ 539915Ssteve.reinhardt@amd.com private: 549915Ssteve.reinhardt@amd.com 552107SN/A typedef TheISA::IntReg IntReg; 562107SN/A typedef TheISA::FloatReg FloatReg; 572669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 589920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 592159SN/A 602669Sktlim@umich.edu typedef union { 612669Sktlim@umich.edu FloatReg d; 622669Sktlim@umich.edu FloatRegBits q; 632669Sktlim@umich.edu } PhysFloatReg; 641060SN/A 659915Ssteve.reinhardt@amd.com /** Integer register file. */ 669919Ssteve.reinhardt@amd.com std::vector<IntReg> intRegFile; 671060SN/A 689915Ssteve.reinhardt@amd.com /** Floating point register file. */ 699919Ssteve.reinhardt@amd.com std::vector<PhysFloatReg> floatRegFile; 709915Ssteve.reinhardt@amd.com 719920Syasuko.eckert@amd.com /** Condition-code register file. */ 729920Syasuko.eckert@amd.com std::vector<CCReg> ccRegFile; 739920Syasuko.eckert@amd.com 749915Ssteve.reinhardt@amd.com /** 759915Ssteve.reinhardt@amd.com * The first floating-point physical register index. The physical 769915Ssteve.reinhardt@amd.com * register file has a single continuous index space, with the 779915Ssteve.reinhardt@amd.com * initial indices mapping to the integer registers, followed 789915Ssteve.reinhardt@amd.com * immediately by the floating-point registers. Thus the first 799915Ssteve.reinhardt@amd.com * floating-point index is equal to the number of integer 809915Ssteve.reinhardt@amd.com * registers. 819919Ssteve.reinhardt@amd.com * 829919Ssteve.reinhardt@amd.com * Note that this internal organizational detail on how physical 839919Ssteve.reinhardt@amd.com * register file indices are ordered should *NOT* be exposed 849919Ssteve.reinhardt@amd.com * outside of this class. Other classes can use the is*PhysReg() 859919Ssteve.reinhardt@amd.com * methods to map from a physical register index to a class 869919Ssteve.reinhardt@amd.com * without knowing the internal structure of the index map. 879915Ssteve.reinhardt@amd.com */ 889915Ssteve.reinhardt@amd.com unsigned baseFloatRegIndex; 899915Ssteve.reinhardt@amd.com 909920Syasuko.eckert@amd.com /** 919920Syasuko.eckert@amd.com * The first condition-code physical register index. The 929920Syasuko.eckert@amd.com * condition-code registers follow the floating-point registers. 939920Syasuko.eckert@amd.com */ 949920Syasuko.eckert@amd.com unsigned baseCCRegIndex; 959920Syasuko.eckert@amd.com 969915Ssteve.reinhardt@amd.com /** Total number of physical registers. */ 979915Ssteve.reinhardt@amd.com unsigned totalNumRegs; 989915Ssteve.reinhardt@amd.com 991060SN/A public: 1002292SN/A /** 1012292SN/A * Constructs a physical register file with the specified amount of 1022292SN/A * integer and floating point registers. 1032292SN/A */ 1049915Ssteve.reinhardt@amd.com PhysRegFile(unsigned _numPhysicalIntRegs, 1059920Syasuko.eckert@amd.com unsigned _numPhysicalFloatRegs, 1069920Syasuko.eckert@amd.com unsigned _numPhysicalCCRegs); 1071060SN/A 1089086Sandreas.hansson@arm.com /** 1099086Sandreas.hansson@arm.com * Destructor to free resources 1109086Sandreas.hansson@arm.com */ 1119919Ssteve.reinhardt@amd.com ~PhysRegFile() {} 1129919Ssteve.reinhardt@amd.com 1139919Ssteve.reinhardt@amd.com /** Initialize the free list */ 1149919Ssteve.reinhardt@amd.com void initFreeList(UnifiedFreeList *freeList); 1159086Sandreas.hansson@arm.com 1169915Ssteve.reinhardt@amd.com /** @return the number of integer physical registers. */ 1179915Ssteve.reinhardt@amd.com unsigned numIntPhysRegs() const { return baseFloatRegIndex; } 1189915Ssteve.reinhardt@amd.com 1199915Ssteve.reinhardt@amd.com /** @return the number of floating-point physical registers. */ 1209915Ssteve.reinhardt@amd.com unsigned numFloatPhysRegs() const 1219920Syasuko.eckert@amd.com { return baseCCRegIndex - baseFloatRegIndex; } 1229920Syasuko.eckert@amd.com 1239920Syasuko.eckert@amd.com /** @return the number of condition-code physical registers. */ 1249920Syasuko.eckert@amd.com unsigned numCCPhysRegs() const 1259920Syasuko.eckert@amd.com { return totalNumRegs - baseCCRegIndex; } 1269915Ssteve.reinhardt@amd.com 1279915Ssteve.reinhardt@amd.com /** @return the total number of physical registers. */ 1289915Ssteve.reinhardt@amd.com unsigned totalNumPhysRegs() const { return totalNumRegs; } 1299915Ssteve.reinhardt@amd.com 1309915Ssteve.reinhardt@amd.com /** 1319915Ssteve.reinhardt@amd.com * @return true if the specified physical register index 1329915Ssteve.reinhardt@amd.com * corresponds to an integer physical register. 1339915Ssteve.reinhardt@amd.com */ 1349915Ssteve.reinhardt@amd.com bool isIntPhysReg(PhysRegIndex reg_idx) const 1359915Ssteve.reinhardt@amd.com { 1369915Ssteve.reinhardt@amd.com return 0 <= reg_idx && reg_idx < baseFloatRegIndex; 1379915Ssteve.reinhardt@amd.com } 1389915Ssteve.reinhardt@amd.com 1399915Ssteve.reinhardt@amd.com /** 1409915Ssteve.reinhardt@amd.com * @return true if the specified physical register index 1419915Ssteve.reinhardt@amd.com * corresponds to a floating-point physical register. 1429915Ssteve.reinhardt@amd.com */ 1439915Ssteve.reinhardt@amd.com bool isFloatPhysReg(PhysRegIndex reg_idx) const 1449915Ssteve.reinhardt@amd.com { 1459920Syasuko.eckert@amd.com return (baseFloatRegIndex <= reg_idx && reg_idx < baseCCRegIndex); 1469920Syasuko.eckert@amd.com } 1479920Syasuko.eckert@amd.com 1489920Syasuko.eckert@amd.com /** 1499920Syasuko.eckert@amd.com * Return true if the specified physical register index 1509920Syasuko.eckert@amd.com * corresponds to a condition-code physical register. 1519920Syasuko.eckert@amd.com */ 1529920Syasuko.eckert@amd.com bool isCCPhysReg(PhysRegIndex reg_idx) 1539920Syasuko.eckert@amd.com { 1549920Syasuko.eckert@amd.com return (baseCCRegIndex <= reg_idx && reg_idx < totalNumRegs); 1559915Ssteve.reinhardt@amd.com } 1561060SN/A 1572292SN/A /** Reads an integer register. */ 1589915Ssteve.reinhardt@amd.com uint64_t readIntReg(PhysRegIndex reg_idx) const 1591060SN/A { 1609915Ssteve.reinhardt@amd.com assert(isIntPhysReg(reg_idx)); 1611061SN/A 1621060SN/A DPRINTF(IEW, "RegFile: Access to int register %i, has data " 1632690Sktlim@umich.edu "%#x\n", int(reg_idx), intRegFile[reg_idx]); 1641060SN/A return intRegFile[reg_idx]; 1651060SN/A } 1661060SN/A 1672292SN/A /** Reads a floating point register (double precision). */ 1689915Ssteve.reinhardt@amd.com FloatReg readFloatReg(PhysRegIndex reg_idx) const 1691060SN/A { 1709915Ssteve.reinhardt@amd.com assert(isFloatPhysReg(reg_idx)); 1719915Ssteve.reinhardt@amd.com 1721060SN/A // Remove the base Float reg dependency. 1739915Ssteve.reinhardt@amd.com PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex; 1741060SN/A 1752455SN/A DPRINTF(IEW, "RegFile: Access to float register %i, has " 1769915Ssteve.reinhardt@amd.com "data %#x\n", int(reg_idx), floatRegFile[reg_offset].q); 1772455SN/A 1789915Ssteve.reinhardt@amd.com return floatRegFile[reg_offset].d; 1791060SN/A } 1801060SN/A 1819915Ssteve.reinhardt@amd.com FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) const 1822455SN/A { 1839915Ssteve.reinhardt@amd.com assert(isFloatPhysReg(reg_idx)); 1849915Ssteve.reinhardt@amd.com 1852455SN/A // Remove the base Float reg dependency. 1869915Ssteve.reinhardt@amd.com PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex; 1872455SN/A 1889915Ssteve.reinhardt@amd.com FloatRegBits floatRegBits = floatRegFile[reg_offset].q; 1892455SN/A 1902455SN/A DPRINTF(IEW, "RegFile: Access to float register %i as int, " 1912690Sktlim@umich.edu "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 1922455SN/A 1932455SN/A return floatRegBits; 1941060SN/A } 1951060SN/A 1969920Syasuko.eckert@amd.com /** Reads a condition-code register. */ 1979920Syasuko.eckert@amd.com CCReg readCCReg(PhysRegIndex reg_idx) 1989920Syasuko.eckert@amd.com { 1999920Syasuko.eckert@amd.com assert(isCCPhysReg(reg_idx)); 2009920Syasuko.eckert@amd.com 2019920Syasuko.eckert@amd.com // Remove the base CC reg dependency. 2029920Syasuko.eckert@amd.com PhysRegIndex reg_offset = reg_idx - baseCCRegIndex; 2039920Syasuko.eckert@amd.com 2049920Syasuko.eckert@amd.com DPRINTF(IEW, "RegFile: Access to cc register %i, has " 2059920Syasuko.eckert@amd.com "data %#x\n", int(reg_idx), ccRegFile[reg_offset]); 2069920Syasuko.eckert@amd.com 2079920Syasuko.eckert@amd.com return ccRegFile[reg_offset]; 2089920Syasuko.eckert@amd.com } 2099920Syasuko.eckert@amd.com 2102292SN/A /** Sets an integer register to the given value. */ 2111060SN/A void setIntReg(PhysRegIndex reg_idx, uint64_t val) 2121060SN/A { 2139915Ssteve.reinhardt@amd.com assert(isIntPhysReg(reg_idx)); 2141061SN/A 2152690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 2161060SN/A int(reg_idx), val); 2171060SN/A 2182292SN/A if (reg_idx != TheISA::ZeroReg) 2192292SN/A intRegFile[reg_idx] = val; 2201060SN/A } 2211060SN/A 2222292SN/A /** Sets a double precision floating point register to the given value. */ 2232455SN/A void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 2241060SN/A { 2259915Ssteve.reinhardt@amd.com assert(isFloatPhysReg(reg_idx)); 2269915Ssteve.reinhardt@amd.com 2271060SN/A // Remove the base Float reg dependency. 2289915Ssteve.reinhardt@amd.com PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex; 2291061SN/A 2302690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 2312690Sktlim@umich.edu int(reg_idx), (uint64_t)val); 2321060SN/A 2334642Sgblack@eecs.umich.edu#if THE_ISA == ALPHA_ISA 2349915Ssteve.reinhardt@amd.com if (reg_offset != TheISA::ZeroReg) 2354642Sgblack@eecs.umich.edu#endif 2369915Ssteve.reinhardt@amd.com floatRegFile[reg_offset].d = val; 2371060SN/A } 2381060SN/A 2392455SN/A void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 2402455SN/A { 2419915Ssteve.reinhardt@amd.com assert(isFloatPhysReg(reg_idx)); 2429915Ssteve.reinhardt@amd.com 2432455SN/A // Remove the base Float reg dependency. 2449915Ssteve.reinhardt@amd.com PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex; 2452455SN/A 2462690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 2472455SN/A int(reg_idx), (uint64_t)val); 2482455SN/A 2499915Ssteve.reinhardt@amd.com floatRegFile[reg_offset].q = val; 2501060SN/A } 2511060SN/A 2529920Syasuko.eckert@amd.com /** Sets a condition-code register to the given value. */ 2539920Syasuko.eckert@amd.com void setCCReg(PhysRegIndex reg_idx, CCReg val) 2549920Syasuko.eckert@amd.com { 2559920Syasuko.eckert@amd.com assert(isCCPhysReg(reg_idx)); 2569920Syasuko.eckert@amd.com 2579920Syasuko.eckert@amd.com // Remove the base CC reg dependency. 2589920Syasuko.eckert@amd.com PhysRegIndex reg_offset = reg_idx - baseCCRegIndex; 2599920Syasuko.eckert@amd.com 2609920Syasuko.eckert@amd.com DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n", 2619920Syasuko.eckert@amd.com int(reg_idx), (uint64_t)val); 2629920Syasuko.eckert@amd.com 2639920Syasuko.eckert@amd.com ccRegFile[reg_offset] = val; 2649920Syasuko.eckert@amd.com } 2651060SN/A}; 2661060SN/A 2679915Ssteve.reinhardt@amd.com 2689915Ssteve.reinhardt@amd.com#endif //__CPU_O3_REGFILE_HH__ 269