regfile.hh revision 9919
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 39915Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * Redistribution and use in source and binary forms, with or without 71689SN/A * modification, are permitted provided that the following conditions are 81689SN/A * met: redistributions of source code must retain the above copyright 91689SN/A * notice, this list of conditions and the following disclaimer; 101689SN/A * redistributions in binary form must reproduce the above copyright 111689SN/A * notice, this list of conditions and the following disclaimer in the 121689SN/A * documentation and/or other materials provided with the distribution; 131689SN/A * neither the name of the copyright holders nor the names of its 141689SN/A * contributors may be used to endorse or promote products derived from 151689SN/A * this software without specific prior written permission. 161689SN/A * 171689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 302665Ssaidi@eecs.umich.edu * Gabe Black 311689SN/A */ 321689SN/A 332292SN/A#ifndef __CPU_O3_REGFILE_HH__ 342292SN/A#define __CPU_O3_REGFILE_HH__ 351060SN/A 366658Snate@binkert.org#include <vector> 376658Snate@binkert.org 382165SN/A#include "arch/isa_traits.hh" 398793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 402669Sktlim@umich.edu#include "arch/types.hh" 411681SN/A#include "base/trace.hh" 426658Snate@binkert.org#include "config/the_isa.hh" 431717SN/A#include "cpu/o3/comm.hh" 448232Snate@binkert.org#include "debug/IEW.hh" 451060SN/A 469919Ssteve.reinhardt@amd.comclass UnifiedFreeList; 479919Ssteve.reinhardt@amd.com 482292SN/A/** 492292SN/A * Simple physical register file class. 502292SN/A */ 511060SN/Aclass PhysRegFile 521060SN/A{ 539915Ssteve.reinhardt@amd.com private: 549915Ssteve.reinhardt@amd.com 552107SN/A typedef TheISA::IntReg IntReg; 562107SN/A typedef TheISA::FloatReg FloatReg; 572669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 582159SN/A 592669Sktlim@umich.edu typedef union { 602669Sktlim@umich.edu FloatReg d; 612669Sktlim@umich.edu FloatRegBits q; 622669Sktlim@umich.edu } PhysFloatReg; 631060SN/A 649915Ssteve.reinhardt@amd.com /** Integer register file. */ 659919Ssteve.reinhardt@amd.com std::vector<IntReg> intRegFile; 661060SN/A 679915Ssteve.reinhardt@amd.com /** Floating point register file. */ 689919Ssteve.reinhardt@amd.com std::vector<PhysFloatReg> floatRegFile; 699915Ssteve.reinhardt@amd.com 709915Ssteve.reinhardt@amd.com /** 719915Ssteve.reinhardt@amd.com * The first floating-point physical register index. The physical 729915Ssteve.reinhardt@amd.com * register file has a single continuous index space, with the 739915Ssteve.reinhardt@amd.com * initial indices mapping to the integer registers, followed 749915Ssteve.reinhardt@amd.com * immediately by the floating-point registers. Thus the first 759915Ssteve.reinhardt@amd.com * floating-point index is equal to the number of integer 769915Ssteve.reinhardt@amd.com * registers. 779919Ssteve.reinhardt@amd.com * 789919Ssteve.reinhardt@amd.com * Note that this internal organizational detail on how physical 799919Ssteve.reinhardt@amd.com * register file indices are ordered should *NOT* be exposed 809919Ssteve.reinhardt@amd.com * outside of this class. Other classes can use the is*PhysReg() 819919Ssteve.reinhardt@amd.com * methods to map from a physical register index to a class 829919Ssteve.reinhardt@amd.com * without knowing the internal structure of the index map. 839915Ssteve.reinhardt@amd.com */ 849915Ssteve.reinhardt@amd.com unsigned baseFloatRegIndex; 859915Ssteve.reinhardt@amd.com 869915Ssteve.reinhardt@amd.com /** Total number of physical registers. */ 879915Ssteve.reinhardt@amd.com unsigned totalNumRegs; 889915Ssteve.reinhardt@amd.com 891060SN/A public: 902292SN/A /** 912292SN/A * Constructs a physical register file with the specified amount of 922292SN/A * integer and floating point registers. 932292SN/A */ 949915Ssteve.reinhardt@amd.com PhysRegFile(unsigned _numPhysicalIntRegs, 951060SN/A unsigned _numPhysicalFloatRegs); 961060SN/A 979086Sandreas.hansson@arm.com /** 989086Sandreas.hansson@arm.com * Destructor to free resources 999086Sandreas.hansson@arm.com */ 1009919Ssteve.reinhardt@amd.com ~PhysRegFile() {} 1019919Ssteve.reinhardt@amd.com 1029919Ssteve.reinhardt@amd.com /** Initialize the free list */ 1039919Ssteve.reinhardt@amd.com void initFreeList(UnifiedFreeList *freeList); 1049086Sandreas.hansson@arm.com 1059915Ssteve.reinhardt@amd.com /** @return the number of integer physical registers. */ 1069915Ssteve.reinhardt@amd.com unsigned numIntPhysRegs() const { return baseFloatRegIndex; } 1079915Ssteve.reinhardt@amd.com 1089915Ssteve.reinhardt@amd.com /** @return the number of floating-point physical registers. */ 1099915Ssteve.reinhardt@amd.com unsigned numFloatPhysRegs() const 1109915Ssteve.reinhardt@amd.com { return totalNumRegs - baseFloatRegIndex; } 1119915Ssteve.reinhardt@amd.com 1129915Ssteve.reinhardt@amd.com /** @return the total number of physical registers. */ 1139915Ssteve.reinhardt@amd.com unsigned totalNumPhysRegs() const { return totalNumRegs; } 1149915Ssteve.reinhardt@amd.com 1159915Ssteve.reinhardt@amd.com /** 1169915Ssteve.reinhardt@amd.com * @return true if the specified physical register index 1179915Ssteve.reinhardt@amd.com * corresponds to an integer physical register. 1189915Ssteve.reinhardt@amd.com */ 1199915Ssteve.reinhardt@amd.com bool isIntPhysReg(PhysRegIndex reg_idx) const 1209915Ssteve.reinhardt@amd.com { 1219915Ssteve.reinhardt@amd.com return 0 <= reg_idx && reg_idx < baseFloatRegIndex; 1229915Ssteve.reinhardt@amd.com } 1239915Ssteve.reinhardt@amd.com 1249915Ssteve.reinhardt@amd.com /** 1259915Ssteve.reinhardt@amd.com * @return true if the specified physical register index 1269915Ssteve.reinhardt@amd.com * corresponds to a floating-point physical register. 1279915Ssteve.reinhardt@amd.com */ 1289915Ssteve.reinhardt@amd.com bool isFloatPhysReg(PhysRegIndex reg_idx) const 1299915Ssteve.reinhardt@amd.com { 1309915Ssteve.reinhardt@amd.com return (baseFloatRegIndex <= reg_idx && reg_idx < totalNumRegs); 1319915Ssteve.reinhardt@amd.com } 1321060SN/A 1332292SN/A /** Reads an integer register. */ 1349915Ssteve.reinhardt@amd.com uint64_t readIntReg(PhysRegIndex reg_idx) const 1351060SN/A { 1369915Ssteve.reinhardt@amd.com assert(isIntPhysReg(reg_idx)); 1371061SN/A 1381060SN/A DPRINTF(IEW, "RegFile: Access to int register %i, has data " 1392690Sktlim@umich.edu "%#x\n", int(reg_idx), intRegFile[reg_idx]); 1401060SN/A return intRegFile[reg_idx]; 1411060SN/A } 1421060SN/A 1432292SN/A /** Reads a floating point register (double precision). */ 1449915Ssteve.reinhardt@amd.com FloatReg readFloatReg(PhysRegIndex reg_idx) const 1451060SN/A { 1469915Ssteve.reinhardt@amd.com assert(isFloatPhysReg(reg_idx)); 1479915Ssteve.reinhardt@amd.com 1481060SN/A // Remove the base Float reg dependency. 1499915Ssteve.reinhardt@amd.com PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex; 1501060SN/A 1512455SN/A DPRINTF(IEW, "RegFile: Access to float register %i, has " 1529915Ssteve.reinhardt@amd.com "data %#x\n", int(reg_idx), floatRegFile[reg_offset].q); 1532455SN/A 1549915Ssteve.reinhardt@amd.com return floatRegFile[reg_offset].d; 1551060SN/A } 1561060SN/A 1579915Ssteve.reinhardt@amd.com FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) const 1582455SN/A { 1599915Ssteve.reinhardt@amd.com assert(isFloatPhysReg(reg_idx)); 1609915Ssteve.reinhardt@amd.com 1612455SN/A // Remove the base Float reg dependency. 1629915Ssteve.reinhardt@amd.com PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex; 1632455SN/A 1649915Ssteve.reinhardt@amd.com FloatRegBits floatRegBits = floatRegFile[reg_offset].q; 1652455SN/A 1662455SN/A DPRINTF(IEW, "RegFile: Access to float register %i as int, " 1672690Sktlim@umich.edu "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 1682455SN/A 1692455SN/A return floatRegBits; 1701060SN/A } 1711060SN/A 1722292SN/A /** Sets an integer register to the given value. */ 1731060SN/A void setIntReg(PhysRegIndex reg_idx, uint64_t val) 1741060SN/A { 1759915Ssteve.reinhardt@amd.com assert(isIntPhysReg(reg_idx)); 1761061SN/A 1772690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 1781060SN/A int(reg_idx), val); 1791060SN/A 1802292SN/A if (reg_idx != TheISA::ZeroReg) 1812292SN/A intRegFile[reg_idx] = val; 1821060SN/A } 1831060SN/A 1842292SN/A /** Sets a double precision floating point register to the given value. */ 1852455SN/A void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 1861060SN/A { 1879915Ssteve.reinhardt@amd.com assert(isFloatPhysReg(reg_idx)); 1889915Ssteve.reinhardt@amd.com 1891060SN/A // Remove the base Float reg dependency. 1909915Ssteve.reinhardt@amd.com PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex; 1911061SN/A 1922690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 1932690Sktlim@umich.edu int(reg_idx), (uint64_t)val); 1941060SN/A 1954642Sgblack@eecs.umich.edu#if THE_ISA == ALPHA_ISA 1969915Ssteve.reinhardt@amd.com if (reg_offset != TheISA::ZeroReg) 1974642Sgblack@eecs.umich.edu#endif 1989915Ssteve.reinhardt@amd.com floatRegFile[reg_offset].d = val; 1991060SN/A } 2001060SN/A 2012455SN/A void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 2022455SN/A { 2039915Ssteve.reinhardt@amd.com assert(isFloatPhysReg(reg_idx)); 2049915Ssteve.reinhardt@amd.com 2052455SN/A // Remove the base Float reg dependency. 2069915Ssteve.reinhardt@amd.com PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex; 2072455SN/A 2082690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 2092455SN/A int(reg_idx), (uint64_t)val); 2102455SN/A 2119915Ssteve.reinhardt@amd.com floatRegFile[reg_offset].q = val; 2121060SN/A } 2131060SN/A 2141060SN/A}; 2151060SN/A 2169915Ssteve.reinhardt@amd.com 2179915Ssteve.reinhardt@amd.com#endif //__CPU_O3_REGFILE_HH__ 218