regfile.hh revision 9915
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 39915Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * Redistribution and use in source and binary forms, with or without 71689SN/A * modification, are permitted provided that the following conditions are 81689SN/A * met: redistributions of source code must retain the above copyright 91689SN/A * notice, this list of conditions and the following disclaimer; 101689SN/A * redistributions in binary form must reproduce the above copyright 111689SN/A * notice, this list of conditions and the following disclaimer in the 121689SN/A * documentation and/or other materials provided with the distribution; 131689SN/A * neither the name of the copyright holders nor the names of its 141689SN/A * contributors may be used to endorse or promote products derived from 151689SN/A * this software without specific prior written permission. 161689SN/A * 171689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 302665Ssaidi@eecs.umich.edu * Gabe Black 311689SN/A */ 321689SN/A 332292SN/A#ifndef __CPU_O3_REGFILE_HH__ 342292SN/A#define __CPU_O3_REGFILE_HH__ 351060SN/A 366658Snate@binkert.org#include <vector> 376658Snate@binkert.org 382165SN/A#include "arch/isa_traits.hh" 398793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 402669Sktlim@umich.edu#include "arch/types.hh" 411681SN/A#include "base/trace.hh" 426658Snate@binkert.org#include "config/the_isa.hh" 431717SN/A#include "cpu/o3/comm.hh" 448232Snate@binkert.org#include "debug/IEW.hh" 451060SN/A 462292SN/A/** 472292SN/A * Simple physical register file class. 482292SN/A */ 491060SN/Aclass PhysRegFile 501060SN/A{ 519915Ssteve.reinhardt@amd.com private: 529915Ssteve.reinhardt@amd.com 532107SN/A typedef TheISA::IntReg IntReg; 542107SN/A typedef TheISA::FloatReg FloatReg; 552669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 562159SN/A 572669Sktlim@umich.edu typedef union { 582669Sktlim@umich.edu FloatReg d; 592669Sktlim@umich.edu FloatRegBits q; 602669Sktlim@umich.edu } PhysFloatReg; 611060SN/A 629915Ssteve.reinhardt@amd.com /** Integer register file. */ 639915Ssteve.reinhardt@amd.com IntReg *intRegFile; 641060SN/A 659915Ssteve.reinhardt@amd.com /** Floating point register file. */ 669915Ssteve.reinhardt@amd.com PhysFloatReg *floatRegFile; 679915Ssteve.reinhardt@amd.com 689915Ssteve.reinhardt@amd.com /** 699915Ssteve.reinhardt@amd.com * The first floating-point physical register index. The physical 709915Ssteve.reinhardt@amd.com * register file has a single continuous index space, with the 719915Ssteve.reinhardt@amd.com * initial indices mapping to the integer registers, followed 729915Ssteve.reinhardt@amd.com * immediately by the floating-point registers. Thus the first 739915Ssteve.reinhardt@amd.com * floating-point index is equal to the number of integer 749915Ssteve.reinhardt@amd.com * registers. 759915Ssteve.reinhardt@amd.com */ 769915Ssteve.reinhardt@amd.com unsigned baseFloatRegIndex; 779915Ssteve.reinhardt@amd.com 789915Ssteve.reinhardt@amd.com /** Total number of physical registers. */ 799915Ssteve.reinhardt@amd.com unsigned totalNumRegs; 809915Ssteve.reinhardt@amd.com 811060SN/A public: 822292SN/A /** 832292SN/A * Constructs a physical register file with the specified amount of 842292SN/A * integer and floating point registers. 852292SN/A */ 869915Ssteve.reinhardt@amd.com PhysRegFile(unsigned _numPhysicalIntRegs, 871060SN/A unsigned _numPhysicalFloatRegs); 881060SN/A 899086Sandreas.hansson@arm.com /** 909086Sandreas.hansson@arm.com * Destructor to free resources 919086Sandreas.hansson@arm.com */ 929086Sandreas.hansson@arm.com ~PhysRegFile(); 939086Sandreas.hansson@arm.com 949915Ssteve.reinhardt@amd.com /** @return the number of integer physical registers. */ 959915Ssteve.reinhardt@amd.com unsigned numIntPhysRegs() const { return baseFloatRegIndex; } 969915Ssteve.reinhardt@amd.com 979915Ssteve.reinhardt@amd.com /** @return the number of floating-point physical registers. */ 989915Ssteve.reinhardt@amd.com unsigned numFloatPhysRegs() const 999915Ssteve.reinhardt@amd.com { return totalNumRegs - baseFloatRegIndex; } 1009915Ssteve.reinhardt@amd.com 1019915Ssteve.reinhardt@amd.com /** @return the total number of physical registers. */ 1029915Ssteve.reinhardt@amd.com unsigned totalNumPhysRegs() const { return totalNumRegs; } 1039915Ssteve.reinhardt@amd.com 1049915Ssteve.reinhardt@amd.com /** 1059915Ssteve.reinhardt@amd.com * @return true if the specified physical register index 1069915Ssteve.reinhardt@amd.com * corresponds to an integer physical register. 1079915Ssteve.reinhardt@amd.com */ 1089915Ssteve.reinhardt@amd.com bool isIntPhysReg(PhysRegIndex reg_idx) const 1099915Ssteve.reinhardt@amd.com { 1109915Ssteve.reinhardt@amd.com return 0 <= reg_idx && reg_idx < baseFloatRegIndex; 1119915Ssteve.reinhardt@amd.com } 1129915Ssteve.reinhardt@amd.com 1139915Ssteve.reinhardt@amd.com /** 1149915Ssteve.reinhardt@amd.com * @return true if the specified physical register index 1159915Ssteve.reinhardt@amd.com * corresponds to a floating-point physical register. 1169915Ssteve.reinhardt@amd.com */ 1179915Ssteve.reinhardt@amd.com bool isFloatPhysReg(PhysRegIndex reg_idx) const 1189915Ssteve.reinhardt@amd.com { 1199915Ssteve.reinhardt@amd.com return (baseFloatRegIndex <= reg_idx && reg_idx < totalNumRegs); 1209915Ssteve.reinhardt@amd.com } 1211060SN/A 1222292SN/A /** Reads an integer register. */ 1239915Ssteve.reinhardt@amd.com uint64_t readIntReg(PhysRegIndex reg_idx) const 1241060SN/A { 1259915Ssteve.reinhardt@amd.com assert(isIntPhysReg(reg_idx)); 1261061SN/A 1271060SN/A DPRINTF(IEW, "RegFile: Access to int register %i, has data " 1282690Sktlim@umich.edu "%#x\n", int(reg_idx), intRegFile[reg_idx]); 1291060SN/A return intRegFile[reg_idx]; 1301060SN/A } 1311060SN/A 1322292SN/A /** Reads a floating point register (double precision). */ 1339915Ssteve.reinhardt@amd.com FloatReg readFloatReg(PhysRegIndex reg_idx) const 1341060SN/A { 1359915Ssteve.reinhardt@amd.com assert(isFloatPhysReg(reg_idx)); 1369915Ssteve.reinhardt@amd.com 1371060SN/A // Remove the base Float reg dependency. 1389915Ssteve.reinhardt@amd.com PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex; 1391060SN/A 1402455SN/A DPRINTF(IEW, "RegFile: Access to float register %i, has " 1419915Ssteve.reinhardt@amd.com "data %#x\n", int(reg_idx), floatRegFile[reg_offset].q); 1422455SN/A 1439915Ssteve.reinhardt@amd.com return floatRegFile[reg_offset].d; 1441060SN/A } 1451060SN/A 1469915Ssteve.reinhardt@amd.com FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) const 1472455SN/A { 1489915Ssteve.reinhardt@amd.com assert(isFloatPhysReg(reg_idx)); 1499915Ssteve.reinhardt@amd.com 1502455SN/A // Remove the base Float reg dependency. 1519915Ssteve.reinhardt@amd.com PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex; 1522455SN/A 1539915Ssteve.reinhardt@amd.com FloatRegBits floatRegBits = floatRegFile[reg_offset].q; 1542455SN/A 1552455SN/A DPRINTF(IEW, "RegFile: Access to float register %i as int, " 1562690Sktlim@umich.edu "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 1572455SN/A 1582455SN/A return floatRegBits; 1591060SN/A } 1601060SN/A 1612292SN/A /** Sets an integer register to the given value. */ 1621060SN/A void setIntReg(PhysRegIndex reg_idx, uint64_t val) 1631060SN/A { 1649915Ssteve.reinhardt@amd.com assert(isIntPhysReg(reg_idx)); 1651061SN/A 1662690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 1671060SN/A int(reg_idx), val); 1681060SN/A 1692292SN/A if (reg_idx != TheISA::ZeroReg) 1702292SN/A intRegFile[reg_idx] = val; 1711060SN/A } 1721060SN/A 1732292SN/A /** Sets a double precision floating point register to the given value. */ 1742455SN/A void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 1751060SN/A { 1769915Ssteve.reinhardt@amd.com assert(isFloatPhysReg(reg_idx)); 1779915Ssteve.reinhardt@amd.com 1781060SN/A // Remove the base Float reg dependency. 1799915Ssteve.reinhardt@amd.com PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex; 1801061SN/A 1812690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 1822690Sktlim@umich.edu int(reg_idx), (uint64_t)val); 1831060SN/A 1844642Sgblack@eecs.umich.edu#if THE_ISA == ALPHA_ISA 1859915Ssteve.reinhardt@amd.com if (reg_offset != TheISA::ZeroReg) 1864642Sgblack@eecs.umich.edu#endif 1879915Ssteve.reinhardt@amd.com floatRegFile[reg_offset].d = val; 1881060SN/A } 1891060SN/A 1902455SN/A void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 1912455SN/A { 1929915Ssteve.reinhardt@amd.com assert(isFloatPhysReg(reg_idx)); 1939915Ssteve.reinhardt@amd.com 1942455SN/A // Remove the base Float reg dependency. 1959915Ssteve.reinhardt@amd.com PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex; 1962455SN/A 1972690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 1982455SN/A int(reg_idx), (uint64_t)val); 1992455SN/A 2009915Ssteve.reinhardt@amd.com floatRegFile[reg_offset].q = val; 2011060SN/A } 2021060SN/A 2031060SN/A}; 2041060SN/A 2059915Ssteve.reinhardt@amd.com 2069915Ssteve.reinhardt@amd.cominline 2079915Ssteve.reinhardt@amd.comPhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs, 2089915Ssteve.reinhardt@amd.com unsigned _numPhysicalFloatRegs) 2099915Ssteve.reinhardt@amd.com : baseFloatRegIndex(_numPhysicalIntRegs), 2109915Ssteve.reinhardt@amd.com totalNumRegs(_numPhysicalIntRegs + _numPhysicalFloatRegs) 2111060SN/A{ 2129915Ssteve.reinhardt@amd.com intRegFile = new IntReg[_numPhysicalIntRegs]; 2139915Ssteve.reinhardt@amd.com floatRegFile = new PhysFloatReg[_numPhysicalFloatRegs]; 2141060SN/A 2159915Ssteve.reinhardt@amd.com memset(intRegFile, 0, sizeof(IntReg) * _numPhysicalIntRegs); 2169915Ssteve.reinhardt@amd.com memset(floatRegFile, 0, sizeof(PhysFloatReg) * _numPhysicalFloatRegs); 2171060SN/A} 2181060SN/A 2199915Ssteve.reinhardt@amd.com 2209915Ssteve.reinhardt@amd.cominline 2219915Ssteve.reinhardt@amd.comPhysRegFile::~PhysRegFile() 2229086Sandreas.hansson@arm.com{ 2239086Sandreas.hansson@arm.com delete intRegFile; 2249086Sandreas.hansson@arm.com delete floatRegFile; 2259086Sandreas.hansson@arm.com} 2269086Sandreas.hansson@arm.com 2279915Ssteve.reinhardt@amd.com#endif //__CPU_O3_REGFILE_HH__ 228