regfile.hh revision 8793
1955SN/A/* 2955SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31762SN/A * All rights reserved. 4955SN/A * 5955SN/A * Redistribution and use in source and binary forms, with or without 6955SN/A * modification, are permitted provided that the following conditions are 7955SN/A * met: redistributions of source code must retain the above copyright 8955SN/A * notice, this list of conditions and the following disclaimer; 9955SN/A * redistributions in binary form must reproduce the above copyright 10955SN/A * notice, this list of conditions and the following disclaimer in the 11955SN/A * documentation and/or other materials provided with the distribution; 12955SN/A * neither the name of the copyright holders nor the names of its 13955SN/A * contributors may be used to endorse or promote products derived from 14955SN/A * this software without specific prior written permission. 15955SN/A * 16955SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17955SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18955SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19955SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20955SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21955SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22955SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23955SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24955SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25955SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26955SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27955SN/A * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292665Ssaidi@eecs.umich.edu * Gabe Black 30955SN/A */ 31955SN/A 32955SN/A#ifndef __CPU_O3_REGFILE_HH__ 33955SN/A#define __CPU_O3_REGFILE_HH__ 34955SN/A 352632Sstever@eecs.umich.edu#include <vector> 362632Sstever@eecs.umich.edu 372632Sstever@eecs.umich.edu#include "arch/isa_traits.hh" 382632Sstever@eecs.umich.edu#include "arch/kernel_stats.hh" 39955SN/A#include "arch/types.hh" 402632Sstever@eecs.umich.edu#include "base/trace.hh" 412632Sstever@eecs.umich.edu#include "config/full_system.hh" 422761Sstever@eecs.umich.edu#include "config/the_isa.hh" 432632Sstever@eecs.umich.edu#include "cpu/o3/comm.hh" 442632Sstever@eecs.umich.edu#include "debug/IEW.hh" 452632Sstever@eecs.umich.edu 462761Sstever@eecs.umich.edu/** 472761Sstever@eecs.umich.edu * Simple physical register file class. 482761Sstever@eecs.umich.edu * Right now this is specific to Alpha until we decide if/how to make things 492632Sstever@eecs.umich.edu * generic enough to support other ISAs. 502632Sstever@eecs.umich.edu */ 512761Sstever@eecs.umich.edutemplate <class Impl> 522761Sstever@eecs.umich.educlass PhysRegFile 532761Sstever@eecs.umich.edu{ 542761Sstever@eecs.umich.edu protected: 552761Sstever@eecs.umich.edu typedef TheISA::IntReg IntReg; 562632Sstever@eecs.umich.edu typedef TheISA::FloatReg FloatReg; 572632Sstever@eecs.umich.edu typedef TheISA::FloatRegBits FloatRegBits; 582632Sstever@eecs.umich.edu 592632Sstever@eecs.umich.edu typedef union { 602632Sstever@eecs.umich.edu FloatReg d; 612632Sstever@eecs.umich.edu FloatRegBits q; 622632Sstever@eecs.umich.edu } PhysFloatReg; 63955SN/A 64955SN/A // Note that most of the definitions of the IntReg, FloatReg, etc. exist 65955SN/A // within the Impl/ISA class and not within this PhysRegFile class. 66955SN/A 67955SN/A // Will make these registers public for now, but they probably should 683918Ssaidi@eecs.umich.edu // be private eventually with some accessor functions. 694202Sbinkertn@umich.edu public: 704678Snate@binkert.org typedef typename Impl::O3CPU O3CPU; 71955SN/A 722656Sstever@eecs.umich.edu /** 732656Sstever@eecs.umich.edu * Constructs a physical register file with the specified amount of 742656Sstever@eecs.umich.edu * integer and floating point registers. 752656Sstever@eecs.umich.edu */ 762656Sstever@eecs.umich.edu PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs, 772656Sstever@eecs.umich.edu unsigned _numPhysicalFloatRegs); 782656Sstever@eecs.umich.edu 792653Sstever@eecs.umich.edu //Everything below should be pretty well identical to the normal 802653Sstever@eecs.umich.edu //register file that exists within AlphaISA class. 812653Sstever@eecs.umich.edu //The duplication is unfortunate but it's better than having 822653Sstever@eecs.umich.edu //different ways to access certain registers. 832653Sstever@eecs.umich.edu 842653Sstever@eecs.umich.edu /** Reads an integer register. */ 852653Sstever@eecs.umich.edu uint64_t readIntReg(PhysRegIndex reg_idx) 862653Sstever@eecs.umich.edu { 872653Sstever@eecs.umich.edu assert(reg_idx < numPhysicalIntRegs); 882653Sstever@eecs.umich.edu 892653Sstever@eecs.umich.edu DPRINTF(IEW, "RegFile: Access to int register %i, has data " 901852SN/A "%#x\n", int(reg_idx), intRegFile[reg_idx]); 91955SN/A return intRegFile[reg_idx]; 92955SN/A } 93955SN/A 943717Sstever@eecs.umich.edu /** Reads a floating point register (double precision). */ 953716Sstever@eecs.umich.edu FloatReg readFloatReg(PhysRegIndex reg_idx) 96955SN/A { 971533SN/A // Remove the base Float reg dependency. 983716Sstever@eecs.umich.edu reg_idx = reg_idx - numPhysicalIntRegs; 991533SN/A 1004678Snate@binkert.org assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1014678Snate@binkert.org 1024678Snate@binkert.org FloatReg floatReg = floatRegFile[reg_idx].d; 1034678Snate@binkert.org 1044678Snate@binkert.org DPRINTF(IEW, "RegFile: Access to float register %i, has " 1054678Snate@binkert.org "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); 1064678Snate@binkert.org 1074678Snate@binkert.org return floatReg; 1084678Snate@binkert.org } 1094678Snate@binkert.org 1104678Snate@binkert.org FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) 1114678Snate@binkert.org { 1124678Snate@binkert.org // Remove the base Float reg dependency. 1134678Snate@binkert.org reg_idx = reg_idx - numPhysicalIntRegs; 1144678Snate@binkert.org 1154678Snate@binkert.org assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1164678Snate@binkert.org 1174678Snate@binkert.org FloatRegBits floatRegBits = floatRegFile[reg_idx].q; 1184678Snate@binkert.org 1194678Snate@binkert.org DPRINTF(IEW, "RegFile: Access to float register %i as int, " 1204678Snate@binkert.org "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 1214678Snate@binkert.org 1224678Snate@binkert.org return floatRegBits; 1234678Snate@binkert.org } 1244678Snate@binkert.org 1254678Snate@binkert.org /** Sets an integer register to the given value. */ 1264678Snate@binkert.org void setIntReg(PhysRegIndex reg_idx, uint64_t val) 1274678Snate@binkert.org { 128955SN/A assert(reg_idx < numPhysicalIntRegs); 129955SN/A 1302632Sstever@eecs.umich.edu DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 1312632Sstever@eecs.umich.edu int(reg_idx), val); 132955SN/A 133955SN/A if (reg_idx != TheISA::ZeroReg) 134955SN/A intRegFile[reg_idx] = val; 135955SN/A } 1362632Sstever@eecs.umich.edu 137955SN/A /** Sets a double precision floating point register to the given value. */ 1382632Sstever@eecs.umich.edu void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 1392632Sstever@eecs.umich.edu { 1402632Sstever@eecs.umich.edu // Remove the base Float reg dependency. 1412632Sstever@eecs.umich.edu reg_idx = reg_idx - numPhysicalIntRegs; 1422632Sstever@eecs.umich.edu 1432632Sstever@eecs.umich.edu assert(reg_idx < numPhysicalFloatRegs); 1442632Sstever@eecs.umich.edu 1453053Sstever@eecs.umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 1463053Sstever@eecs.umich.edu int(reg_idx), (uint64_t)val); 1473053Sstever@eecs.umich.edu 1483053Sstever@eecs.umich.edu#if THE_ISA == ALPHA_ISA 1493053Sstever@eecs.umich.edu if (reg_idx != TheISA::ZeroReg) 1503053Sstever@eecs.umich.edu#endif 1513053Sstever@eecs.umich.edu floatRegFile[reg_idx].d = val; 1523053Sstever@eecs.umich.edu } 1533053Sstever@eecs.umich.edu 1543053Sstever@eecs.umich.edu void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 1553053Sstever@eecs.umich.edu { 1563053Sstever@eecs.umich.edu // Remove the base Float reg dependency. 1573053Sstever@eecs.umich.edu reg_idx = reg_idx - numPhysicalIntRegs; 1583053Sstever@eecs.umich.edu 1593053Sstever@eecs.umich.edu assert(reg_idx < numPhysicalFloatRegs); 1603053Sstever@eecs.umich.edu 1612632Sstever@eecs.umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 1622632Sstever@eecs.umich.edu int(reg_idx), (uint64_t)val); 1632632Sstever@eecs.umich.edu 1642632Sstever@eecs.umich.edu floatRegFile[reg_idx].q = val; 1652632Sstever@eecs.umich.edu } 1662632Sstever@eecs.umich.edu 1673718Sstever@eecs.umich.edu public: 1683718Sstever@eecs.umich.edu /** (signed) integer register file. */ 1693718Sstever@eecs.umich.edu IntReg *intRegFile; 1703718Sstever@eecs.umich.edu 1713718Sstever@eecs.umich.edu /** Floating point register file. */ 1723718Sstever@eecs.umich.edu PhysFloatReg *floatRegFile; 1733718Sstever@eecs.umich.edu 1743718Sstever@eecs.umich.edu private: 1753718Sstever@eecs.umich.edu int intrflag; // interrupt flag 1763718Sstever@eecs.umich.edu 1773718Sstever@eecs.umich.edu private: 1783718Sstever@eecs.umich.edu /** CPU pointer. */ 1793718Sstever@eecs.umich.edu O3CPU *cpu; 1802634Sstever@eecs.umich.edu 1812634Sstever@eecs.umich.edu public: 1822632Sstever@eecs.umich.edu /** Number of physical integer registers. */ 1832638Sstever@eecs.umich.edu unsigned numPhysicalIntRegs; 1842632Sstever@eecs.umich.edu /** Number of physical floating point registers. */ 1852632Sstever@eecs.umich.edu unsigned numPhysicalFloatRegs; 1862632Sstever@eecs.umich.edu}; 1872632Sstever@eecs.umich.edu 1882632Sstever@eecs.umich.edutemplate <class Impl> 1892632Sstever@eecs.umich.eduPhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs, 1901858SN/A unsigned _numPhysicalFloatRegs) 1913716Sstever@eecs.umich.edu : cpu(_cpu), numPhysicalIntRegs(_numPhysicalIntRegs), 1922638Sstever@eecs.umich.edu numPhysicalFloatRegs(_numPhysicalFloatRegs) 1932638Sstever@eecs.umich.edu{ 1942638Sstever@eecs.umich.edu intRegFile = new IntReg[numPhysicalIntRegs]; 1952638Sstever@eecs.umich.edu floatRegFile = new PhysFloatReg[numPhysicalFloatRegs]; 1962638Sstever@eecs.umich.edu 1972638Sstever@eecs.umich.edu memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs); 1982638Sstever@eecs.umich.edu memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs); 1993716Sstever@eecs.umich.edu} 2002634Sstever@eecs.umich.edu 2012634Sstever@eecs.umich.edu#endif 202955SN/A