regfile.hh revision 8232
112771Sqtt2@cornell.edu/*
212771Sqtt2@cornell.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan
312771Sqtt2@cornell.edu * All rights reserved.
412771Sqtt2@cornell.edu *
512771Sqtt2@cornell.edu * Redistribution and use in source and binary forms, with or without
612771Sqtt2@cornell.edu * modification, are permitted provided that the following conditions are
712771Sqtt2@cornell.edu * met: redistributions of source code must retain the above copyright
812771Sqtt2@cornell.edu * notice, this list of conditions and the following disclaimer;
912771Sqtt2@cornell.edu * redistributions in binary form must reproduce the above copyright
1012771Sqtt2@cornell.edu * notice, this list of conditions and the following disclaimer in the
1112771Sqtt2@cornell.edu * documentation and/or other materials provided with the distribution;
1212771Sqtt2@cornell.edu * neither the name of the copyright holders nor the names of its
1312771Sqtt2@cornell.edu * contributors may be used to endorse or promote products derived from
1412771Sqtt2@cornell.edu * this software without specific prior written permission.
1512771Sqtt2@cornell.edu *
1612771Sqtt2@cornell.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1712771Sqtt2@cornell.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1812771Sqtt2@cornell.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1912771Sqtt2@cornell.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2012771Sqtt2@cornell.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2112771Sqtt2@cornell.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2212771Sqtt2@cornell.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2312771Sqtt2@cornell.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2412771Sqtt2@cornell.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2512771Sqtt2@cornell.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2612771Sqtt2@cornell.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2712771Sqtt2@cornell.edu *
2812771Sqtt2@cornell.edu * Authors: Kevin Lim
2912771Sqtt2@cornell.edu *          Gabe Black
3012771Sqtt2@cornell.edu */
3112771Sqtt2@cornell.edu
3212771Sqtt2@cornell.edu#ifndef __CPU_O3_REGFILE_HH__
3312771Sqtt2@cornell.edu#define __CPU_O3_REGFILE_HH__
3412771Sqtt2@cornell.edu
3512771Sqtt2@cornell.edu#include <vector>
3612771Sqtt2@cornell.edu
3712771Sqtt2@cornell.edu#include "arch/isa_traits.hh"
3812771Sqtt2@cornell.edu#include "arch/types.hh"
3912771Sqtt2@cornell.edu#include "base/trace.hh"
4012771Sqtt2@cornell.edu#include "config/full_system.hh"
4112771Sqtt2@cornell.edu#include "config/the_isa.hh"
4212771Sqtt2@cornell.edu#include "cpu/o3/comm.hh"
4312771Sqtt2@cornell.edu#include "debug/IEW.hh"
4412771Sqtt2@cornell.edu
4512771Sqtt2@cornell.edu#if FULL_SYSTEM
4612771Sqtt2@cornell.edu#include "arch/kernel_stats.hh"
4712771Sqtt2@cornell.edu#endif
4812771Sqtt2@cornell.edu
4912771Sqtt2@cornell.edu/**
5012771Sqtt2@cornell.edu * Simple physical register file class.
5112771Sqtt2@cornell.edu * Right now this is specific to Alpha until we decide if/how to make things
5212771Sqtt2@cornell.edu * generic enough to support other ISAs.
5312771Sqtt2@cornell.edu */
5412771Sqtt2@cornell.edutemplate <class Impl>
5512771Sqtt2@cornell.educlass PhysRegFile
5612771Sqtt2@cornell.edu{
5712771Sqtt2@cornell.edu  protected:
5812771Sqtt2@cornell.edu    typedef TheISA::IntReg IntReg;
5912771Sqtt2@cornell.edu    typedef TheISA::FloatReg FloatReg;
6012771Sqtt2@cornell.edu    typedef TheISA::FloatRegBits FloatRegBits;
6112771Sqtt2@cornell.edu
6212771Sqtt2@cornell.edu    typedef union {
6312771Sqtt2@cornell.edu        FloatReg d;
6412771Sqtt2@cornell.edu        FloatRegBits q;
6512771Sqtt2@cornell.edu    } PhysFloatReg;
6612771Sqtt2@cornell.edu
6712771Sqtt2@cornell.edu    // Note that most of the definitions of the IntReg, FloatReg, etc. exist
6812771Sqtt2@cornell.edu    // within the Impl/ISA class and not within this PhysRegFile class.
6912771Sqtt2@cornell.edu
7012771Sqtt2@cornell.edu    // Will make these registers public for now, but they probably should
7112771Sqtt2@cornell.edu    // be private eventually with some accessor functions.
7212771Sqtt2@cornell.edu  public:
7312771Sqtt2@cornell.edu    typedef typename Impl::O3CPU O3CPU;
7412771Sqtt2@cornell.edu
7512771Sqtt2@cornell.edu    /**
7612771Sqtt2@cornell.edu     * Constructs a physical register file with the specified amount of
7712771Sqtt2@cornell.edu     * integer and floating point registers.
78     */
79    PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
80                unsigned _numPhysicalFloatRegs);
81
82    //Everything below should be pretty well identical to the normal
83    //register file that exists within AlphaISA class.
84    //The duplication is unfortunate but it's better than having
85    //different ways to access certain registers.
86
87    /** Reads an integer register. */
88    uint64_t readIntReg(PhysRegIndex reg_idx)
89    {
90        assert(reg_idx < numPhysicalIntRegs);
91
92        DPRINTF(IEW, "RegFile: Access to int register %i, has data "
93                "%#x\n", int(reg_idx), intRegFile[reg_idx]);
94        return intRegFile[reg_idx];
95    }
96
97    /** Reads a floating point register (double precision). */
98    FloatReg readFloatReg(PhysRegIndex reg_idx)
99    {
100        // Remove the base Float reg dependency.
101        reg_idx = reg_idx - numPhysicalIntRegs;
102
103        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
104
105        FloatReg floatReg = floatRegFile[reg_idx].d;
106
107        DPRINTF(IEW, "RegFile: Access to float register %i, has "
108                "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
109
110        return floatReg;
111    }
112
113    FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
114    {
115        // Remove the base Float reg dependency.
116        reg_idx = reg_idx - numPhysicalIntRegs;
117
118        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
119
120        FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
121
122        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
123                "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
124
125        return floatRegBits;
126    }
127
128    /** Sets an integer register to the given value. */
129    void setIntReg(PhysRegIndex reg_idx, uint64_t val)
130    {
131        assert(reg_idx < numPhysicalIntRegs);
132
133        DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
134                int(reg_idx), val);
135
136        if (reg_idx != TheISA::ZeroReg)
137            intRegFile[reg_idx] = val;
138    }
139
140    /** Sets a double precision floating point register to the given value. */
141    void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
142    {
143        // Remove the base Float reg dependency.
144        reg_idx = reg_idx - numPhysicalIntRegs;
145
146        assert(reg_idx < numPhysicalFloatRegs);
147
148        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
149                int(reg_idx), (uint64_t)val);
150
151#if THE_ISA == ALPHA_ISA
152        if (reg_idx != TheISA::ZeroReg)
153#endif
154            floatRegFile[reg_idx].d = val;
155    }
156
157    void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
158    {
159        // Remove the base Float reg dependency.
160        reg_idx = reg_idx - numPhysicalIntRegs;
161
162        assert(reg_idx < numPhysicalFloatRegs);
163
164        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
165                int(reg_idx), (uint64_t)val);
166
167        floatRegFile[reg_idx].q = val;
168    }
169
170  public:
171    /** (signed) integer register file. */
172    IntReg *intRegFile;
173
174    /** Floating point register file. */
175    PhysFloatReg *floatRegFile;
176
177#if FULL_SYSTEM
178  private:
179    int intrflag;                       // interrupt flag
180#endif
181
182  private:
183    /** CPU pointer. */
184    O3CPU *cpu;
185
186  public:
187    /** Number of physical integer registers. */
188    unsigned numPhysicalIntRegs;
189    /** Number of physical floating point registers. */
190    unsigned numPhysicalFloatRegs;
191};
192
193template <class Impl>
194PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
195                               unsigned _numPhysicalFloatRegs)
196    : cpu(_cpu), numPhysicalIntRegs(_numPhysicalIntRegs),
197      numPhysicalFloatRegs(_numPhysicalFloatRegs)
198{
199    intRegFile = new IntReg[numPhysicalIntRegs];
200    floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
201
202    memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
203    memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
204}
205
206#endif
207