regfile.hh revision 8232
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292665Ssaidi@eecs.umich.edu * Gabe Black 301689SN/A */ 311689SN/A 322292SN/A#ifndef __CPU_O3_REGFILE_HH__ 332292SN/A#define __CPU_O3_REGFILE_HH__ 341060SN/A 356658Snate@binkert.org#include <vector> 366658Snate@binkert.org 372165SN/A#include "arch/isa_traits.hh" 382669Sktlim@umich.edu#include "arch/types.hh" 391681SN/A#include "base/trace.hh" 401858SN/A#include "config/full_system.hh" 416658Snate@binkert.org#include "config/the_isa.hh" 421717SN/A#include "cpu/o3/comm.hh" 438232Snate@binkert.org#include "debug/IEW.hh" 441060SN/A 451858SN/A#if FULL_SYSTEM 463565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 471681SN/A#endif 481063SN/A 492292SN/A/** 502292SN/A * Simple physical register file class. 512669Sktlim@umich.edu * Right now this is specific to Alpha until we decide if/how to make things 522669Sktlim@umich.edu * generic enough to support other ISAs. 532292SN/A */ 541061SN/Atemplate <class Impl> 551060SN/Aclass PhysRegFile 561060SN/A{ 572107SN/A protected: 582107SN/A typedef TheISA::IntReg IntReg; 592107SN/A typedef TheISA::FloatReg FloatReg; 602669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 612159SN/A 622669Sktlim@umich.edu typedef union { 632669Sktlim@umich.edu FloatReg d; 642669Sktlim@umich.edu FloatRegBits q; 652669Sktlim@umich.edu } PhysFloatReg; 661060SN/A 672292SN/A // Note that most of the definitions of the IntReg, FloatReg, etc. exist 682292SN/A // within the Impl/ISA class and not within this PhysRegFile class. 691060SN/A 702292SN/A // Will make these registers public for now, but they probably should 712292SN/A // be private eventually with some accessor functions. 721060SN/A public: 732733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 741060SN/A 752292SN/A /** 762292SN/A * Constructs a physical register file with the specified amount of 772292SN/A * integer and floating point registers. 782292SN/A */ 794329Sktlim@umich.edu PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs, 801060SN/A unsigned _numPhysicalFloatRegs); 811060SN/A 821060SN/A //Everything below should be pretty well identical to the normal 831060SN/A //register file that exists within AlphaISA class. 841060SN/A //The duplication is unfortunate but it's better than having 851060SN/A //different ways to access certain registers. 861060SN/A 872292SN/A /** Reads an integer register. */ 881060SN/A uint64_t readIntReg(PhysRegIndex reg_idx) 891060SN/A { 901061SN/A assert(reg_idx < numPhysicalIntRegs); 911061SN/A 921060SN/A DPRINTF(IEW, "RegFile: Access to int register %i, has data " 932690Sktlim@umich.edu "%#x\n", int(reg_idx), intRegFile[reg_idx]); 941060SN/A return intRegFile[reg_idx]; 951060SN/A } 961060SN/A 972292SN/A /** Reads a floating point register (double precision). */ 982455SN/A FloatReg readFloatReg(PhysRegIndex reg_idx) 991060SN/A { 1001060SN/A // Remove the base Float reg dependency. 1011060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1021060SN/A 1031062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1041061SN/A 1052669Sktlim@umich.edu FloatReg floatReg = floatRegFile[reg_idx].d; 1061060SN/A 1072455SN/A DPRINTF(IEW, "RegFile: Access to float register %i, has " 1082690Sktlim@umich.edu "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); 1092455SN/A 1102455SN/A return floatReg; 1111060SN/A } 1121060SN/A 1132455SN/A FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) 1142455SN/A { 1152455SN/A // Remove the base Float reg dependency. 1162455SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1172455SN/A 1182455SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1192455SN/A 1202669Sktlim@umich.edu FloatRegBits floatRegBits = floatRegFile[reg_idx].q; 1212455SN/A 1222455SN/A DPRINTF(IEW, "RegFile: Access to float register %i as int, " 1232690Sktlim@umich.edu "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 1242455SN/A 1252455SN/A return floatRegBits; 1261060SN/A } 1271060SN/A 1282292SN/A /** Sets an integer register to the given value. */ 1291060SN/A void setIntReg(PhysRegIndex reg_idx, uint64_t val) 1301060SN/A { 1311061SN/A assert(reg_idx < numPhysicalIntRegs); 1321061SN/A 1332690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 1341060SN/A int(reg_idx), val); 1351060SN/A 1362292SN/A if (reg_idx != TheISA::ZeroReg) 1372292SN/A intRegFile[reg_idx] = val; 1381060SN/A } 1391060SN/A 1402292SN/A /** Sets a double precision floating point register to the given value. */ 1412455SN/A void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 1421060SN/A { 1431060SN/A // Remove the base Float reg dependency. 1441060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1451060SN/A 1464352Sgblack@eecs.umich.edu assert(reg_idx < numPhysicalFloatRegs); 1471061SN/A 1482690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 1492690Sktlim@umich.edu int(reg_idx), (uint64_t)val); 1501060SN/A 1514642Sgblack@eecs.umich.edu#if THE_ISA == ALPHA_ISA 1522292SN/A if (reg_idx != TheISA::ZeroReg) 1534642Sgblack@eecs.umich.edu#endif 1542669Sktlim@umich.edu floatRegFile[reg_idx].d = val; 1551060SN/A } 1561060SN/A 1572455SN/A void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 1582455SN/A { 1592455SN/A // Remove the base Float reg dependency. 1602455SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1612455SN/A 1624352Sgblack@eecs.umich.edu assert(reg_idx < numPhysicalFloatRegs); 1632455SN/A 1642690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 1652455SN/A int(reg_idx), (uint64_t)val); 1662455SN/A 1672669Sktlim@umich.edu floatRegFile[reg_idx].q = val; 1681060SN/A } 1691060SN/A 1701060SN/A public: 1711060SN/A /** (signed) integer register file. */ 1722690Sktlim@umich.edu IntReg *intRegFile; 1731060SN/A 1741060SN/A /** Floating point register file. */ 1752690Sktlim@umich.edu PhysFloatReg *floatRegFile; 1761060SN/A 1771858SN/A#if FULL_SYSTEM 1781060SN/A private: 1795543Ssaidi@eecs.umich.edu int intrflag; // interrupt flag 1801681SN/A#endif 1811681SN/A 1821681SN/A private: 1832292SN/A /** CPU pointer. */ 1842733Sktlim@umich.edu O3CPU *cpu; 1851681SN/A 1861681SN/A public: 1872292SN/A /** Number of physical integer registers. */ 1881060SN/A unsigned numPhysicalIntRegs; 1892292SN/A /** Number of physical floating point registers. */ 1901060SN/A unsigned numPhysicalFloatRegs; 1911060SN/A}; 1921060SN/A 1931061SN/Atemplate <class Impl> 1944329Sktlim@umich.eduPhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs, 1951060SN/A unsigned _numPhysicalFloatRegs) 1964329Sktlim@umich.edu : cpu(_cpu), numPhysicalIntRegs(_numPhysicalIntRegs), 1971060SN/A numPhysicalFloatRegs(_numPhysicalFloatRegs) 1981060SN/A{ 1992690Sktlim@umich.edu intRegFile = new IntReg[numPhysicalIntRegs]; 2002690Sktlim@umich.edu floatRegFile = new PhysFloatReg[numPhysicalFloatRegs]; 2011060SN/A 2022690Sktlim@umich.edu memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs); 2032690Sktlim@umich.edu memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs); 2041060SN/A} 2051060SN/A 2062292SN/A#endif 207