regfile.hh revision 6658
11689SN/A/*
21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
31689SN/A * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
292665Ssaidi@eecs.umich.edu *          Gabe Black
301689SN/A */
311689SN/A
322292SN/A#ifndef __CPU_O3_REGFILE_HH__
332292SN/A#define __CPU_O3_REGFILE_HH__
341060SN/A
356658Snate@binkert.org#include <vector>
366658Snate@binkert.org
372165SN/A#include "arch/isa_traits.hh"
382669Sktlim@umich.edu#include "arch/types.hh"
391681SN/A#include "base/trace.hh"
401858SN/A#include "config/full_system.hh"
416658Snate@binkert.org#include "config/the_isa.hh"
421717SN/A#include "cpu/o3/comm.hh"
431060SN/A
441858SN/A#if FULL_SYSTEM
453565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh"
461681SN/A#endif
471063SN/A
482292SN/A/**
492292SN/A * Simple physical register file class.
502669Sktlim@umich.edu * Right now this is specific to Alpha until we decide if/how to make things
512669Sktlim@umich.edu * generic enough to support other ISAs.
522292SN/A */
531061SN/Atemplate <class Impl>
541060SN/Aclass PhysRegFile
551060SN/A{
562107SN/A  protected:
572107SN/A    typedef TheISA::IntReg IntReg;
582107SN/A    typedef TheISA::FloatReg FloatReg;
592669Sktlim@umich.edu    typedef TheISA::FloatRegBits FloatRegBits;
602159SN/A
612669Sktlim@umich.edu    typedef union {
622669Sktlim@umich.edu        FloatReg d;
632669Sktlim@umich.edu        FloatRegBits q;
642669Sktlim@umich.edu    } PhysFloatReg;
651060SN/A
662292SN/A    // Note that most of the definitions of the IntReg, FloatReg, etc. exist
672292SN/A    // within the Impl/ISA class and not within this PhysRegFile class.
681060SN/A
692292SN/A    // Will make these registers public for now, but they probably should
702292SN/A    // be private eventually with some accessor functions.
711060SN/A  public:
722733Sktlim@umich.edu    typedef typename Impl::O3CPU O3CPU;
731060SN/A
742292SN/A    /**
752292SN/A     * Constructs a physical register file with the specified amount of
762292SN/A     * integer and floating point registers.
772292SN/A     */
784329Sktlim@umich.edu    PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
791060SN/A                unsigned _numPhysicalFloatRegs);
801060SN/A
811060SN/A    //Everything below should be pretty well identical to the normal
821060SN/A    //register file that exists within AlphaISA class.
831060SN/A    //The duplication is unfortunate but it's better than having
841060SN/A    //different ways to access certain registers.
851060SN/A
862292SN/A    /** Reads an integer register. */
871060SN/A    uint64_t readIntReg(PhysRegIndex reg_idx)
881060SN/A    {
891061SN/A        assert(reg_idx < numPhysicalIntRegs);
901061SN/A
911060SN/A        DPRINTF(IEW, "RegFile: Access to int register %i, has data "
922690Sktlim@umich.edu                "%#x\n", int(reg_idx), intRegFile[reg_idx]);
931060SN/A        return intRegFile[reg_idx];
941060SN/A    }
951060SN/A
962292SN/A    /** Reads a floating point register (double precision). */
972455SN/A    FloatReg readFloatReg(PhysRegIndex reg_idx)
981060SN/A    {
991060SN/A        // Remove the base Float reg dependency.
1001060SN/A        reg_idx = reg_idx - numPhysicalIntRegs;
1011060SN/A
1021062SN/A        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
1031061SN/A
1042669Sktlim@umich.edu        FloatReg floatReg = floatRegFile[reg_idx].d;
1051060SN/A
1062455SN/A        DPRINTF(IEW, "RegFile: Access to float register %i, has "
1072690Sktlim@umich.edu                "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
1082455SN/A
1092455SN/A        return floatReg;
1101060SN/A    }
1111060SN/A
1122455SN/A    FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
1132455SN/A    {
1142455SN/A        // Remove the base Float reg dependency.
1152455SN/A        reg_idx = reg_idx - numPhysicalIntRegs;
1162455SN/A
1172455SN/A        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
1182455SN/A
1192669Sktlim@umich.edu        FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
1202455SN/A
1212455SN/A        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
1222690Sktlim@umich.edu                "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
1232455SN/A
1242455SN/A        return floatRegBits;
1251060SN/A    }
1261060SN/A
1272292SN/A    /** Sets an integer register to the given value. */
1281060SN/A    void setIntReg(PhysRegIndex reg_idx, uint64_t val)
1291060SN/A    {
1301061SN/A        assert(reg_idx < numPhysicalIntRegs);
1311061SN/A
1322690Sktlim@umich.edu        DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
1331060SN/A                int(reg_idx), val);
1341060SN/A
1352292SN/A        if (reg_idx != TheISA::ZeroReg)
1362292SN/A            intRegFile[reg_idx] = val;
1371060SN/A    }
1381060SN/A
1392292SN/A    /** Sets a double precision floating point register to the given value. */
1402455SN/A    void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
1411060SN/A    {
1421060SN/A        // Remove the base Float reg dependency.
1431060SN/A        reg_idx = reg_idx - numPhysicalIntRegs;
1441060SN/A
1454352Sgblack@eecs.umich.edu        assert(reg_idx < numPhysicalFloatRegs);
1461061SN/A
1472690Sktlim@umich.edu        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
1482690Sktlim@umich.edu                int(reg_idx), (uint64_t)val);
1491060SN/A
1504642Sgblack@eecs.umich.edu#if THE_ISA == ALPHA_ISA
1512292SN/A        if (reg_idx != TheISA::ZeroReg)
1524642Sgblack@eecs.umich.edu#endif
1532669Sktlim@umich.edu            floatRegFile[reg_idx].d = val;
1541060SN/A    }
1551060SN/A
1562455SN/A    void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
1572455SN/A    {
1582455SN/A        // Remove the base Float reg dependency.
1592455SN/A        reg_idx = reg_idx - numPhysicalIntRegs;
1602455SN/A
1614352Sgblack@eecs.umich.edu        assert(reg_idx < numPhysicalFloatRegs);
1622455SN/A
1632690Sktlim@umich.edu        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
1642455SN/A                int(reg_idx), (uint64_t)val);
1652455SN/A
1662669Sktlim@umich.edu        floatRegFile[reg_idx].q = val;
1671060SN/A    }
1681060SN/A
1691060SN/A  public:
1701060SN/A    /** (signed) integer register file. */
1712690Sktlim@umich.edu    IntReg *intRegFile;
1721060SN/A
1731060SN/A    /** Floating point register file. */
1742690Sktlim@umich.edu    PhysFloatReg *floatRegFile;
1751060SN/A
1761858SN/A#if FULL_SYSTEM
1771060SN/A  private:
1785543Ssaidi@eecs.umich.edu    int intrflag;                       // interrupt flag
1791681SN/A#endif
1801681SN/A
1811681SN/A  private:
1822292SN/A    /** CPU pointer. */
1832733Sktlim@umich.edu    O3CPU *cpu;
1841681SN/A
1851681SN/A  public:
1862292SN/A    /** Number of physical integer registers. */
1871060SN/A    unsigned numPhysicalIntRegs;
1882292SN/A    /** Number of physical floating point registers. */
1891060SN/A    unsigned numPhysicalFloatRegs;
1901060SN/A};
1911060SN/A
1921061SN/Atemplate <class Impl>
1934329Sktlim@umich.eduPhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
1941060SN/A                               unsigned _numPhysicalFloatRegs)
1954329Sktlim@umich.edu    : cpu(_cpu), numPhysicalIntRegs(_numPhysicalIntRegs),
1961060SN/A      numPhysicalFloatRegs(_numPhysicalFloatRegs)
1971060SN/A{
1982690Sktlim@umich.edu    intRegFile = new IntReg[numPhysicalIntRegs];
1992690Sktlim@umich.edu    floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
2001060SN/A
2012690Sktlim@umich.edu    memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
2022690Sktlim@umich.edu    memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
2031060SN/A}
2041060SN/A
2052292SN/A#endif
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