regfile.hh revision 2690
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292665Ssaidi@eecs.umich.edu * Gabe Black 301689SN/A */ 311689SN/A 322292SN/A#ifndef __CPU_O3_REGFILE_HH__ 332292SN/A#define __CPU_O3_REGFILE_HH__ 341060SN/A 352165SN/A#include "arch/isa_traits.hh" 362170SN/A#include "arch/faults.hh" 372669Sktlim@umich.edu#include "arch/types.hh" 381681SN/A#include "base/trace.hh" 391858SN/A#include "config/full_system.hh" 401717SN/A#include "cpu/o3/comm.hh" 411060SN/A 421858SN/A#if FULL_SYSTEM 431681SN/A#include "kern/kernel_stats.hh" 441681SN/A 451681SN/A#endif 461063SN/A 472292SN/A#include <vector> 481060SN/A 492292SN/A/** 502292SN/A * Simple physical register file class. 512669Sktlim@umich.edu * Right now this is specific to Alpha until we decide if/how to make things 522669Sktlim@umich.edu * generic enough to support other ISAs. 532292SN/A */ 541061SN/Atemplate <class Impl> 551060SN/Aclass PhysRegFile 561060SN/A{ 572107SN/A protected: 582107SN/A typedef TheISA::IntReg IntReg; 592107SN/A typedef TheISA::FloatReg FloatReg; 602669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 612107SN/A typedef TheISA::MiscRegFile MiscRegFile; 622159SN/A typedef TheISA::MiscReg MiscReg; 632159SN/A 642669Sktlim@umich.edu typedef union { 652669Sktlim@umich.edu FloatReg d; 662669Sktlim@umich.edu FloatRegBits q; 672669Sktlim@umich.edu } PhysFloatReg; 681060SN/A 692292SN/A // Note that most of the definitions of the IntReg, FloatReg, etc. exist 702292SN/A // within the Impl/ISA class and not within this PhysRegFile class. 711060SN/A 722292SN/A // Will make these registers public for now, but they probably should 732292SN/A // be private eventually with some accessor functions. 741060SN/A public: 751681SN/A typedef typename Impl::FullCPU FullCPU; 761060SN/A 772292SN/A /** 782292SN/A * Constructs a physical register file with the specified amount of 792292SN/A * integer and floating point registers. 802292SN/A */ 811060SN/A PhysRegFile(unsigned _numPhysicalIntRegs, 821060SN/A unsigned _numPhysicalFloatRegs); 831060SN/A 841060SN/A //Everything below should be pretty well identical to the normal 851060SN/A //register file that exists within AlphaISA class. 861060SN/A //The duplication is unfortunate but it's better than having 871060SN/A //different ways to access certain registers. 881060SN/A 891060SN/A //Add these in later when everything else is in place 901060SN/A// void serialize(std::ostream &os); 911060SN/A// void unserialize(Checkpoint *cp, const std::string §ion); 921060SN/A 932292SN/A /** Reads an integer register. */ 941060SN/A uint64_t readIntReg(PhysRegIndex reg_idx) 951060SN/A { 961061SN/A assert(reg_idx < numPhysicalIntRegs); 971061SN/A 981060SN/A DPRINTF(IEW, "RegFile: Access to int register %i, has data " 992690Sktlim@umich.edu "%#x\n", int(reg_idx), intRegFile[reg_idx]); 1001060SN/A return intRegFile[reg_idx]; 1011060SN/A } 1021060SN/A 1032455SN/A FloatReg readFloatReg(PhysRegIndex reg_idx, int width) 1041060SN/A { 1051060SN/A // Remove the base Float reg dependency. 1061060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1071060SN/A 1081062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1091061SN/A 1102669Sktlim@umich.edu FloatReg floatReg = floatRegFile[reg_idx].d; 1111060SN/A 1122455SN/A DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " 1132690Sktlim@umich.edu "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); 1142455SN/A 1152455SN/A return floatReg; 1161060SN/A } 1171060SN/A 1182292SN/A /** Reads a floating point register (double precision). */ 1192455SN/A FloatReg readFloatReg(PhysRegIndex reg_idx) 1201060SN/A { 1211060SN/A // Remove the base Float reg dependency. 1221060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1231060SN/A 1241062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1251061SN/A 1262669Sktlim@umich.edu FloatReg floatReg = floatRegFile[reg_idx].d; 1271060SN/A 1282455SN/A DPRINTF(IEW, "RegFile: Access to float register %i, has " 1292690Sktlim@umich.edu "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); 1302455SN/A 1312455SN/A return floatReg; 1321060SN/A } 1331060SN/A 1342292SN/A /** Reads a floating point register as an integer. */ 1352455SN/A FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) 1361060SN/A { 1371060SN/A // Remove the base Float reg dependency. 1381060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1391060SN/A 1401062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1411061SN/A 1422669Sktlim@umich.edu FloatRegBits floatRegBits = floatRegFile[reg_idx].q; 1431060SN/A 1442690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Access to float register %i as int, " 1452690Sktlim@umich.edu "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 1462455SN/A 1472455SN/A return floatRegBits; 1482455SN/A } 1492455SN/A 1502455SN/A FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) 1512455SN/A { 1522455SN/A // Remove the base Float reg dependency. 1532455SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1542455SN/A 1552455SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1562455SN/A 1572669Sktlim@umich.edu FloatRegBits floatRegBits = floatRegFile[reg_idx].q; 1582455SN/A 1592455SN/A DPRINTF(IEW, "RegFile: Access to float register %i as int, " 1602690Sktlim@umich.edu "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 1612455SN/A 1622455SN/A return floatRegBits; 1631060SN/A } 1641060SN/A 1652292SN/A /** Sets an integer register to the given value. */ 1661060SN/A void setIntReg(PhysRegIndex reg_idx, uint64_t val) 1671060SN/A { 1681061SN/A assert(reg_idx < numPhysicalIntRegs); 1691061SN/A 1702690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 1711060SN/A int(reg_idx), val); 1721060SN/A 1732292SN/A if (reg_idx != TheISA::ZeroReg) 1742292SN/A intRegFile[reg_idx] = val; 1751060SN/A } 1761060SN/A 1772292SN/A /** Sets a single precision floating point register to the given value. */ 1782455SN/A void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) 1791060SN/A { 1801060SN/A // Remove the base Float reg dependency. 1811060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1821060SN/A 1831062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1841061SN/A 1852690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 1862690Sktlim@umich.edu int(reg_idx), (uint64_t)val); 1871060SN/A 1882292SN/A if (reg_idx != TheISA::ZeroReg) 1892690Sktlim@umich.edu floatRegFile[reg_idx].d = val; 1901060SN/A } 1911060SN/A 1922292SN/A /** Sets a double precision floating point register to the given value. */ 1932455SN/A void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 1941060SN/A { 1951060SN/A // Remove the base Float reg dependency. 1961060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1971060SN/A 1981062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1991061SN/A 2002690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 2012690Sktlim@umich.edu int(reg_idx), (uint64_t)val); 2021060SN/A 2032292SN/A if (reg_idx != TheISA::ZeroReg) 2042669Sktlim@umich.edu floatRegFile[reg_idx].d = val; 2051060SN/A } 2061060SN/A 2072292SN/A /** Sets a floating point register to the given integer value. */ 2082455SN/A void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) 2091060SN/A { 2101060SN/A // Remove the base Float reg dependency. 2111060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 2121060SN/A 2131062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 2141061SN/A 2152690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 2162455SN/A int(reg_idx), (uint64_t)val); 2171060SN/A 2182669Sktlim@umich.edu floatRegFile[reg_idx].q = val; 2192455SN/A } 2202455SN/A 2212455SN/A void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 2222455SN/A { 2232455SN/A // Remove the base Float reg dependency. 2242455SN/A reg_idx = reg_idx - numPhysicalIntRegs; 2252455SN/A 2262455SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 2272455SN/A 2282690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 2292455SN/A int(reg_idx), (uint64_t)val); 2302455SN/A 2312669Sktlim@umich.edu floatRegFile[reg_idx].q = val; 2321060SN/A } 2331060SN/A 2342669Sktlim@umich.edu MiscReg readMiscReg(int misc_reg, unsigned thread_id) 2351060SN/A { 2362669Sktlim@umich.edu return miscRegs[thread_id].readReg(misc_reg); 2371060SN/A } 2381060SN/A 2392292SN/A MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, 2402292SN/A unsigned thread_id) 2411060SN/A { 2422292SN/A return miscRegs[thread_id].readRegWithEffect(misc_reg, fault, 2432680Sktlim@umich.edu cpu->tcBase(thread_id)); 2441060SN/A } 2451060SN/A 2462292SN/A Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id) 2471060SN/A { 2482292SN/A return miscRegs[thread_id].setReg(misc_reg, val); 2491060SN/A } 2501060SN/A 2512292SN/A Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, 2522292SN/A unsigned thread_id) 2531060SN/A { 2542292SN/A return miscRegs[thread_id].setRegWithEffect(misc_reg, val, 2552680Sktlim@umich.edu cpu->tcBase(thread_id)); 2561060SN/A } 2571060SN/A 2581858SN/A#if FULL_SYSTEM 2591060SN/A int readIntrFlag() { return intrflag; } 2602292SN/A /** Sets an interrupt flag. */ 2611060SN/A void setIntrFlag(int val) { intrflag = val; } 2621060SN/A#endif 2631060SN/A 2641060SN/A public: 2651060SN/A /** (signed) integer register file. */ 2662690Sktlim@umich.edu IntReg *intRegFile; 2671060SN/A 2681060SN/A /** Floating point register file. */ 2692690Sktlim@umich.edu PhysFloatReg *floatRegFile; 2701060SN/A 2711060SN/A /** Miscellaneous register file. */ 2722292SN/A MiscRegFile miscRegs[Impl::MaxThreads]; 2731060SN/A 2741858SN/A#if FULL_SYSTEM 2751060SN/A private: 2761681SN/A int intrflag; // interrupt flag 2771681SN/A#endif 2781681SN/A 2791681SN/A private: 2802292SN/A /** CPU pointer. */ 2811681SN/A FullCPU *cpu; 2821681SN/A 2831681SN/A public: 2842292SN/A /** Sets the CPU pointer. */ 2851681SN/A void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } 2861681SN/A 2872292SN/A /** Number of physical integer registers. */ 2881060SN/A unsigned numPhysicalIntRegs; 2892292SN/A /** Number of physical floating point registers. */ 2901060SN/A unsigned numPhysicalFloatRegs; 2911060SN/A}; 2921060SN/A 2931061SN/Atemplate <class Impl> 2941060SN/APhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, 2951060SN/A unsigned _numPhysicalFloatRegs) 2961060SN/A : numPhysicalIntRegs(_numPhysicalIntRegs), 2971060SN/A numPhysicalFloatRegs(_numPhysicalFloatRegs) 2981060SN/A{ 2992690Sktlim@umich.edu intRegFile = new IntReg[numPhysicalIntRegs]; 3002690Sktlim@umich.edu floatRegFile = new PhysFloatReg[numPhysicalFloatRegs]; 3011060SN/A 3022681Sktlim@umich.edu for (int i = 0; i < Impl::MaxThreads; ++i) { 3032681Sktlim@umich.edu miscRegs[i].clear(); 3042681Sktlim@umich.edu } 3052681Sktlim@umich.edu 3062690Sktlim@umich.edu memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs); 3072690Sktlim@umich.edu memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs); 3081060SN/A} 3091060SN/A 3102292SN/A#endif 311