regfile.hh revision 2669
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271689SN/A */ 281689SN/A 292292SN/A#ifndef __CPU_O3_REGFILE_HH__ 302292SN/A#define __CPU_O3_REGFILE_HH__ 311060SN/A 322165SN/A#include "arch/isa_traits.hh" 332170SN/A#include "arch/faults.hh" 342669Sktlim@umich.edu#include "arch/types.hh" 351681SN/A#include "base/trace.hh" 361858SN/A#include "config/full_system.hh" 371717SN/A#include "cpu/o3/comm.hh" 381060SN/A 391858SN/A#if FULL_SYSTEM 401681SN/A#include "kern/kernel_stats.hh" 411681SN/A 421681SN/A#endif 431063SN/A 442292SN/A#include <vector> 451060SN/A 462292SN/A/** 472292SN/A * Simple physical register file class. 482669Sktlim@umich.edu * Right now this is specific to Alpha until we decide if/how to make things 492669Sktlim@umich.edu * generic enough to support other ISAs. 502292SN/A */ 511061SN/Atemplate <class Impl> 521060SN/Aclass PhysRegFile 531060SN/A{ 542107SN/A protected: 552107SN/A typedef TheISA::IntReg IntReg; 562107SN/A typedef TheISA::FloatReg FloatReg; 572669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 582107SN/A typedef TheISA::MiscRegFile MiscRegFile; 592159SN/A typedef TheISA::MiscReg MiscReg; 602669Sktlim@umich.edu 612669Sktlim@umich.edu typedef union { 622669Sktlim@umich.edu FloatReg d; 632669Sktlim@umich.edu FloatRegBits q; 642669Sktlim@umich.edu } PhysFloatReg; 652669Sktlim@umich.edu 662292SN/A // Note that most of the definitions of the IntReg, FloatReg, etc. exist 672292SN/A // within the Impl/ISA class and not within this PhysRegFile class. 682159SN/A 692292SN/A // Will make these registers public for now, but they probably should 702292SN/A // be private eventually with some accessor functions. 711060SN/A public: 721681SN/A typedef typename Impl::FullCPU FullCPU; 731060SN/A 742292SN/A /** 752292SN/A * Constructs a physical register file with the specified amount of 762292SN/A * integer and floating point registers. 772292SN/A */ 781060SN/A PhysRegFile(unsigned _numPhysicalIntRegs, 791060SN/A unsigned _numPhysicalFloatRegs); 801060SN/A 811060SN/A //Everything below should be pretty well identical to the normal 821060SN/A //register file that exists within AlphaISA class. 831060SN/A //The duplication is unfortunate but it's better than having 841060SN/A //different ways to access certain registers. 851060SN/A 861060SN/A //Add these in later when everything else is in place 871060SN/A// void serialize(std::ostream &os); 881060SN/A// void unserialize(Checkpoint *cp, const std::string §ion); 891060SN/A 902292SN/A /** Reads an integer register. */ 911060SN/A uint64_t readIntReg(PhysRegIndex reg_idx) 921060SN/A { 931061SN/A assert(reg_idx < numPhysicalIntRegs); 941061SN/A 951060SN/A DPRINTF(IEW, "RegFile: Access to int register %i, has data " 961060SN/A "%i\n", int(reg_idx), intRegFile[reg_idx]); 971060SN/A return intRegFile[reg_idx]; 981060SN/A } 991060SN/A 1002455SN/A FloatReg readFloatReg(PhysRegIndex reg_idx, int width) 1011060SN/A { 1021060SN/A // Remove the base Float reg dependency. 1031060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1041060SN/A 1051062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1061061SN/A 1072669Sktlim@umich.edu FloatReg floatReg = floatRegFile[reg_idx].d; 1081060SN/A 1092455SN/A DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " 1102455SN/A "data %8.8d\n", int(reg_idx), (double)floatReg); 1112455SN/A 1122455SN/A return floatReg; 1131060SN/A } 1141060SN/A 1152292SN/A /** Reads a floating point register (double precision). */ 1162455SN/A FloatReg readFloatReg(PhysRegIndex reg_idx) 1171060SN/A { 1181060SN/A // Remove the base Float reg dependency. 1191060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1201060SN/A 1211062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1221061SN/A 1232669Sktlim@umich.edu FloatReg floatReg = floatRegFile[reg_idx].d; 1241060SN/A 1252455SN/A DPRINTF(IEW, "RegFile: Access to float register %i, has " 1262455SN/A "data %8.8d\n", int(reg_idx), (double)floatReg); 1272455SN/A 1282455SN/A return floatReg; 1291060SN/A } 1301060SN/A 1312292SN/A /** Reads a floating point register as an integer. */ 1322455SN/A FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) 1331060SN/A { 1341060SN/A // Remove the base Float reg dependency. 1351060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1361060SN/A 1371062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1381061SN/A 1392669Sktlim@umich.edu FloatRegBits floatRegBits = floatRegFile[reg_idx].q; 1401060SN/A 1412455SN/A DPRINTF(IEW, "RegFile: Access to %d byte float register %i as int, " 1422455SN/A "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits); 1432455SN/A 1442455SN/A return floatRegBits; 1452455SN/A } 1462455SN/A 1472455SN/A FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) 1482455SN/A { 1492455SN/A // Remove the base Float reg dependency. 1502455SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1512455SN/A 1522455SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1532455SN/A 1542669Sktlim@umich.edu FloatRegBits floatRegBits = floatRegFile[reg_idx].q; 1552455SN/A 1562455SN/A DPRINTF(IEW, "RegFile: Access to float register %i as int, " 1572455SN/A "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits); 1582455SN/A 1592455SN/A return floatRegBits; 1601060SN/A } 1611060SN/A 1622292SN/A /** Sets an integer register to the given value. */ 1631060SN/A void setIntReg(PhysRegIndex reg_idx, uint64_t val) 1641060SN/A { 1651061SN/A assert(reg_idx < numPhysicalIntRegs); 1661061SN/A 1671060SN/A DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n", 1681060SN/A int(reg_idx), val); 1691060SN/A 1702292SN/A if (reg_idx != TheISA::ZeroReg) 1712292SN/A intRegFile[reg_idx] = val; 1721060SN/A } 1731060SN/A 1742292SN/A /** Sets a single precision floating point register to the given value. */ 1752455SN/A void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) 1761060SN/A { 1771060SN/A // Remove the base Float reg dependency. 1781060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1791060SN/A 1801062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1811061SN/A 1822455SN/A DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n", 1832455SN/A int(reg_idx), (double)val); 1841060SN/A 1852292SN/A if (reg_idx != TheISA::ZeroReg) 1862669Sktlim@umich.edu floatRegFile[reg_idx].d = width; 1871060SN/A } 1881060SN/A 1892292SN/A /** Sets a double precision floating point register to the given value. */ 1902455SN/A void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 1911060SN/A { 1921060SN/A // Remove the base Float reg dependency. 1931060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1941060SN/A 1951062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1961061SN/A 1972455SN/A DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n", 1982455SN/A int(reg_idx), (double)val); 1991060SN/A 2002292SN/A if (reg_idx != TheISA::ZeroReg) 2012669Sktlim@umich.edu floatRegFile[reg_idx].d = val; 2021060SN/A } 2031060SN/A 2042292SN/A /** Sets a floating point register to the given integer value. */ 2052455SN/A void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) 2061060SN/A { 2071060SN/A // Remove the base Float reg dependency. 2081060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 2091060SN/A 2101062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 2111061SN/A 2121060SN/A DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 2132455SN/A int(reg_idx), (uint64_t)val); 2141060SN/A 2152669Sktlim@umich.edu floatRegFile[reg_idx].q = val; 2162455SN/A } 2172455SN/A 2182455SN/A void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 2192455SN/A { 2202455SN/A // Remove the base Float reg dependency. 2212455SN/A reg_idx = reg_idx - numPhysicalIntRegs; 2222455SN/A 2232455SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 2242455SN/A 2252455SN/A DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 2262455SN/A int(reg_idx), (uint64_t)val); 2272669Sktlim@umich.edu 2282669Sktlim@umich.edu floatRegFile[reg_idx].q = val; 2292669Sktlim@umich.edu } 2302669Sktlim@umich.edu 2312669Sktlim@umich.edu MiscReg readMiscReg(int misc_reg, unsigned thread_id) 2322669Sktlim@umich.edu { 2332669Sktlim@umich.edu return miscRegs[thread_id].readReg(misc_reg); 2341060SN/A } 2351060SN/A 2362292SN/A MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, 2372292SN/A unsigned thread_id) 2381060SN/A { 2392292SN/A return miscRegs[thread_id].readRegWithEffect(misc_reg, fault, 2402316SN/A cpu->xcBase(thread_id)); 2411060SN/A } 2421060SN/A 2432292SN/A Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id) 2441060SN/A { 2452292SN/A return miscRegs[thread_id].setReg(misc_reg, val); 2461060SN/A } 2471060SN/A 2482292SN/A Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, 2492292SN/A unsigned thread_id) 2501060SN/A { 2512292SN/A return miscRegs[thread_id].setRegWithEffect(misc_reg, val, 2522316SN/A cpu->xcBase(thread_id)); 2531060SN/A } 2541060SN/A 2551858SN/A#if FULL_SYSTEM 2561060SN/A int readIntrFlag() { return intrflag; } 2572292SN/A /** Sets an interrupt flag. */ 2581060SN/A void setIntrFlag(int val) { intrflag = val; } 2591060SN/A#endif 2601060SN/A 2611060SN/A public: 2621060SN/A /** (signed) integer register file. */ 2632292SN/A std::vector<IntReg> intRegFile; 2641060SN/A 2651060SN/A /** Floating point register file. */ 2662669Sktlim@umich.edu std::vector<PhysFloatReg> floatRegFile; 2671060SN/A 2681060SN/A /** Miscellaneous register file. */ 2692292SN/A MiscRegFile miscRegs[Impl::MaxThreads]; 2701060SN/A 2711858SN/A#if FULL_SYSTEM 2721060SN/A private: 2731681SN/A int intrflag; // interrupt flag 2741681SN/A#endif 2751681SN/A 2761681SN/A private: 2772292SN/A /** CPU pointer. */ 2781681SN/A FullCPU *cpu; 2791681SN/A 2801681SN/A public: 2812292SN/A /** Sets the CPU pointer. */ 2821681SN/A void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } 2831681SN/A 2842292SN/A /** Number of physical integer registers. */ 2851060SN/A unsigned numPhysicalIntRegs; 2862292SN/A /** Number of physical floating point registers. */ 2871060SN/A unsigned numPhysicalFloatRegs; 2881060SN/A}; 2891060SN/A 2901061SN/Atemplate <class Impl> 2911060SN/APhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, 2921060SN/A unsigned _numPhysicalFloatRegs) 2931060SN/A : numPhysicalIntRegs(_numPhysicalIntRegs), 2941060SN/A numPhysicalFloatRegs(_numPhysicalFloatRegs) 2951060SN/A{ 2962292SN/A intRegFile.resize(numPhysicalIntRegs); 2972292SN/A floatRegFile.resize(numPhysicalFloatRegs); 2981060SN/A 2992292SN/A //memset(intRegFile, 0, sizeof(*intRegFile)); 3002292SN/A //memset(floatRegFile, 0, sizeof(*floatRegFile)); 3011060SN/A} 3021060SN/A 3032292SN/A#endif 304