regfile.hh revision 2165
16498Snate@binkert.org/* 24479Sbinkertn@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 34479Sbinkertn@umich.edu * All rights reserved. 44479Sbinkertn@umich.edu * 54479Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 66498Snate@binkert.org * modification, are permitted provided that the following conditions are 74479Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 84479Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 94479Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 106498Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 114479Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 124479Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 134479Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 144479Sbinkertn@umich.edu * this software without specific prior written permission. 154479Sbinkertn@umich.edu * 166498Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174479Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184479Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194479Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204479Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214479Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224479Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234479Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244479Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254479Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264479Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276498Snate@binkert.org */ 284479Sbinkertn@umich.edu 294479Sbinkertn@umich.edu#ifndef __CPU_O3_CPU_REGFILE_HH__ 304479Sbinkertn@umich.edu#define __CPU_O3_CPU_REGFILE_HH__ 316498Snate@binkert.org 324479Sbinkertn@umich.edu// @todo: Destructor 334479Sbinkertn@umich.edu 344479Sbinkertn@umich.edu#include "arch/isa_traits.hh" 354479Sbinkertn@umich.edu#include "targetarch/faults.hh" 364479Sbinkertn@umich.edu#include "base/trace.hh" 376498Snate@binkert.org#include "config/full_system.hh" 384479Sbinkertn@umich.edu#include "cpu/o3/comm.hh" 394479Sbinkertn@umich.edu 404479Sbinkertn@umich.edu#if FULL_SYSTEM 414479Sbinkertn@umich.edu#include "targetarch/ev5.hh" 42#include "kern/kernel_stats.hh" 43 44using namespace EV5; 45#endif 46 47// This really only depends on the ISA, and not the Impl. It might be nicer 48// to see if I can make it depend on nothing... 49// Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA, 50// and should go in the AlphaFullCPU. 51 52template <class Impl> 53class PhysRegFile 54{ 55 protected: 56 typedef TheISA::IntReg IntReg; 57 typedef TheISA::FloatReg FloatReg; 58 typedef TheISA::MiscRegFile MiscRegFile; 59 //Note that most of the definitions of the IntReg, FloatReg, etc. exist 60 //within the Impl/ISA class and not within this PhysRegFile class. 61 62 //Will need some way to allow stuff like swap_palshadow to access the 63 //correct registers. Might require code changes to swap_palshadow and 64 //other execution contexts. 65 66 //Will make these registers public for now, but they probably should 67 //be private eventually with some accessor functions. 68 public: 69 typedef typename Impl::FullCPU FullCPU; 70 71 PhysRegFile(unsigned _numPhysicalIntRegs, 72 unsigned _numPhysicalFloatRegs); 73 74 //Everything below should be pretty well identical to the normal 75 //register file that exists within AlphaISA class. 76 //The duplication is unfortunate but it's better than having 77 //different ways to access certain registers. 78 79 //Add these in later when everything else is in place 80// void serialize(std::ostream &os); 81// void unserialize(Checkpoint *cp, const std::string §ion); 82 83 uint64_t readIntReg(PhysRegIndex reg_idx) 84 { 85 assert(reg_idx < numPhysicalIntRegs); 86 87 DPRINTF(IEW, "RegFile: Access to int register %i, has data " 88 "%i\n", int(reg_idx), intRegFile[reg_idx]); 89 return intRegFile[reg_idx]; 90 } 91 92 float readFloatRegSingle(PhysRegIndex reg_idx) 93 { 94 // Remove the base Float reg dependency. 95 reg_idx = reg_idx - numPhysicalIntRegs; 96 97 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 98 99 DPRINTF(IEW, "RegFile: Access to float register %i as single, has " 100 "data %8.8f\n", int(reg_idx), (float)floatRegFile[reg_idx].d); 101 102 return (float)floatRegFile[reg_idx].d; 103 } 104 105 double readFloatRegDouble(PhysRegIndex reg_idx) 106 { 107 // Remove the base Float reg dependency. 108 reg_idx = reg_idx - numPhysicalIntRegs; 109 110 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 111 112 DPRINTF(IEW, "RegFile: Access to float register %i as double, has " 113 " data %8.8f\n", int(reg_idx), floatRegFile[reg_idx].d); 114 115 return floatRegFile[reg_idx].d; 116 } 117 118 uint64_t readFloatRegInt(PhysRegIndex reg_idx) 119 { 120 // Remove the base Float reg dependency. 121 reg_idx = reg_idx - numPhysicalIntRegs; 122 123 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 124 125 DPRINTF(IEW, "RegFile: Access to float register %i as int, has data " 126 "%lli\n", int(reg_idx), floatRegFile[reg_idx].q); 127 128 return floatRegFile[reg_idx].q; 129 } 130 131 void setIntReg(PhysRegIndex reg_idx, uint64_t val) 132 { 133 assert(reg_idx < numPhysicalIntRegs); 134 135 DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n", 136 int(reg_idx), val); 137 138 intRegFile[reg_idx] = val; 139 } 140 141 void setFloatRegSingle(PhysRegIndex reg_idx, float val) 142 { 143 // Remove the base Float reg dependency. 144 reg_idx = reg_idx - numPhysicalIntRegs; 145 146 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 147 148 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n", 149 int(reg_idx), val); 150 151 floatRegFile[reg_idx].d = (double)val; 152 } 153 154 void setFloatRegDouble(PhysRegIndex reg_idx, double val) 155 { 156 // Remove the base Float reg dependency. 157 reg_idx = reg_idx - numPhysicalIntRegs; 158 159 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 160 161 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n", 162 int(reg_idx), val); 163 164 floatRegFile[reg_idx].d = val; 165 } 166 167 void setFloatRegInt(PhysRegIndex reg_idx, uint64_t val) 168 { 169 // Remove the base Float reg dependency. 170 reg_idx = reg_idx - numPhysicalIntRegs; 171 172 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 173 174 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 175 int(reg_idx), val); 176 177 floatRegFile[reg_idx].q = val; 178 } 179 180 uint64_t readPC() 181 { 182 return pc; 183 } 184 185 void setPC(uint64_t val) 186 { 187 pc = val; 188 } 189 190 void setNextPC(uint64_t val) 191 { 192 npc = val; 193 } 194 195 //Consider leaving this stuff and below in some implementation specific 196 //file as opposed to the general register file. Or have a derived class. 197 uint64_t readUniq() 198 { 199 return miscRegs.uniq; 200 } 201 202 void setUniq(uint64_t val) 203 { 204 miscRegs.uniq = val; 205 } 206 207 uint64_t readFpcr() 208 { 209 return miscRegs.fpcr; 210 } 211 212 void setFpcr(uint64_t val) 213 { 214 miscRegs.fpcr = val; 215 } 216 217#if FULL_SYSTEM 218 uint64_t readIpr(int idx, Fault &fault); 219 Fault setIpr(int idx, uint64_t val); 220 InternalProcReg *getIpr() { return ipr; } 221 int readIntrFlag() { return intrflag; } 222 void setIntrFlag(int val) { intrflag = val; } 223#endif 224 225 // These should be private eventually, but will be public for now 226 // so that I can hack around the initregs issue. 227 public: 228 /** (signed) integer register file. */ 229 IntReg *intRegFile; 230 231 /** Floating point register file. */ 232 FloatReg *floatRegFile; 233 234 /** Miscellaneous register file. */ 235 MiscRegFile miscRegs; 236 237 /** Program counter. */ 238 Addr pc; 239 240 /** Next-cycle program counter. */ 241 Addr npc; 242 243#if FULL_SYSTEM 244 private: 245 // This is ISA specifc stuff; remove it eventually once ISAImpl is used 246 IntReg palregs[NumIntRegs]; // PAL shadow registers 247 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs 248 int intrflag; // interrupt flag 249 bool pal_shadow; // using pal_shadow registers 250#endif 251 252 private: 253 FullCPU *cpu; 254 255 public: 256 void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } 257 258 unsigned numPhysicalIntRegs; 259 unsigned numPhysicalFloatRegs; 260}; 261 262template <class Impl> 263PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, 264 unsigned _numPhysicalFloatRegs) 265 : numPhysicalIntRegs(_numPhysicalIntRegs), 266 numPhysicalFloatRegs(_numPhysicalFloatRegs) 267{ 268 intRegFile = new IntReg[numPhysicalIntRegs]; 269 floatRegFile = new FloatReg[numPhysicalFloatRegs]; 270 271 memset(intRegFile, 0, sizeof(*intRegFile)); 272 memset(floatRegFile, 0, sizeof(*floatRegFile)); 273} 274 275#if FULL_SYSTEM 276 277//Problem: This code doesn't make sense at the RegFile level because it 278//needs things such as the itb and dtb. Either put it at the CPU level or 279//the DynInst level. 280template <class Impl> 281uint64_t 282PhysRegFile<Impl>::readIpr(int idx, Fault &fault) 283{ 284 uint64_t retval = 0; // return value, default 0 285 286 switch (idx) { 287 case TheISA::IPR_PALtemp0: 288 case TheISA::IPR_PALtemp1: 289 case TheISA::IPR_PALtemp2: 290 case TheISA::IPR_PALtemp3: 291 case TheISA::IPR_PALtemp4: 292 case TheISA::IPR_PALtemp5: 293 case TheISA::IPR_PALtemp6: 294 case TheISA::IPR_PALtemp7: 295 case TheISA::IPR_PALtemp8: 296 case TheISA::IPR_PALtemp9: 297 case TheISA::IPR_PALtemp10: 298 case TheISA::IPR_PALtemp11: 299 case TheISA::IPR_PALtemp12: 300 case TheISA::IPR_PALtemp13: 301 case TheISA::IPR_PALtemp14: 302 case TheISA::IPR_PALtemp15: 303 case TheISA::IPR_PALtemp16: 304 case TheISA::IPR_PALtemp17: 305 case TheISA::IPR_PALtemp18: 306 case TheISA::IPR_PALtemp19: 307 case TheISA::IPR_PALtemp20: 308 case TheISA::IPR_PALtemp21: 309 case TheISA::IPR_PALtemp22: 310 case TheISA::IPR_PALtemp23: 311 case TheISA::IPR_PAL_BASE: 312 313 case TheISA::IPR_IVPTBR: 314 case TheISA::IPR_DC_MODE: 315 case TheISA::IPR_MAF_MODE: 316 case TheISA::IPR_ISR: 317 case TheISA::IPR_EXC_ADDR: 318 case TheISA::IPR_IC_PERR_STAT: 319 case TheISA::IPR_DC_PERR_STAT: 320 case TheISA::IPR_MCSR: 321 case TheISA::IPR_ASTRR: 322 case TheISA::IPR_ASTER: 323 case TheISA::IPR_SIRR: 324 case TheISA::IPR_ICSR: 325 case TheISA::IPR_ICM: 326 case TheISA::IPR_DTB_CM: 327 case TheISA::IPR_IPLR: 328 case TheISA::IPR_INTID: 329 case TheISA::IPR_PMCTR: 330 // no side-effect 331 retval = ipr[idx]; 332 break; 333 334 case TheISA::IPR_CC: 335 retval |= ipr[idx] & ULL(0xffffffff00000000); 336 retval |= curTick & ULL(0x00000000ffffffff); 337 break; 338 339 case TheISA::IPR_VA: 340 retval = ipr[idx]; 341 break; 342 343 case TheISA::IPR_VA_FORM: 344 case TheISA::IPR_MM_STAT: 345 case TheISA::IPR_IFAULT_VA_FORM: 346 case TheISA::IPR_EXC_MASK: 347 case TheISA::IPR_EXC_SUM: 348 retval = ipr[idx]; 349 break; 350 351 case TheISA::IPR_DTB_PTE: 352 { 353 TheISA::PTE &pte = cpu->dtb->index(1); 354 355 retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; 356 retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; 357 retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; 358 retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; 359 retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; 360 retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; 361 retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; 362 } 363 break; 364 365 // write only registers 366 case TheISA::IPR_HWINT_CLR: 367 case TheISA::IPR_SL_XMIT: 368 case TheISA::IPR_DC_FLUSH: 369 case TheISA::IPR_IC_FLUSH: 370 case TheISA::IPR_ALT_MODE: 371 case TheISA::IPR_DTB_IA: 372 case TheISA::IPR_DTB_IAP: 373 case TheISA::IPR_ITB_IA: 374 case TheISA::IPR_ITB_IAP: 375 fault = new UnimplementedOpcodeFault; 376 break; 377 378 default: 379 // invalid IPR 380 fault = new UnimplementedOpcodeFault; 381 break; 382 } 383 384 return retval; 385} 386 387extern int break_ipl; 388 389template <class Impl> 390Fault 391PhysRegFile<Impl>::setIpr(int idx, uint64_t val) 392{ 393 uint64_t old; 394 395 switch (idx) { 396 case TheISA::IPR_PALtemp0: 397 case TheISA::IPR_PALtemp1: 398 case TheISA::IPR_PALtemp2: 399 case TheISA::IPR_PALtemp3: 400 case TheISA::IPR_PALtemp4: 401 case TheISA::IPR_PALtemp5: 402 case TheISA::IPR_PALtemp6: 403 case TheISA::IPR_PALtemp7: 404 case TheISA::IPR_PALtemp8: 405 case TheISA::IPR_PALtemp9: 406 case TheISA::IPR_PALtemp10: 407 case TheISA::IPR_PALtemp11: 408 case TheISA::IPR_PALtemp12: 409 case TheISA::IPR_PALtemp13: 410 case TheISA::IPR_PALtemp14: 411 case TheISA::IPR_PALtemp15: 412 case TheISA::IPR_PALtemp16: 413 case TheISA::IPR_PALtemp17: 414 case TheISA::IPR_PALtemp18: 415 case TheISA::IPR_PALtemp19: 416 case TheISA::IPR_PALtemp20: 417 case TheISA::IPR_PALtemp21: 418 case TheISA::IPR_PALtemp22: 419 case TheISA::IPR_PAL_BASE: 420 case TheISA::IPR_IC_PERR_STAT: 421 case TheISA::IPR_DC_PERR_STAT: 422 case TheISA::IPR_PMCTR: 423 // write entire quad w/ no side-effect 424 ipr[idx] = val; 425 break; 426 427 case TheISA::IPR_CC_CTL: 428 // This IPR resets the cycle counter. We assume this only 429 // happens once... let's verify that. 430 assert(ipr[idx] == 0); 431 ipr[idx] = 1; 432 break; 433 434 case TheISA::IPR_CC: 435 // This IPR only writes the upper 64 bits. It's ok to write 436 // all 64 here since we mask out the lower 32 in rpcc (see 437 // isa_desc). 438 ipr[idx] = val; 439 break; 440 441 case TheISA::IPR_PALtemp23: 442 // write entire quad w/ no side-effect 443 old = ipr[idx]; 444 ipr[idx] = val; 445 break; 446 447 case TheISA::IPR_DTB_PTE: 448 // write entire quad w/ no side-effect, tag is forthcoming 449 ipr[idx] = val; 450 break; 451 452 case TheISA::IPR_EXC_ADDR: 453 // second least significant bit in PC is always zero 454 ipr[idx] = val & ~2; 455 break; 456 457 case TheISA::IPR_ASTRR: 458 case TheISA::IPR_ASTER: 459 // only write least significant four bits - privilege mask 460 ipr[idx] = val & 0xf; 461 break; 462 463 case TheISA::IPR_IPLR: 464 // only write least significant five bits - interrupt level 465 ipr[idx] = val & 0x1f; 466 break; 467 468 case TheISA::IPR_DTB_CM: 469 470 case TheISA::IPR_ICM: 471 // only write two mode bits - processor mode 472 ipr[idx] = val & 0x18; 473 break; 474 475 case TheISA::IPR_ALT_MODE: 476 // only write two mode bits - processor mode 477 ipr[idx] = val & 0x18; 478 break; 479 480 case TheISA::IPR_MCSR: 481 // more here after optimization... 482 ipr[idx] = val; 483 break; 484 485 case TheISA::IPR_SIRR: 486 // only write software interrupt mask 487 ipr[idx] = val & 0x7fff0; 488 break; 489 490 case TheISA::IPR_ICSR: 491 ipr[idx] = val & ULL(0xffffff0300); 492 break; 493 494 case TheISA::IPR_IVPTBR: 495 case TheISA::IPR_MVPTBR: 496 ipr[idx] = val & ULL(0xffffffffc0000000); 497 break; 498 499 case TheISA::IPR_DC_TEST_CTL: 500 ipr[idx] = val & 0x1ffb; 501 break; 502 503 case TheISA::IPR_DC_MODE: 504 case TheISA::IPR_MAF_MODE: 505 ipr[idx] = val & 0x3f; 506 break; 507 508 case TheISA::IPR_ITB_ASN: 509 ipr[idx] = val & 0x7f0; 510 break; 511 512 case TheISA::IPR_DTB_ASN: 513 ipr[idx] = val & ULL(0xfe00000000000000); 514 break; 515 516 case TheISA::IPR_EXC_SUM: 517 case TheISA::IPR_EXC_MASK: 518 // any write to this register clears it 519 ipr[idx] = 0; 520 break; 521 522 case TheISA::IPR_INTID: 523 case TheISA::IPR_SL_RCV: 524 case TheISA::IPR_MM_STAT: 525 case TheISA::IPR_ITB_PTE_TEMP: 526 case TheISA::IPR_DTB_PTE_TEMP: 527 // read-only registers 528 return new UnimplementedOpcodeFault; 529 530 case TheISA::IPR_HWINT_CLR: 531 case TheISA::IPR_SL_XMIT: 532 case TheISA::IPR_DC_FLUSH: 533 case TheISA::IPR_IC_FLUSH: 534 // the following are write only 535 ipr[idx] = val; 536 break; 537 538 case TheISA::IPR_DTB_IA: 539 // really a control write 540 ipr[idx] = 0; 541 542 cpu->dtb->flushAll(); 543 break; 544 545 case TheISA::IPR_DTB_IAP: 546 // really a control write 547 ipr[idx] = 0; 548 549 cpu->dtb->flushProcesses(); 550 break; 551 552 case TheISA::IPR_DTB_IS: 553 // really a control write 554 ipr[idx] = val; 555 556 cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN])); 557 break; 558 559 case TheISA::IPR_DTB_TAG: { 560 struct TheISA::PTE pte; 561 562 // FIXME: granularity hints NYI... 563 if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0) 564 panic("PTE GH field != 0"); 565 566 // write entire quad 567 ipr[idx] = val; 568 569 // construct PTE for new entry 570 pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]); 571 pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]); 572 pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]); 573 pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]); 574 pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]); 575 pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]); 576 pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]); 577 578 // insert new TAG/PTE value into data TLB 579 cpu->dtb->insert(val, pte); 580 } 581 break; 582 583 case TheISA::IPR_ITB_PTE: { 584 struct TheISA::PTE pte; 585 586 // FIXME: granularity hints NYI... 587 if (ITB_PTE_GH(val) != 0) 588 panic("PTE GH field != 0"); 589 590 // write entire quad 591 ipr[idx] = val; 592 593 // construct PTE for new entry 594 pte.ppn = ITB_PTE_PPN(val); 595 pte.xre = ITB_PTE_XRE(val); 596 pte.xwe = 0; 597 pte.fonr = ITB_PTE_FONR(val); 598 pte.fonw = ITB_PTE_FONW(val); 599 pte.asma = ITB_PTE_ASMA(val); 600 pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]); 601 602 // insert new TAG/PTE value into data TLB 603 cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte); 604 } 605 break; 606 607 case TheISA::IPR_ITB_IA: 608 // really a control write 609 ipr[idx] = 0; 610 611 cpu->itb->flushAll(); 612 break; 613 614 case TheISA::IPR_ITB_IAP: 615 // really a control write 616 ipr[idx] = 0; 617 618 cpu->itb->flushProcesses(); 619 break; 620 621 case TheISA::IPR_ITB_IS: 622 // really a control write 623 ipr[idx] = val; 624 625 cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN])); 626 break; 627 628 default: 629 // invalid IPR 630 return new UnimplementedOpcodeFault; 631 } 632 633 // no error... 634 return NoFault; 635} 636 637#endif // #if FULL_SYSTEM 638 639#endif // __CPU_O3_CPU_REGFILE_HH__ 640