regfile.hh revision 2107 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_O3_CPU_REGFILE_HH__
30#define __CPU_O3_CPU_REGFILE_HH__
31
32// @todo: Destructor
33
34#include "arch/alpha/isa_traits.hh"
35#include "arch/alpha/faults.hh"
36#include "base/trace.hh"
37#include "config/full_system.hh"
38#include "cpu/o3/comm.hh"
39
40#if FULL_SYSTEM
41#include "arch/alpha/ev5.hh"
42#include "kern/kernel_stats.hh"
43
44using namespace EV5;
45#endif
46
47// This really only depends on the ISA, and not the Impl.  It might be nicer
48// to see if I can make it depend on nothing...
49// Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA,
50// and should go in the AlphaFullCPU.
51
52template <class Impl>
53class PhysRegFile
54{
55  protected:
56    typedef TheISA::Addr Addr;
57    typedef TheISA::IntReg IntReg;
58    typedef TheISA::FloatReg FloatReg;
59    typedef TheISA::MiscRegFile MiscRegFile;
60    //Note that most of the definitions of the IntReg, FloatReg, etc. exist
61    //within the Impl/ISA class and not within this PhysRegFile class.
62
63    //Will need some way to allow stuff like swap_palshadow to access the
64    //correct registers.  Might require code changes to swap_palshadow and
65    //other execution contexts.
66
67    //Will make these registers public for now, but they probably should
68    //be private eventually with some accessor functions.
69  public:
70    typedef typename Impl::FullCPU FullCPU;
71
72    PhysRegFile(unsigned _numPhysicalIntRegs,
73                unsigned _numPhysicalFloatRegs);
74
75    //Everything below should be pretty well identical to the normal
76    //register file that exists within AlphaISA class.
77    //The duplication is unfortunate but it's better than having
78    //different ways to access certain registers.
79
80    //Add these in later when everything else is in place
81//    void serialize(std::ostream &os);
82//    void unserialize(Checkpoint *cp, const std::string &section);
83
84    uint64_t readIntReg(PhysRegIndex reg_idx)
85    {
86        assert(reg_idx < numPhysicalIntRegs);
87
88        DPRINTF(IEW, "RegFile: Access to int register %i, has data "
89                "%i\n", int(reg_idx), intRegFile[reg_idx]);
90        return intRegFile[reg_idx];
91    }
92
93    float readFloatRegSingle(PhysRegIndex reg_idx)
94    {
95        // Remove the base Float reg dependency.
96        reg_idx = reg_idx - numPhysicalIntRegs;
97
98        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
99
100        DPRINTF(IEW, "RegFile: Access to float register %i as single, has "
101                "data %8.8f\n", int(reg_idx), (float)floatRegFile[reg_idx].d);
102
103        return (float)floatRegFile[reg_idx].d;
104    }
105
106    double readFloatRegDouble(PhysRegIndex reg_idx)
107    {
108        // Remove the base Float reg dependency.
109        reg_idx = reg_idx - numPhysicalIntRegs;
110
111        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
112
113        DPRINTF(IEW, "RegFile: Access to float register %i as double, has "
114                " data %8.8f\n", int(reg_idx), floatRegFile[reg_idx].d);
115
116        return floatRegFile[reg_idx].d;
117    }
118
119    uint64_t readFloatRegInt(PhysRegIndex reg_idx)
120    {
121        // Remove the base Float reg dependency.
122        reg_idx = reg_idx - numPhysicalIntRegs;
123
124        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
125
126        DPRINTF(IEW, "RegFile: Access to float register %i as int, has data "
127                "%lli\n", int(reg_idx), floatRegFile[reg_idx].q);
128
129        return floatRegFile[reg_idx].q;
130    }
131
132    void setIntReg(PhysRegIndex reg_idx, uint64_t val)
133    {
134        assert(reg_idx < numPhysicalIntRegs);
135
136        DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n",
137                int(reg_idx), val);
138
139        intRegFile[reg_idx] = val;
140    }
141
142    void setFloatRegSingle(PhysRegIndex reg_idx, float val)
143    {
144        // Remove the base Float reg dependency.
145        reg_idx = reg_idx - numPhysicalIntRegs;
146
147        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
148
149        DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n",
150                int(reg_idx), val);
151
152        floatRegFile[reg_idx].d = (double)val;
153    }
154
155    void setFloatRegDouble(PhysRegIndex reg_idx, double val)
156    {
157        // Remove the base Float reg dependency.
158        reg_idx = reg_idx - numPhysicalIntRegs;
159
160        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
161
162        DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n",
163                int(reg_idx), val);
164
165        floatRegFile[reg_idx].d = val;
166    }
167
168    void setFloatRegInt(PhysRegIndex reg_idx, uint64_t val)
169    {
170        // Remove the base Float reg dependency.
171        reg_idx = reg_idx - numPhysicalIntRegs;
172
173        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
174
175        DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
176                int(reg_idx), val);
177
178        floatRegFile[reg_idx].q = val;
179    }
180
181    uint64_t readPC()
182    {
183        return pc;
184    }
185
186    void setPC(uint64_t val)
187    {
188        pc = val;
189    }
190
191    void setNextPC(uint64_t val)
192    {
193        npc = val;
194    }
195
196    //Consider leaving this stuff and below in some implementation specific
197    //file as opposed to the general register file.  Or have a derived class.
198    uint64_t readUniq()
199    {
200        return miscRegs.uniq;
201    }
202
203    void setUniq(uint64_t val)
204    {
205        miscRegs.uniq = val;
206    }
207
208    uint64_t readFpcr()
209    {
210        return miscRegs.fpcr;
211    }
212
213    void setFpcr(uint64_t val)
214    {
215        miscRegs.fpcr = val;
216    }
217
218#if FULL_SYSTEM
219    uint64_t readIpr(int idx, Fault * &fault);
220    Fault * setIpr(int idx, uint64_t val);
221    InternalProcReg *getIpr() { return ipr; }
222    int readIntrFlag() { return intrflag; }
223    void setIntrFlag(int val) { intrflag = val; }
224#endif
225
226    // These should be private eventually, but will be public for now
227    // so that I can hack around the initregs issue.
228  public:
229    /** (signed) integer register file. */
230    IntReg *intRegFile;
231
232    /** Floating point register file. */
233    FloatReg *floatRegFile;
234
235    /** Miscellaneous register file. */
236    MiscRegFile miscRegs;
237
238    /** Program counter. */
239    Addr pc;
240
241    /** Next-cycle program counter. */
242    Addr npc;
243
244#if FULL_SYSTEM
245  private:
246    // This is ISA specifc stuff; remove it eventually once ISAImpl is used
247    IntReg palregs[NumIntRegs];	// PAL shadow registers
248    InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
249    int intrflag;			// interrupt flag
250    bool pal_shadow;		// using pal_shadow registers
251#endif
252
253  private:
254    FullCPU *cpu;
255
256  public:
257    void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; }
258
259    unsigned numPhysicalIntRegs;
260    unsigned numPhysicalFloatRegs;
261};
262
263template <class Impl>
264PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
265                               unsigned _numPhysicalFloatRegs)
266    : numPhysicalIntRegs(_numPhysicalIntRegs),
267      numPhysicalFloatRegs(_numPhysicalFloatRegs)
268{
269    intRegFile = new IntReg[numPhysicalIntRegs];
270    floatRegFile = new FloatReg[numPhysicalFloatRegs];
271
272    memset(intRegFile, 0, sizeof(*intRegFile));
273    memset(floatRegFile, 0, sizeof(*floatRegFile));
274}
275
276#if FULL_SYSTEM
277
278//Problem:  This code doesn't make sense at the RegFile level because it
279//needs things such as the itb and dtb.  Either put it at the CPU level or
280//the DynInst level.
281template <class Impl>
282uint64_t
283PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
284{
285    uint64_t retval = 0;    // return value, default 0
286
287    switch (idx) {
288      case TheISA::IPR_PALtemp0:
289      case TheISA::IPR_PALtemp1:
290      case TheISA::IPR_PALtemp2:
291      case TheISA::IPR_PALtemp3:
292      case TheISA::IPR_PALtemp4:
293      case TheISA::IPR_PALtemp5:
294      case TheISA::IPR_PALtemp6:
295      case TheISA::IPR_PALtemp7:
296      case TheISA::IPR_PALtemp8:
297      case TheISA::IPR_PALtemp9:
298      case TheISA::IPR_PALtemp10:
299      case TheISA::IPR_PALtemp11:
300      case TheISA::IPR_PALtemp12:
301      case TheISA::IPR_PALtemp13:
302      case TheISA::IPR_PALtemp14:
303      case TheISA::IPR_PALtemp15:
304      case TheISA::IPR_PALtemp16:
305      case TheISA::IPR_PALtemp17:
306      case TheISA::IPR_PALtemp18:
307      case TheISA::IPR_PALtemp19:
308      case TheISA::IPR_PALtemp20:
309      case TheISA::IPR_PALtemp21:
310      case TheISA::IPR_PALtemp22:
311      case TheISA::IPR_PALtemp23:
312      case TheISA::IPR_PAL_BASE:
313
314      case TheISA::IPR_IVPTBR:
315      case TheISA::IPR_DC_MODE:
316      case TheISA::IPR_MAF_MODE:
317      case TheISA::IPR_ISR:
318      case TheISA::IPR_EXC_ADDR:
319      case TheISA::IPR_IC_PERR_STAT:
320      case TheISA::IPR_DC_PERR_STAT:
321      case TheISA::IPR_MCSR:
322      case TheISA::IPR_ASTRR:
323      case TheISA::IPR_ASTER:
324      case TheISA::IPR_SIRR:
325      case TheISA::IPR_ICSR:
326      case TheISA::IPR_ICM:
327      case TheISA::IPR_DTB_CM:
328      case TheISA::IPR_IPLR:
329      case TheISA::IPR_INTID:
330      case TheISA::IPR_PMCTR:
331        // no side-effect
332        retval = ipr[idx];
333        break;
334
335      case TheISA::IPR_CC:
336        retval |= ipr[idx] & ULL(0xffffffff00000000);
337        retval |= curTick  & ULL(0x00000000ffffffff);
338        break;
339
340      case TheISA::IPR_VA:
341        retval = ipr[idx];
342        break;
343
344      case TheISA::IPR_VA_FORM:
345      case TheISA::IPR_MM_STAT:
346      case TheISA::IPR_IFAULT_VA_FORM:
347      case TheISA::IPR_EXC_MASK:
348      case TheISA::IPR_EXC_SUM:
349        retval = ipr[idx];
350        break;
351
352      case TheISA::IPR_DTB_PTE:
353        {
354            TheISA::PTE &pte = cpu->dtb->index(1);
355
356            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
357            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
358            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
359            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
360            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
361            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
362            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
363        }
364        break;
365
366        // write only registers
367      case TheISA::IPR_HWINT_CLR:
368      case TheISA::IPR_SL_XMIT:
369      case TheISA::IPR_DC_FLUSH:
370      case TheISA::IPR_IC_FLUSH:
371      case TheISA::IPR_ALT_MODE:
372      case TheISA::IPR_DTB_IA:
373      case TheISA::IPR_DTB_IAP:
374      case TheISA::IPR_ITB_IA:
375      case TheISA::IPR_ITB_IAP:
376        fault = UnimplementedOpcodeFault;
377        break;
378
379      default:
380        // invalid IPR
381        fault = UnimplementedOpcodeFault;
382        break;
383    }
384
385    return retval;
386}
387
388extern int break_ipl;
389
390template <class Impl>
391Fault *
392PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
393{
394    uint64_t old;
395
396    switch (idx) {
397      case TheISA::IPR_PALtemp0:
398      case TheISA::IPR_PALtemp1:
399      case TheISA::IPR_PALtemp2:
400      case TheISA::IPR_PALtemp3:
401      case TheISA::IPR_PALtemp4:
402      case TheISA::IPR_PALtemp5:
403      case TheISA::IPR_PALtemp6:
404      case TheISA::IPR_PALtemp7:
405      case TheISA::IPR_PALtemp8:
406      case TheISA::IPR_PALtemp9:
407      case TheISA::IPR_PALtemp10:
408      case TheISA::IPR_PALtemp11:
409      case TheISA::IPR_PALtemp12:
410      case TheISA::IPR_PALtemp13:
411      case TheISA::IPR_PALtemp14:
412      case TheISA::IPR_PALtemp15:
413      case TheISA::IPR_PALtemp16:
414      case TheISA::IPR_PALtemp17:
415      case TheISA::IPR_PALtemp18:
416      case TheISA::IPR_PALtemp19:
417      case TheISA::IPR_PALtemp20:
418      case TheISA::IPR_PALtemp21:
419      case TheISA::IPR_PALtemp22:
420      case TheISA::IPR_PAL_BASE:
421      case TheISA::IPR_IC_PERR_STAT:
422      case TheISA::IPR_DC_PERR_STAT:
423      case TheISA::IPR_PMCTR:
424        // write entire quad w/ no side-effect
425        ipr[idx] = val;
426        break;
427
428      case TheISA::IPR_CC_CTL:
429        // This IPR resets the cycle counter.  We assume this only
430        // happens once... let's verify that.
431        assert(ipr[idx] == 0);
432        ipr[idx] = 1;
433        break;
434
435      case TheISA::IPR_CC:
436        // This IPR only writes the upper 64 bits.  It's ok to write
437        // all 64 here since we mask out the lower 32 in rpcc (see
438        // isa_desc).
439        ipr[idx] = val;
440        break;
441
442      case TheISA::IPR_PALtemp23:
443        // write entire quad w/ no side-effect
444        old = ipr[idx];
445        ipr[idx] = val;
446        break;
447
448      case TheISA::IPR_DTB_PTE:
449        // write entire quad w/ no side-effect, tag is forthcoming
450        ipr[idx] = val;
451        break;
452
453      case TheISA::IPR_EXC_ADDR:
454        // second least significant bit in PC is always zero
455        ipr[idx] = val & ~2;
456        break;
457
458      case TheISA::IPR_ASTRR:
459      case TheISA::IPR_ASTER:
460        // only write least significant four bits - privilege mask
461        ipr[idx] = val & 0xf;
462        break;
463
464      case TheISA::IPR_IPLR:
465        // only write least significant five bits - interrupt level
466        ipr[idx] = val & 0x1f;
467        break;
468
469      case TheISA::IPR_DTB_CM:
470
471      case TheISA::IPR_ICM:
472        // only write two mode bits - processor mode
473        ipr[idx] = val & 0x18;
474        break;
475
476      case TheISA::IPR_ALT_MODE:
477        // only write two mode bits - processor mode
478        ipr[idx] = val & 0x18;
479        break;
480
481      case TheISA::IPR_MCSR:
482        // more here after optimization...
483        ipr[idx] = val;
484        break;
485
486      case TheISA::IPR_SIRR:
487        // only write software interrupt mask
488        ipr[idx] = val & 0x7fff0;
489        break;
490
491      case TheISA::IPR_ICSR:
492        ipr[idx] = val & ULL(0xffffff0300);
493        break;
494
495      case TheISA::IPR_IVPTBR:
496      case TheISA::IPR_MVPTBR:
497        ipr[idx] = val & ULL(0xffffffffc0000000);
498        break;
499
500      case TheISA::IPR_DC_TEST_CTL:
501        ipr[idx] = val & 0x1ffb;
502        break;
503
504      case TheISA::IPR_DC_MODE:
505      case TheISA::IPR_MAF_MODE:
506        ipr[idx] = val & 0x3f;
507        break;
508
509      case TheISA::IPR_ITB_ASN:
510        ipr[idx] = val & 0x7f0;
511        break;
512
513      case TheISA::IPR_DTB_ASN:
514        ipr[idx] = val & ULL(0xfe00000000000000);
515        break;
516
517      case TheISA::IPR_EXC_SUM:
518      case TheISA::IPR_EXC_MASK:
519        // any write to this register clears it
520        ipr[idx] = 0;
521        break;
522
523      case TheISA::IPR_INTID:
524      case TheISA::IPR_SL_RCV:
525      case TheISA::IPR_MM_STAT:
526      case TheISA::IPR_ITB_PTE_TEMP:
527      case TheISA::IPR_DTB_PTE_TEMP:
528        // read-only registers
529        return UnimplementedOpcodeFault;
530
531      case TheISA::IPR_HWINT_CLR:
532      case TheISA::IPR_SL_XMIT:
533      case TheISA::IPR_DC_FLUSH:
534      case TheISA::IPR_IC_FLUSH:
535        // the following are write only
536        ipr[idx] = val;
537        break;
538
539      case TheISA::IPR_DTB_IA:
540        // really a control write
541        ipr[idx] = 0;
542
543        cpu->dtb->flushAll();
544        break;
545
546      case TheISA::IPR_DTB_IAP:
547        // really a control write
548        ipr[idx] = 0;
549
550        cpu->dtb->flushProcesses();
551        break;
552
553      case TheISA::IPR_DTB_IS:
554        // really a control write
555        ipr[idx] = val;
556
557        cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]));
558        break;
559
560      case TheISA::IPR_DTB_TAG: {
561          struct TheISA::PTE pte;
562
563          // FIXME: granularity hints NYI...
564          if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0)
565              panic("PTE GH field != 0");
566
567          // write entire quad
568          ipr[idx] = val;
569
570          // construct PTE for new entry
571          pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]);
572          pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]);
573          pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]);
574          pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]);
575          pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]);
576          pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]);
577          pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]);
578
579          // insert new TAG/PTE value into data TLB
580          cpu->dtb->insert(val, pte);
581      }
582        break;
583
584      case TheISA::IPR_ITB_PTE: {
585          struct TheISA::PTE pte;
586
587          // FIXME: granularity hints NYI...
588          if (ITB_PTE_GH(val) != 0)
589              panic("PTE GH field != 0");
590
591          // write entire quad
592          ipr[idx] = val;
593
594          // construct PTE for new entry
595          pte.ppn = ITB_PTE_PPN(val);
596          pte.xre = ITB_PTE_XRE(val);
597          pte.xwe = 0;
598          pte.fonr = ITB_PTE_FONR(val);
599          pte.fonw = ITB_PTE_FONW(val);
600          pte.asma = ITB_PTE_ASMA(val);
601          pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]);
602
603          // insert new TAG/PTE value into data TLB
604          cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte);
605      }
606        break;
607
608      case TheISA::IPR_ITB_IA:
609        // really a control write
610        ipr[idx] = 0;
611
612        cpu->itb->flushAll();
613        break;
614
615      case TheISA::IPR_ITB_IAP:
616        // really a control write
617        ipr[idx] = 0;
618
619        cpu->itb->flushProcesses();
620        break;
621
622      case TheISA::IPR_ITB_IS:
623        // really a control write
624        ipr[idx] = val;
625
626        cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]));
627        break;
628
629      default:
630        // invalid IPR
631        return UnimplementedOpcodeFault;
632    }
633
634    // no error...
635    return NoFault;
636}
637
638#endif // #if FULL_SYSTEM
639
640#endif // __CPU_O3_CPU_REGFILE_HH__
641