regfile.hh revision 1717
12SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#ifndef __CPU_BETA_CPU_REGFILE_HH__ 302665Ssaidi@eecs.umich.edu#define __CPU_BETA_CPU_REGFILE_HH__ 312665Ssaidi@eecs.umich.edu 322SN/A// @todo: Destructor 332SN/A 344265Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 352SN/A#include "base/trace.hh" 362SN/A#include "cpu/o3/comm.hh" 373506Ssaidi@eecs.umich.edu 383506Ssaidi@eecs.umich.edu#ifdef FULL_SYSTEM 392SN/A#include "arch/alpha/ev5.hh" 404266Sgblack@eecs.umich.edu#include "kern/kernel_stats.hh" 412973Sgblack@eecs.umich.edu 423584Ssaidi@eecs.umich.eduusing namespace EV5; 4356SN/A#endif 444265Sgblack@eecs.umich.edu 453614Sgblack@eecs.umich.edu// This really only depends on the ISA, and not the Impl. It might be nicer 461717SN/A// to see if I can make it depend on nothing... 472518SN/A// Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA, 4856SN/A// and should go in the AlphaFullCPU. 494762Snate@binkert.org 502518SN/Atemplate <class Impl> 512SN/Aclass PhysRegFile 523614Sgblack@eecs.umich.edu{ 533614Sgblack@eecs.umich.edu //Note that most of the definitions of the IntReg, FloatReg, etc. exist 543614Sgblack@eecs.umich.edu //within the Impl/ISA class and not within this PhysRegFile class. 553614Sgblack@eecs.umich.edu 563065Sgblack@eecs.umich.edu //Will need some way to allow stuff like swap_palshadow to access the 573065Sgblack@eecs.umich.edu //correct registers. Might require code changes to swap_palshadow and 583506Ssaidi@eecs.umich.edu //other execution contexts. 593065Sgblack@eecs.umich.edu 602SN/A //Will make these registers public for now, but they probably should 612973Sgblack@eecs.umich.edu //be private eventually with some accessor functions. 622SN/A public: 633840Shsul@eecs.umich.edu typedef typename Impl::ISA ISA; 643825Ssaidi@eecs.umich.edu typedef typename Impl::FullCPU FullCPU; 653903Ssaidi@eecs.umich.edu 663840Shsul@eecs.umich.edu PhysRegFile(unsigned _numPhysicalIntRegs, 673825Ssaidi@eecs.umich.edu unsigned _numPhysicalFloatRegs); 683506Ssaidi@eecs.umich.edu 693506Ssaidi@eecs.umich.edu //Everything below should be pretty well identical to the normal 704265Sgblack@eecs.umich.edu //register file that exists within AlphaISA class. 714054Sbinkertn@umich.edu //The duplication is unfortunate but it's better than having 724054Sbinkertn@umich.edu //different ways to access certain registers. 734054Sbinkertn@umich.edu 744054Sbinkertn@umich.edu //Add these in later when everything else is in place 754054Sbinkertn@umich.edu// void serialize(std::ostream &os); 764054Sbinkertn@umich.edu// void unserialize(Checkpoint *cp, const std::string §ion); 774054Sbinkertn@umich.edu 784054Sbinkertn@umich.edu uint64_t readIntReg(PhysRegIndex reg_idx) 794054Sbinkertn@umich.edu { 804054Sbinkertn@umich.edu assert(reg_idx < numPhysicalIntRegs); 814054Sbinkertn@umich.edu 824054Sbinkertn@umich.edu DPRINTF(IEW, "RegFile: Access to int register %i, has data " 834054Sbinkertn@umich.edu "%i\n", int(reg_idx), intRegFile[reg_idx]); 844054Sbinkertn@umich.edu return intRegFile[reg_idx]; 854054Sbinkertn@umich.edu } 864054Sbinkertn@umich.edu 874054Sbinkertn@umich.edu float readFloatRegSingle(PhysRegIndex reg_idx) 884054Sbinkertn@umich.edu { 894054Sbinkertn@umich.edu // Remove the base Float reg dependency. 904054Sbinkertn@umich.edu reg_idx = reg_idx - numPhysicalIntRegs; 914054Sbinkertn@umich.edu 923506Ssaidi@eecs.umich.edu assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 933506Ssaidi@eecs.umich.edu 942SN/A DPRINTF(IEW, "RegFile: Access to float register %i as single, has " 952SN/A "data %8.8f\n", int(reg_idx), (float)floatRegFile[reg_idx].d); 962SN/A 972SN/A return (float)floatRegFile[reg_idx].d; 982SN/A } 993748Sgblack@eecs.umich.edu 1003748Sgblack@eecs.umich.edu double readFloatRegDouble(PhysRegIndex reg_idx) 1013748Sgblack@eecs.umich.edu { 1023748Sgblack@eecs.umich.edu // Remove the base Float reg dependency. 1033748Sgblack@eecs.umich.edu reg_idx = reg_idx - numPhysicalIntRegs; 1043748Sgblack@eecs.umich.edu 1053748Sgblack@eecs.umich.edu assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1063748Sgblack@eecs.umich.edu 1073748Sgblack@eecs.umich.edu DPRINTF(IEW, "RegFile: Access to float register %i as double, has " 1083748Sgblack@eecs.umich.edu " data %8.8f\n", int(reg_idx), floatRegFile[reg_idx].d); 1093748Sgblack@eecs.umich.edu 1103748Sgblack@eecs.umich.edu return floatRegFile[reg_idx].d; 1113748Sgblack@eecs.umich.edu } 1123748Sgblack@eecs.umich.edu 1133748Sgblack@eecs.umich.edu uint64_t readFloatRegInt(PhysRegIndex reg_idx) 1143748Sgblack@eecs.umich.edu { 1153748Sgblack@eecs.umich.edu // Remove the base Float reg dependency. 1163748Sgblack@eecs.umich.edu reg_idx = reg_idx - numPhysicalIntRegs; 1173748Sgblack@eecs.umich.edu 1183748Sgblack@eecs.umich.edu assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1193748Sgblack@eecs.umich.edu 1203748Sgblack@eecs.umich.edu DPRINTF(IEW, "RegFile: Access to float register %i as int, has data " 1213748Sgblack@eecs.umich.edu "%lli\n", int(reg_idx), floatRegFile[reg_idx].q); 1223748Sgblack@eecs.umich.edu 1233748Sgblack@eecs.umich.edu return floatRegFile[reg_idx].q; 1243748Sgblack@eecs.umich.edu } 1253748Sgblack@eecs.umich.edu 1263748Sgblack@eecs.umich.edu void setIntReg(PhysRegIndex reg_idx, uint64_t val) 1273748Sgblack@eecs.umich.edu { 1283748Sgblack@eecs.umich.edu assert(reg_idx < numPhysicalIntRegs); 1293748Sgblack@eecs.umich.edu 1303748Sgblack@eecs.umich.edu DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n", 1313748Sgblack@eecs.umich.edu int(reg_idx), val); 1323748Sgblack@eecs.umich.edu 1333748Sgblack@eecs.umich.edu intRegFile[reg_idx] = val; 1343748Sgblack@eecs.umich.edu } 1353748Sgblack@eecs.umich.edu 1363748Sgblack@eecs.umich.edu void setFloatRegSingle(PhysRegIndex reg_idx, float val) 1373748Sgblack@eecs.umich.edu { 1383748Sgblack@eecs.umich.edu // Remove the base Float reg dependency. 1393748Sgblack@eecs.umich.edu reg_idx = reg_idx - numPhysicalIntRegs; 1403748Sgblack@eecs.umich.edu 1413748Sgblack@eecs.umich.edu assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1423748Sgblack@eecs.umich.edu 1433748Sgblack@eecs.umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n", 1443748Sgblack@eecs.umich.edu int(reg_idx), val); 1453748Sgblack@eecs.umich.edu 1463748Sgblack@eecs.umich.edu floatRegFile[reg_idx].d = (double)val; 1473748Sgblack@eecs.umich.edu } 1483748Sgblack@eecs.umich.edu 1492SN/A void setFloatRegDouble(PhysRegIndex reg_idx, double val) 1502SN/A { 1514046Sbinkertn@umich.edu // Remove the base Float reg dependency. 1522SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1534046Sbinkertn@umich.edu 1544046Sbinkertn@umich.edu assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1553903Ssaidi@eecs.umich.edu 1564265Sgblack@eecs.umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n", 1574054Sbinkertn@umich.edu int(reg_idx), val); 1582973Sgblack@eecs.umich.edu 1594265Sgblack@eecs.umich.edu floatRegFile[reg_idx].d = val; 1604265Sgblack@eecs.umich.edu } 1613065Sgblack@eecs.umich.edu 1624265Sgblack@eecs.umich.edu void setFloatRegInt(PhysRegIndex reg_idx, uint64_t val) 1634265Sgblack@eecs.umich.edu { 1644265Sgblack@eecs.umich.edu // Remove the base Float reg dependency. 1654539Sgblack@eecs.umich.edu reg_idx = reg_idx - numPhysicalIntRegs; 1664265Sgblack@eecs.umich.edu 1674265Sgblack@eecs.umich.edu assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1684265Sgblack@eecs.umich.edu 1694265Sgblack@eecs.umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 1704265Sgblack@eecs.umich.edu int(reg_idx), val); 1714265Sgblack@eecs.umich.edu 1724265Sgblack@eecs.umich.edu floatRegFile[reg_idx].q = val; 1734265Sgblack@eecs.umich.edu } 1744265Sgblack@eecs.umich.edu 1754265Sgblack@eecs.umich.edu uint64_t readPC() 1764265Sgblack@eecs.umich.edu { 1774265Sgblack@eecs.umich.edu return pc; 1784265Sgblack@eecs.umich.edu } 1794265Sgblack@eecs.umich.edu 1804265Sgblack@eecs.umich.edu void setPC(uint64_t val) 1814265Sgblack@eecs.umich.edu { 1824265Sgblack@eecs.umich.edu pc = val; 1834265Sgblack@eecs.umich.edu } 1844265Sgblack@eecs.umich.edu 1854265Sgblack@eecs.umich.edu void setNextPC(uint64_t val) 1864265Sgblack@eecs.umich.edu { 1874265Sgblack@eecs.umich.edu npc = val; 1884265Sgblack@eecs.umich.edu } 1894265Sgblack@eecs.umich.edu 1904265Sgblack@eecs.umich.edu //Consider leaving this stuff and below in some implementation specific 1914265Sgblack@eecs.umich.edu //file as opposed to the general register file. Or have a derived class. 1924265Sgblack@eecs.umich.edu uint64_t readUniq() 1934265Sgblack@eecs.umich.edu { 1944265Sgblack@eecs.umich.edu return miscRegs.uniq; 1954265Sgblack@eecs.umich.edu } 1964265Sgblack@eecs.umich.edu 1974265Sgblack@eecs.umich.edu void setUniq(uint64_t val) 1984265Sgblack@eecs.umich.edu { 1994265Sgblack@eecs.umich.edu miscRegs.uniq = val; 2004265Sgblack@eecs.umich.edu } 2014265Sgblack@eecs.umich.edu 2024265Sgblack@eecs.umich.edu uint64_t readFpcr() 2034265Sgblack@eecs.umich.edu { 2044265Sgblack@eecs.umich.edu return miscRegs.fpcr; 2054265Sgblack@eecs.umich.edu } 2064265Sgblack@eecs.umich.edu 2074265Sgblack@eecs.umich.edu void setFpcr(uint64_t val) 2084265Sgblack@eecs.umich.edu { 2094265Sgblack@eecs.umich.edu miscRegs.fpcr = val; 2104265Sgblack@eecs.umich.edu } 2114265Sgblack@eecs.umich.edu 2124265Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 2134265Sgblack@eecs.umich.edu uint64_t readIpr(int idx, Fault &fault); 2144265Sgblack@eecs.umich.edu Fault setIpr(int idx, uint64_t val); 2154265Sgblack@eecs.umich.edu InternalProcReg *getIpr() { return ipr; } 2164265Sgblack@eecs.umich.edu int readIntrFlag() { return intrflag; } 2174265Sgblack@eecs.umich.edu void setIntrFlag(int val) { intrflag = val; } 2184265Sgblack@eecs.umich.edu#endif 2194265Sgblack@eecs.umich.edu 2204265Sgblack@eecs.umich.edu // These should be private eventually, but will be public for now 2214265Sgblack@eecs.umich.edu // so that I can hack around the initregs issue. 2224265Sgblack@eecs.umich.edu public: 2234265Sgblack@eecs.umich.edu /** (signed) integer register file. */ 2244265Sgblack@eecs.umich.edu IntReg *intRegFile; 2254265Sgblack@eecs.umich.edu 2264265Sgblack@eecs.umich.edu /** Floating point register file. */ 2274265Sgblack@eecs.umich.edu FloatReg *floatRegFile; 2284265Sgblack@eecs.umich.edu 2294265Sgblack@eecs.umich.edu /** Miscellaneous register file. */ 2304265Sgblack@eecs.umich.edu MiscRegFile miscRegs; 2314265Sgblack@eecs.umich.edu 2324265Sgblack@eecs.umich.edu /** Program counter. */ 2334265Sgblack@eecs.umich.edu Addr pc; 2344265Sgblack@eecs.umich.edu 2354265Sgblack@eecs.umich.edu /** Next-cycle program counter. */ 2364265Sgblack@eecs.umich.edu Addr npc; 2374265Sgblack@eecs.umich.edu 2384265Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 2394265Sgblack@eecs.umich.edu private: 2404265Sgblack@eecs.umich.edu // This is ISA specifc stuff; remove it eventually once ISAImpl is used 2414265Sgblack@eecs.umich.edu IntReg palregs[NumIntRegs]; // PAL shadow registers 2424265Sgblack@eecs.umich.edu InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs 2434265Sgblack@eecs.umich.edu int intrflag; // interrupt flag 2444265Sgblack@eecs.umich.edu bool pal_shadow; // using pal_shadow registers 2454265Sgblack@eecs.umich.edu#endif 2463380Sgblack@eecs.umich.edu 2473380Sgblack@eecs.umich.edu private: 2484539Sgblack@eecs.umich.edu FullCPU *cpu; 2493380Sgblack@eecs.umich.edu 2503380Sgblack@eecs.umich.edu public: 2513380Sgblack@eecs.umich.edu void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } 2523380Sgblack@eecs.umich.edu 2533380Sgblack@eecs.umich.edu unsigned numPhysicalIntRegs; 2543380Sgblack@eecs.umich.edu unsigned numPhysicalFloatRegs; 2553380Sgblack@eecs.umich.edu}; 2563380Sgblack@eecs.umich.edu 2573380Sgblack@eecs.umich.edutemplate <class Impl> 2583380Sgblack@eecs.umich.eduPhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, 2593380Sgblack@eecs.umich.edu unsigned _numPhysicalFloatRegs) 2603065Sgblack@eecs.umich.edu : numPhysicalIntRegs(_numPhysicalIntRegs), 2613588Sgblack@eecs.umich.edu numPhysicalFloatRegs(_numPhysicalFloatRegs) 2623588Sgblack@eecs.umich.edu{ 2633588Sgblack@eecs.umich.edu intRegFile = new IntReg[numPhysicalIntRegs]; 2643790Sgblack@eecs.umich.edu floatRegFile = new FloatReg[numPhysicalFloatRegs]; 2654172Ssaidi@eecs.umich.edu 2663380Sgblack@eecs.umich.edu memset(intRegFile, 0, sizeof(*intRegFile)); 2673059Sgblack@eecs.umich.edu memset(floatRegFile, 0, sizeof(*floatRegFile)); 2683588Sgblack@eecs.umich.edu} 2693380Sgblack@eecs.umich.edu 2703380Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 2713790Sgblack@eecs.umich.edu 2724172Ssaidi@eecs.umich.edu//Problem: This code doesn't make sense at the RegFile level because it 2733380Sgblack@eecs.umich.edu//needs things such as the itb and dtb. Either put it at the CPU level or 2743380Sgblack@eecs.umich.edu//the DynInst level. 2753588Sgblack@eecs.umich.edutemplate <class Impl> 2763380Sgblack@eecs.umich.eduuint64_t 2773380Sgblack@eecs.umich.eduPhysRegFile<Impl>::readIpr(int idx, Fault &fault) 2783380Sgblack@eecs.umich.edu{ 2793380Sgblack@eecs.umich.edu uint64_t retval = 0; // return value, default 0 2803380Sgblack@eecs.umich.edu 2813059Sgblack@eecs.umich.edu switch (idx) { 2823380Sgblack@eecs.umich.edu case ISA::IPR_PALtemp0: 2833380Sgblack@eecs.umich.edu case ISA::IPR_PALtemp1: 2843380Sgblack@eecs.umich.edu case ISA::IPR_PALtemp2: 2853380Sgblack@eecs.umich.edu case ISA::IPR_PALtemp3: 2863588Sgblack@eecs.umich.edu case ISA::IPR_PALtemp4: 2873380Sgblack@eecs.umich.edu case ISA::IPR_PALtemp5: 2883380Sgblack@eecs.umich.edu case ISA::IPR_PALtemp6: 2893059Sgblack@eecs.umich.edu case ISA::IPR_PALtemp7: 2903059Sgblack@eecs.umich.edu case ISA::IPR_PALtemp8: 2913380Sgblack@eecs.umich.edu case ISA::IPR_PALtemp9: 2923380Sgblack@eecs.umich.edu case ISA::IPR_PALtemp10: 2933380Sgblack@eecs.umich.edu case ISA::IPR_PALtemp11: 2943380Sgblack@eecs.umich.edu case ISA::IPR_PALtemp12: 2953380Sgblack@eecs.umich.edu case ISA::IPR_PALtemp13: 2963588Sgblack@eecs.umich.edu case ISA::IPR_PALtemp14: 2973380Sgblack@eecs.umich.edu case ISA::IPR_PALtemp15: 2983380Sgblack@eecs.umich.edu case ISA::IPR_PALtemp16: 2993380Sgblack@eecs.umich.edu case ISA::IPR_PALtemp17: 3003588Sgblack@eecs.umich.edu case ISA::IPR_PALtemp18: 3013059Sgblack@eecs.umich.edu case ISA::IPR_PALtemp19: 3023065Sgblack@eecs.umich.edu case ISA::IPR_PALtemp20: 3032973Sgblack@eecs.umich.edu case ISA::IPR_PALtemp21: 3044265Sgblack@eecs.umich.edu case ISA::IPR_PALtemp22: 3054265Sgblack@eecs.umich.edu case ISA::IPR_PALtemp23: 3064054Sbinkertn@umich.edu case ISA::IPR_PAL_BASE: 3074054Sbinkertn@umich.edu 3084054Sbinkertn@umich.edu case ISA::IPR_IVPTBR: 3094054Sbinkertn@umich.edu case ISA::IPR_DC_MODE: 3104054Sbinkertn@umich.edu case ISA::IPR_MAF_MODE: 3114054Sbinkertn@umich.edu case ISA::IPR_ISR: 3121904SN/A case ISA::IPR_EXC_ADDR: 3134054Sbinkertn@umich.edu case ISA::IPR_IC_PERR_STAT: 3141904SN/A case ISA::IPR_DC_PERR_STAT: 3154054Sbinkertn@umich.edu case ISA::IPR_MCSR: 3164046Sbinkertn@umich.edu case ISA::IPR_ASTRR: 317452SN/A case ISA::IPR_ASTER: 3183064Sgblack@eecs.umich.edu case ISA::IPR_SIRR: 3192SN/A case ISA::IPR_ICSR: 3204054Sbinkertn@umich.edu case ISA::IPR_ICM: 3211904SN/A case ISA::IPR_DTB_CM: 3222SN/A case ISA::IPR_IPLR: 3234054Sbinkertn@umich.edu case ISA::IPR_INTID: 3243064Sgblack@eecs.umich.edu case ISA::IPR_PMCTR: 3252SN/A // no side-effect 3262SN/A retval = ipr[idx]; 3271904SN/A break; 3281904SN/A 3291904SN/A case ISA::IPR_CC: 3302299SN/A retval |= ipr[idx] & ULL(0xffffffff00000000); 3314054Sbinkertn@umich.edu retval |= curTick & ULL(0x00000000ffffffff); 3321904SN/A break; 3331904SN/A 3341904SN/A case ISA::IPR_VA: 3351904SN/A retval = ipr[idx]; 3361904SN/A break; 3371904SN/A 3381904SN/A case ISA::IPR_VA_FORM: 339452SN/A case ISA::IPR_MM_STAT: 3401904SN/A case ISA::IPR_IFAULT_VA_FORM: 3411904SN/A case ISA::IPR_EXC_MASK: 3421904SN/A case ISA::IPR_EXC_SUM: 3432SN/A retval = ipr[idx]; 3442SN/A break; 3451904SN/A 3461904SN/A case ISA::IPR_DTB_PTE: 3471904SN/A { 3481904SN/A typename ISA::PTE &pte = cpu->dtb->index(1); 3491904SN/A 3501904SN/A retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; 3512SN/A retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; 3521904SN/A retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; 3532SN/A retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; 3542SN/A retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; 3551904SN/A retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; 3562SN/A retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; 3574054Sbinkertn@umich.edu } 3584762Snate@binkert.org break; 3591904SN/A 3601904SN/A // write only registers 3614054Sbinkertn@umich.edu case ISA::IPR_HWINT_CLR: 3621904SN/A case ISA::IPR_SL_XMIT: 3631904SN/A case ISA::IPR_DC_FLUSH: 3641904SN/A case ISA::IPR_IC_FLUSH: 3651904SN/A case ISA::IPR_ALT_MODE: 3661904SN/A case ISA::IPR_DTB_IA: 3671904SN/A case ISA::IPR_DTB_IAP: 3681904SN/A case ISA::IPR_ITB_IA: 3691904SN/A case ISA::IPR_ITB_IAP: 3701904SN/A fault = Unimplemented_Opcode_Fault; 3711904SN/A break; 3721904SN/A 3734054Sbinkertn@umich.edu default: 3741904SN/A // invalid IPR 3751904SN/A fault = Unimplemented_Opcode_Fault; 3764054Sbinkertn@umich.edu break; 3772525SN/A } 3781904SN/A 3792525SN/A return retval; 3802525SN/A} 3812525SN/A 3821904SN/Aextern int break_ipl; 3831904SN/A 3841904SN/Atemplate <class Impl> 3854054Sbinkertn@umich.eduFault 3861904SN/APhysRegFile<Impl>::setIpr(int idx, uint64_t val) 3871904SN/A{ 3884054Sbinkertn@umich.edu uint64_t old; 3891904SN/A 3901967SN/A switch (idx) { 3911967SN/A case ISA::IPR_PALtemp0: 3921967SN/A case ISA::IPR_PALtemp1: 3931967SN/A case ISA::IPR_PALtemp2: 3941967SN/A case ISA::IPR_PALtemp3: 3952SN/A case ISA::IPR_PALtemp4: 3963817Ssaidi@eecs.umich.edu case ISA::IPR_PALtemp5: 3974266Sgblack@eecs.umich.edu case ISA::IPR_PALtemp6: 3983506Ssaidi@eecs.umich.edu case ISA::IPR_PALtemp7: 3994054Sbinkertn@umich.edu case ISA::IPR_PALtemp8: 4003506Ssaidi@eecs.umich.edu case ISA::IPR_PALtemp9: 4013506Ssaidi@eecs.umich.edu case ISA::IPR_PALtemp10: 4023506Ssaidi@eecs.umich.edu case ISA::IPR_PALtemp11: 4033814Ssaidi@eecs.umich.edu case ISA::IPR_PALtemp12: 4043506Ssaidi@eecs.umich.edu case ISA::IPR_PALtemp13: 4053931Ssaidi@eecs.umich.edu case ISA::IPR_PALtemp14: 4063931Ssaidi@eecs.umich.edu case ISA::IPR_PALtemp15: 4073748Sgblack@eecs.umich.edu case ISA::IPR_PALtemp16: 4083748Sgblack@eecs.umich.edu case ISA::IPR_PALtemp17: 4093748Sgblack@eecs.umich.edu case ISA::IPR_PALtemp18: 4103748Sgblack@eecs.umich.edu case ISA::IPR_PALtemp19: 4113748Sgblack@eecs.umich.edu case ISA::IPR_PALtemp20: 4123748Sgblack@eecs.umich.edu case ISA::IPR_PALtemp21: 4133748Sgblack@eecs.umich.edu case ISA::IPR_PALtemp22: 4143748Sgblack@eecs.umich.edu case ISA::IPR_PAL_BASE: 4153748Sgblack@eecs.umich.edu case ISA::IPR_IC_PERR_STAT: 4163748Sgblack@eecs.umich.edu case ISA::IPR_DC_PERR_STAT: 4174001Ssaidi@eecs.umich.edu case ISA::IPR_PMCTR: 4183748Sgblack@eecs.umich.edu // write entire quad w/ no side-effect 4193748Sgblack@eecs.umich.edu ipr[idx] = val; 4203748Sgblack@eecs.umich.edu break; 4213748Sgblack@eecs.umich.edu 4223748Sgblack@eecs.umich.edu case ISA::IPR_CC_CTL: 4233748Sgblack@eecs.umich.edu // This IPR resets the cycle counter. We assume this only 4243748Sgblack@eecs.umich.edu // happens once... let's verify that. 4253748Sgblack@eecs.umich.edu assert(ipr[idx] == 0); 4263748Sgblack@eecs.umich.edu ipr[idx] = 1; 4273748Sgblack@eecs.umich.edu break; 4283880Ssaidi@eecs.umich.edu 4293603Ssaidi@eecs.umich.edu case ISA::IPR_CC: 4303603Ssaidi@eecs.umich.edu // This IPR only writes the upper 64 bits. It's ok to write 4314054Sbinkertn@umich.edu // all 64 here since we mask out the lower 32 in rpcc (see 4324054Sbinkertn@umich.edu // isa_desc). 4334054Sbinkertn@umich.edu ipr[idx] = val; 4343903Ssaidi@eecs.umich.edu break; 4354539Sgblack@eecs.umich.edu 4363903Ssaidi@eecs.umich.edu case ISA::IPR_PALtemp23: 4374046Sbinkertn@umich.edu // write entire quad w/ no side-effect 4383903Ssaidi@eecs.umich.edu old = ipr[idx]; 4393903Ssaidi@eecs.umich.edu ipr[idx] = val; 4403903Ssaidi@eecs.umich.edu break; 4413903Ssaidi@eecs.umich.edu 4423903Ssaidi@eecs.umich.edu case ISA::IPR_DTB_PTE: 4433903Ssaidi@eecs.umich.edu // write entire quad w/ no side-effect, tag is forthcoming 4443903Ssaidi@eecs.umich.edu ipr[idx] = val; 4453903Ssaidi@eecs.umich.edu break; 4463903Ssaidi@eecs.umich.edu 4474539Sgblack@eecs.umich.edu case ISA::IPR_EXC_ADDR: 4483903Ssaidi@eecs.umich.edu // second least significant bit in PC is always zero 4494539Sgblack@eecs.umich.edu ipr[idx] = val & ~2; 4503903Ssaidi@eecs.umich.edu break; 4513903Ssaidi@eecs.umich.edu 4523506Ssaidi@eecs.umich.edu case ISA::IPR_ASTRR: 4534539Sgblack@eecs.umich.edu case ISA::IPR_ASTER: 4543584Ssaidi@eecs.umich.edu // only write least significant four bits - privilege mask 4553584Ssaidi@eecs.umich.edu ipr[idx] = val & 0xf; 4563748Sgblack@eecs.umich.edu break; 4573928Ssaidi@eecs.umich.edu 4583928Ssaidi@eecs.umich.edu case ISA::IPR_IPLR: 4593928Ssaidi@eecs.umich.edu // only write least significant five bits - interrupt level 4603748Sgblack@eecs.umich.edu ipr[idx] = val & 0x1f; 4613603Ssaidi@eecs.umich.edu break; 4623584Ssaidi@eecs.umich.edu 4633814Ssaidi@eecs.umich.edu case ISA::IPR_DTB_CM: 4643814Ssaidi@eecs.umich.edu 4653814Ssaidi@eecs.umich.edu case ISA::IPR_ICM: 4663814Ssaidi@eecs.umich.edu // only write two mode bits - processor mode 4673814Ssaidi@eecs.umich.edu ipr[idx] = val & 0x18; 4683743Sgblack@eecs.umich.edu break; 4693743Sgblack@eecs.umich.edu 4703584Ssaidi@eecs.umich.edu case ISA::IPR_ALT_MODE: 4713743Sgblack@eecs.umich.edu // only write two mode bits - processor mode 4723989Ssaidi@eecs.umich.edu ipr[idx] = val & 0x18; 4733989Ssaidi@eecs.umich.edu break; 4743603Ssaidi@eecs.umich.edu 4753931Ssaidi@eecs.umich.edu case ISA::IPR_MCSR: 4763603Ssaidi@eecs.umich.edu // more here after optimization... 4773584Ssaidi@eecs.umich.edu ipr[idx] = val; 4783931Ssaidi@eecs.umich.edu break; 4793945Ssaidi@eecs.umich.edu 4803931Ssaidi@eecs.umich.edu case ISA::IPR_SIRR: 4813931Ssaidi@eecs.umich.edu // only write software interrupt mask 4823931Ssaidi@eecs.umich.edu ipr[idx] = val & 0x7fff0; 4834172Ssaidi@eecs.umich.edu break; 4843748Sgblack@eecs.umich.edu 4853748Sgblack@eecs.umich.edu case ISA::IPR_ICSR: 4863748Sgblack@eecs.umich.edu ipr[idx] = val & ULL(0xffffff0300); 4874172Ssaidi@eecs.umich.edu break; 4884172Ssaidi@eecs.umich.edu 4893815Ssaidi@eecs.umich.edu case ISA::IPR_IVPTBR: 4903748Sgblack@eecs.umich.edu case ISA::IPR_MVPTBR: 4914172Ssaidi@eecs.umich.edu ipr[idx] = val & ULL(0xffffffffc0000000); 4923815Ssaidi@eecs.umich.edu break; 4933748Sgblack@eecs.umich.edu 4944172Ssaidi@eecs.umich.edu case ISA::IPR_DC_TEST_CTL: 4953815Ssaidi@eecs.umich.edu ipr[idx] = val & 0x1ffb; 4963748Sgblack@eecs.umich.edu break; 4974172Ssaidi@eecs.umich.edu 4983815Ssaidi@eecs.umich.edu case ISA::IPR_DC_MODE: 4993748Sgblack@eecs.umich.edu case ISA::IPR_MAF_MODE: 5004172Ssaidi@eecs.umich.edu ipr[idx] = val & 0x3f; 5013815Ssaidi@eecs.umich.edu break; 5023748Sgblack@eecs.umich.edu 5033748Sgblack@eecs.umich.edu case ISA::IPR_ITB_ASN: 5044172Ssaidi@eecs.umich.edu ipr[idx] = val & 0x7f0; 5053584Ssaidi@eecs.umich.edu break; 5064172Ssaidi@eecs.umich.edu 5073748Sgblack@eecs.umich.edu case ISA::IPR_DTB_ASN: 5083748Sgblack@eecs.umich.edu ipr[idx] = val & ULL(0xfe00000000000000); 5093748Sgblack@eecs.umich.edu break; 5103748Sgblack@eecs.umich.edu 5113748Sgblack@eecs.umich.edu case ISA::IPR_EXC_SUM: 5123748Sgblack@eecs.umich.edu case ISA::IPR_EXC_MASK: 5133748Sgblack@eecs.umich.edu // any write to this register clears it 5144172Ssaidi@eecs.umich.edu ipr[idx] = 0; 5153748Sgblack@eecs.umich.edu break; 5164172Ssaidi@eecs.umich.edu 5173748Sgblack@eecs.umich.edu case ISA::IPR_INTID: 5184172Ssaidi@eecs.umich.edu case ISA::IPR_SL_RCV: 5193748Sgblack@eecs.umich.edu case ISA::IPR_MM_STAT: 5204172Ssaidi@eecs.umich.edu case ISA::IPR_ITB_PTE_TEMP: 5213790Sgblack@eecs.umich.edu case ISA::IPR_DTB_PTE_TEMP: 5223790Sgblack@eecs.umich.edu // read-only registers 5233748Sgblack@eecs.umich.edu return Unimplemented_Opcode_Fault; 5244172Ssaidi@eecs.umich.edu 5254001Ssaidi@eecs.umich.edu case ISA::IPR_HWINT_CLR: 5264011Ssaidi@eecs.umich.edu case ISA::IPR_SL_XMIT: 5274172Ssaidi@eecs.umich.edu case ISA::IPR_DC_FLUSH: 5284172Ssaidi@eecs.umich.edu case ISA::IPR_IC_FLUSH: 5294011Ssaidi@eecs.umich.edu // the following are write only 5304011Ssaidi@eecs.umich.edu ipr[idx] = val; 5314011Ssaidi@eecs.umich.edu break; 5324172Ssaidi@eecs.umich.edu 5333790Sgblack@eecs.umich.edu case ISA::IPR_DTB_IA: 5343790Sgblack@eecs.umich.edu // really a control write 5353748Sgblack@eecs.umich.edu ipr[idx] = 0; 5364172Ssaidi@eecs.umich.edu 5373748Sgblack@eecs.umich.edu cpu->dtb->flushAll(); 5384172Ssaidi@eecs.umich.edu break; 5393748Sgblack@eecs.umich.edu 5404172Ssaidi@eecs.umich.edu case ISA::IPR_DTB_IAP: 5413748Sgblack@eecs.umich.edu // really a control write 5424172Ssaidi@eecs.umich.edu ipr[idx] = 0; 5433748Sgblack@eecs.umich.edu 5444172Ssaidi@eecs.umich.edu cpu->dtb->flushProcesses(); 5453790Sgblack@eecs.umich.edu break; 5463790Sgblack@eecs.umich.edu 5473748Sgblack@eecs.umich.edu case ISA::IPR_DTB_IS: 5483790Sgblack@eecs.umich.edu // really a control write 5494172Ssaidi@eecs.umich.edu ipr[idx] = val; 5503748Sgblack@eecs.umich.edu 5513989Ssaidi@eecs.umich.edu cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN])); 5523748Sgblack@eecs.umich.edu break; 5534172Ssaidi@eecs.umich.edu 5543790Sgblack@eecs.umich.edu case ISA::IPR_DTB_TAG: { 5553989Ssaidi@eecs.umich.edu struct ISA::PTE pte; 5563748Sgblack@eecs.umich.edu 5574172Ssaidi@eecs.umich.edu // FIXME: granularity hints NYI... 5583790Sgblack@eecs.umich.edu if (DTB_PTE_GH(ipr[ISA::IPR_DTB_PTE]) != 0) 5593989Ssaidi@eecs.umich.edu panic("PTE GH field != 0"); 5603748Sgblack@eecs.umich.edu 5613748Sgblack@eecs.umich.edu // write entire quad 5623880Ssaidi@eecs.umich.edu ipr[idx] = val; 5633880Ssaidi@eecs.umich.edu 5643880Ssaidi@eecs.umich.edu // construct PTE for new entry 5653880Ssaidi@eecs.umich.edu pte.ppn = DTB_PTE_PPN(ipr[ISA::IPR_DTB_PTE]); 5663880Ssaidi@eecs.umich.edu pte.xre = DTB_PTE_XRE(ipr[ISA::IPR_DTB_PTE]); 5673880Ssaidi@eecs.umich.edu pte.xwe = DTB_PTE_XWE(ipr[ISA::IPR_DTB_PTE]); 5683880Ssaidi@eecs.umich.edu pte.fonr = DTB_PTE_FONR(ipr[ISA::IPR_DTB_PTE]); 5694008Ssaidi@eecs.umich.edu pte.fonw = DTB_PTE_FONW(ipr[ISA::IPR_DTB_PTE]); 5703931Ssaidi@eecs.umich.edu pte.asma = DTB_PTE_ASMA(ipr[ISA::IPR_DTB_PTE]); 5713931Ssaidi@eecs.umich.edu pte.asn = DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]); 5724001Ssaidi@eecs.umich.edu 5734001Ssaidi@eecs.umich.edu // insert new TAG/PTE value into data TLB 5743931Ssaidi@eecs.umich.edu cpu->dtb->insert(val, pte); 5754008Ssaidi@eecs.umich.edu } 5763863Ssaidi@eecs.umich.edu break; 5773584Ssaidi@eecs.umich.edu 5783584Ssaidi@eecs.umich.edu case ISA::IPR_ITB_PTE: { 5793584Ssaidi@eecs.umich.edu struct ISA::PTE pte; 5803814Ssaidi@eecs.umich.edu 5813814Ssaidi@eecs.umich.edu // FIXME: granularity hints NYI... 5823584Ssaidi@eecs.umich.edu if (ITB_PTE_GH(val) != 0) 5833584Ssaidi@eecs.umich.edu panic("PTE GH field != 0"); 5843931Ssaidi@eecs.umich.edu 5853584Ssaidi@eecs.umich.edu // write entire quad 5863931Ssaidi@eecs.umich.edu ipr[idx] = val; 5873931Ssaidi@eecs.umich.edu 5883748Sgblack@eecs.umich.edu // construct PTE for new entry 5893748Sgblack@eecs.umich.edu pte.ppn = ITB_PTE_PPN(val); 5903748Sgblack@eecs.umich.edu pte.xre = ITB_PTE_XRE(val); 5913748Sgblack@eecs.umich.edu pte.xwe = 0; 5923748Sgblack@eecs.umich.edu pte.fonr = ITB_PTE_FONR(val); 5933748Sgblack@eecs.umich.edu pte.fonw = ITB_PTE_FONW(val); 5943748Sgblack@eecs.umich.edu pte.asma = ITB_PTE_ASMA(val); 5953748Sgblack@eecs.umich.edu pte.asn = ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]); 5963748Sgblack@eecs.umich.edu 5973748Sgblack@eecs.umich.edu // insert new TAG/PTE value into data TLB 5983748Sgblack@eecs.umich.edu cpu->itb->insert(ipr[ISA::IPR_ITB_TAG], pte); 5993748Sgblack@eecs.umich.edu } 6003748Sgblack@eecs.umich.edu break; 6013748Sgblack@eecs.umich.edu 6023748Sgblack@eecs.umich.edu case ISA::IPR_ITB_IA: 6033748Sgblack@eecs.umich.edu // really a control write 6043748Sgblack@eecs.umich.edu ipr[idx] = 0; 6053748Sgblack@eecs.umich.edu 6064001Ssaidi@eecs.umich.edu cpu->itb->flushAll(); 6074001Ssaidi@eecs.umich.edu break; 6083748Sgblack@eecs.umich.edu 6093748Sgblack@eecs.umich.edu case ISA::IPR_ITB_IAP: 6103748Sgblack@eecs.umich.edu // really a control write 6113748Sgblack@eecs.umich.edu ipr[idx] = 0; 6123748Sgblack@eecs.umich.edu 6133748Sgblack@eecs.umich.edu cpu->itb->flushProcesses(); 6143748Sgblack@eecs.umich.edu break; 6153748Sgblack@eecs.umich.edu 6163748Sgblack@eecs.umich.edu case ISA::IPR_ITB_IS: 6173748Sgblack@eecs.umich.edu // really a control write 6183748Sgblack@eecs.umich.edu ipr[idx] = val; 6193748Sgblack@eecs.umich.edu 6203748Sgblack@eecs.umich.edu cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN])); 6213748Sgblack@eecs.umich.edu break; 6223748Sgblack@eecs.umich.edu 6233748Sgblack@eecs.umich.edu default: 6243748Sgblack@eecs.umich.edu // invalid IPR 6253748Sgblack@eecs.umich.edu return Unimplemented_Opcode_Fault; 6263748Sgblack@eecs.umich.edu } 6273748Sgblack@eecs.umich.edu 6283880Ssaidi@eecs.umich.edu // no error... 6293880Ssaidi@eecs.umich.edu return No_Fault; 6303603Ssaidi@eecs.umich.edu} 6313584Ssaidi@eecs.umich.edu 6323603Ssaidi@eecs.umich.edu#endif // #ifdef FULL_SYSTEM 6333584Ssaidi@eecs.umich.edu 6343603Ssaidi@eecs.umich.edu#endif // __CPU_BETA_CPU_REGFILE_HH__ 6353584Ssaidi@eecs.umich.edu