regfile.hh revision 13610
11689SN/A/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2016-2017 ARM Limited 312109SRekai.GonzalezAlberquilla@arm.com * All rights reserved 412109SRekai.GonzalezAlberquilla@arm.com * 512109SRekai.GonzalezAlberquilla@arm.com * The license below extends only to copyright in the software and shall 612109SRekai.GonzalezAlberquilla@arm.com * not be construed as granting a license to any other intellectual 712109SRekai.GonzalezAlberquilla@arm.com * property including but not limited to intellectual property relating 812109SRekai.GonzalezAlberquilla@arm.com * to a hardware implementation of the functionality of the software 912109SRekai.GonzalezAlberquilla@arm.com * licensed hereunder. You may use the software subject to the license 1012109SRekai.GonzalezAlberquilla@arm.com * terms below provided that you ensure that this notice is replicated 1112109SRekai.GonzalezAlberquilla@arm.com * unmodified and in its entirety in all distributions of the software, 1212109SRekai.GonzalezAlberquilla@arm.com * modified or unmodified, in source code or in binary form. 1312109SRekai.GonzalezAlberquilla@arm.com * 141689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 159915Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422665Ssaidi@eecs.umich.edu * Gabe Black 431689SN/A */ 441689SN/A 452292SN/A#ifndef __CPU_O3_REGFILE_HH__ 462292SN/A#define __CPU_O3_REGFILE_HH__ 471060SN/A 486658Snate@binkert.org#include <vector> 496658Snate@binkert.org 502165SN/A#include "arch/isa_traits.hh" 518793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 522669Sktlim@umich.edu#include "arch/types.hh" 531681SN/A#include "base/trace.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 551717SN/A#include "cpu/o3/comm.hh" 568232Snate@binkert.org#include "debug/IEW.hh" 5712109SRekai.GonzalezAlberquilla@arm.com#include "enums/VecRegRenameMode.hh" 581060SN/A 599919Ssteve.reinhardt@amd.comclass UnifiedFreeList; 609919Ssteve.reinhardt@amd.com 612292SN/A/** 622292SN/A * Simple physical register file class. 632292SN/A */ 641060SN/Aclass PhysRegFile 651060SN/A{ 669915Ssteve.reinhardt@amd.com private: 679915Ssteve.reinhardt@amd.com 689920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 6912109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 7012109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 7112109SRekai.GonzalezAlberquilla@arm.com using PhysIds = std::vector<PhysRegId>; 7212109SRekai.GonzalezAlberquilla@arm.com using VecMode = Enums::VecRegRenameMode; 7313610Sgiacomo.gabrielli@arm.com using VecPredRegContainer = TheISA::VecPredRegContainer; 7412109SRekai.GonzalezAlberquilla@arm.com public: 7512109SRekai.GonzalezAlberquilla@arm.com using IdRange = std::pair<PhysIds::const_iterator, 7612109SRekai.GonzalezAlberquilla@arm.com PhysIds::const_iterator>; 7712109SRekai.GonzalezAlberquilla@arm.com private: 7812109SRekai.GonzalezAlberquilla@arm.com static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; 792159SN/A 809915Ssteve.reinhardt@amd.com /** Integer register file. */ 8113557Sgabeblack@google.com std::vector<RegVal> intRegFile; 8212105Snathanael.premillieu@arm.com std::vector<PhysRegId> intRegIds; 831060SN/A 849915Ssteve.reinhardt@amd.com /** Floating point register file. */ 8513557Sgabeblack@google.com std::vector<RegVal> floatRegFile; 8612105Snathanael.premillieu@arm.com std::vector<PhysRegId> floatRegIds; 879915Ssteve.reinhardt@amd.com 8812109SRekai.GonzalezAlberquilla@arm.com /** Vector register file. */ 8912109SRekai.GonzalezAlberquilla@arm.com std::vector<VecRegContainer> vectorRegFile; 9012109SRekai.GonzalezAlberquilla@arm.com std::vector<PhysRegId> vecRegIds; 9112109SRekai.GonzalezAlberquilla@arm.com std::vector<PhysRegId> vecElemIds; 9212109SRekai.GonzalezAlberquilla@arm.com 9313610Sgiacomo.gabrielli@arm.com /** Predicate register file. */ 9413610Sgiacomo.gabrielli@arm.com std::vector<VecPredRegContainer> vecPredRegFile; 9513610Sgiacomo.gabrielli@arm.com std::vector<PhysRegId> vecPredRegIds; 9613610Sgiacomo.gabrielli@arm.com 979920Syasuko.eckert@amd.com /** Condition-code register file. */ 989920Syasuko.eckert@amd.com std::vector<CCReg> ccRegFile; 9912105Snathanael.premillieu@arm.com std::vector<PhysRegId> ccRegIds; 10012105Snathanael.premillieu@arm.com 10112105Snathanael.premillieu@arm.com /** Misc Reg Ids */ 10212105Snathanael.premillieu@arm.com std::vector<PhysRegId> miscRegIds; 1039920Syasuko.eckert@amd.com 1049915Ssteve.reinhardt@amd.com /** 10512105Snathanael.premillieu@arm.com * Number of physical general purpose registers 1069915Ssteve.reinhardt@amd.com */ 10712105Snathanael.premillieu@arm.com unsigned numPhysicalIntRegs; 1089915Ssteve.reinhardt@amd.com 1099920Syasuko.eckert@amd.com /** 11012109SRekai.GonzalezAlberquilla@arm.com * Number of physical floating point registers 1119920Syasuko.eckert@amd.com */ 11212105Snathanael.premillieu@arm.com unsigned numPhysicalFloatRegs; 11312105Snathanael.premillieu@arm.com 11412105Snathanael.premillieu@arm.com /** 11512109SRekai.GonzalezAlberquilla@arm.com * Number of physical vector registers 11612109SRekai.GonzalezAlberquilla@arm.com */ 11712109SRekai.GonzalezAlberquilla@arm.com unsigned numPhysicalVecRegs; 11812109SRekai.GonzalezAlberquilla@arm.com 11912109SRekai.GonzalezAlberquilla@arm.com /** 12012109SRekai.GonzalezAlberquilla@arm.com * Number of physical vector element registers 12112109SRekai.GonzalezAlberquilla@arm.com */ 12212109SRekai.GonzalezAlberquilla@arm.com unsigned numPhysicalVecElemRegs; 12312109SRekai.GonzalezAlberquilla@arm.com 12412109SRekai.GonzalezAlberquilla@arm.com /** 12513610Sgiacomo.gabrielli@arm.com * Number of physical predicate registers 12613610Sgiacomo.gabrielli@arm.com */ 12713610Sgiacomo.gabrielli@arm.com unsigned numPhysicalVecPredRegs; 12813610Sgiacomo.gabrielli@arm.com 12913610Sgiacomo.gabrielli@arm.com /** 13012109SRekai.GonzalezAlberquilla@arm.com * Number of physical CC registers 13112105Snathanael.premillieu@arm.com */ 13212105Snathanael.premillieu@arm.com unsigned numPhysicalCCRegs; 1339920Syasuko.eckert@amd.com 1349915Ssteve.reinhardt@amd.com /** Total number of physical registers. */ 1359915Ssteve.reinhardt@amd.com unsigned totalNumRegs; 1369915Ssteve.reinhardt@amd.com 13712109SRekai.GonzalezAlberquilla@arm.com /** Mode in which vector registers are addressed. */ 13812109SRekai.GonzalezAlberquilla@arm.com VecMode vecMode; 13912109SRekai.GonzalezAlberquilla@arm.com 1401060SN/A public: 1412292SN/A /** 1422292SN/A * Constructs a physical register file with the specified amount of 1432292SN/A * integer and floating point registers. 1442292SN/A */ 1459915Ssteve.reinhardt@amd.com PhysRegFile(unsigned _numPhysicalIntRegs, 1469920Syasuko.eckert@amd.com unsigned _numPhysicalFloatRegs, 14712109SRekai.GonzalezAlberquilla@arm.com unsigned _numPhysicalVecRegs, 14813610Sgiacomo.gabrielli@arm.com unsigned _numPhysicalVecPredRegs, 14912109SRekai.GonzalezAlberquilla@arm.com unsigned _numPhysicalCCRegs, 15012109SRekai.GonzalezAlberquilla@arm.com VecMode vmode 15112109SRekai.GonzalezAlberquilla@arm.com ); 1521060SN/A 1539086Sandreas.hansson@arm.com /** 1549086Sandreas.hansson@arm.com * Destructor to free resources 1559086Sandreas.hansson@arm.com */ 1569919Ssteve.reinhardt@amd.com ~PhysRegFile() {} 1579919Ssteve.reinhardt@amd.com 1589919Ssteve.reinhardt@amd.com /** Initialize the free list */ 1599919Ssteve.reinhardt@amd.com void initFreeList(UnifiedFreeList *freeList); 1609086Sandreas.hansson@arm.com 1619915Ssteve.reinhardt@amd.com /** @return the number of integer physical registers. */ 16212105Snathanael.premillieu@arm.com unsigned numIntPhysRegs() const { return numPhysicalIntRegs; } 1639915Ssteve.reinhardt@amd.com 1649915Ssteve.reinhardt@amd.com /** @return the number of floating-point physical registers. */ 16512105Snathanael.premillieu@arm.com unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; } 16612109SRekai.GonzalezAlberquilla@arm.com /** @return the number of vector physical registers. */ 16712109SRekai.GonzalezAlberquilla@arm.com unsigned numVecPhysRegs() const { return numPhysicalVecRegs; } 16813610Sgiacomo.gabrielli@arm.com /** @return the number of predicate physical registers. */ 16913610Sgiacomo.gabrielli@arm.com unsigned numPredPhysRegs() const { return numPhysicalVecPredRegs; } 17012109SRekai.GonzalezAlberquilla@arm.com 17112109SRekai.GonzalezAlberquilla@arm.com /** @return the number of vector physical registers. */ 17212109SRekai.GonzalezAlberquilla@arm.com unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; } 1739920Syasuko.eckert@amd.com 1749920Syasuko.eckert@amd.com /** @return the number of condition-code physical registers. */ 17512105Snathanael.premillieu@arm.com unsigned numCCPhysRegs() const { return numPhysicalCCRegs; } 1769915Ssteve.reinhardt@amd.com 1779915Ssteve.reinhardt@amd.com /** @return the total number of physical registers. */ 1789915Ssteve.reinhardt@amd.com unsigned totalNumPhysRegs() const { return totalNumRegs; } 1799915Ssteve.reinhardt@amd.com 18012105Snathanael.premillieu@arm.com /** Gets a misc register PhysRegIdPtr. */ 18112105Snathanael.premillieu@arm.com PhysRegIdPtr getMiscRegId(RegIndex reg_idx) { 18212105Snathanael.premillieu@arm.com return &miscRegIds[reg_idx]; 1839915Ssteve.reinhardt@amd.com } 1841060SN/A 1852292SN/A /** Reads an integer register. */ 18613557Sgabeblack@google.com RegVal 18713557Sgabeblack@google.com readIntReg(PhysRegIdPtr phys_reg) const 1881060SN/A { 18912105Snathanael.premillieu@arm.com assert(phys_reg->isIntPhysReg()); 1901061SN/A 1911060SN/A DPRINTF(IEW, "RegFile: Access to int register %i, has data " 19212106SRekai.GonzalezAlberquilla@arm.com "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]); 19312106SRekai.GonzalezAlberquilla@arm.com return intRegFile[phys_reg->index()]; 1941060SN/A } 1951060SN/A 19613557Sgabeblack@google.com RegVal 19713557Sgabeblack@google.com readFloatRegBits(PhysRegIdPtr phys_reg) const 1982455SN/A { 19912105Snathanael.premillieu@arm.com assert(phys_reg->isFloatPhysReg()); 2009915Ssteve.reinhardt@amd.com 20113557Sgabeblack@google.com RegVal floatRegBits = floatRegFile[phys_reg->index()]; 2022455SN/A 2032455SN/A DPRINTF(IEW, "RegFile: Access to float register %i as int, " 20413557Sgabeblack@google.com "has data %#x\n", phys_reg->index(), floatRegBits); 2052455SN/A 2062455SN/A return floatRegBits; 2071060SN/A } 2081060SN/A 20912109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register. */ 21013557Sgabeblack@google.com const VecRegContainer & 21113557Sgabeblack@google.com readVecReg(PhysRegIdPtr phys_reg) const 21212109SRekai.GonzalezAlberquilla@arm.com { 21312109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysReg()); 21412109SRekai.GonzalezAlberquilla@arm.com 21512109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Access to vector register %i, has " 21612109SRekai.GonzalezAlberquilla@arm.com "data %s\n", int(phys_reg->index()), 21713610Sgiacomo.gabrielli@arm.com vectorRegFile[phys_reg->index()].print()); 21812109SRekai.GonzalezAlberquilla@arm.com 21912109SRekai.GonzalezAlberquilla@arm.com return vectorRegFile[phys_reg->index()]; 22012109SRekai.GonzalezAlberquilla@arm.com } 22112109SRekai.GonzalezAlberquilla@arm.com 22212109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register for modification. */ 22313557Sgabeblack@google.com VecRegContainer & 22413557Sgabeblack@google.com getWritableVecReg(PhysRegIdPtr phys_reg) 22512109SRekai.GonzalezAlberquilla@arm.com { 22612109SRekai.GonzalezAlberquilla@arm.com /* const_cast for not duplicating code above. */ 22712109SRekai.GonzalezAlberquilla@arm.com return const_cast<VecRegContainer&>(readVecReg(phys_reg)); 22812109SRekai.GonzalezAlberquilla@arm.com } 22912109SRekai.GonzalezAlberquilla@arm.com 23012109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register lane. */ 23112109SRekai.GonzalezAlberquilla@arm.com template <typename VecElem, int LaneIdx> 23212109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 23312109SRekai.GonzalezAlberquilla@arm.com readVecLane(PhysRegIdPtr phys_reg) const 23412109SRekai.GonzalezAlberquilla@arm.com { 23512109SRekai.GonzalezAlberquilla@arm.com return readVecReg(phys_reg).laneView<VecElem, LaneIdx>(); 23612109SRekai.GonzalezAlberquilla@arm.com } 23712109SRekai.GonzalezAlberquilla@arm.com 23812109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register lane. */ 23912109SRekai.GonzalezAlberquilla@arm.com template <typename VecElem> 24012109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 24112109SRekai.GonzalezAlberquilla@arm.com readVecLane(PhysRegIdPtr phys_reg) const 24212109SRekai.GonzalezAlberquilla@arm.com { 24312109SRekai.GonzalezAlberquilla@arm.com return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex()); 24412109SRekai.GonzalezAlberquilla@arm.com } 24512109SRekai.GonzalezAlberquilla@arm.com 24612109SRekai.GonzalezAlberquilla@arm.com /** Get a vector register lane for modification. */ 24712109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 24812109SRekai.GonzalezAlberquilla@arm.com void 24912109SRekai.GonzalezAlberquilla@arm.com setVecLane(PhysRegIdPtr phys_reg, const LD& val) 25012109SRekai.GonzalezAlberquilla@arm.com { 25112109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysReg()); 25212109SRekai.GonzalezAlberquilla@arm.com 25312109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n", 25412109SRekai.GonzalezAlberquilla@arm.com int(phys_reg->index()), phys_reg->elemIndex(), val); 25512109SRekai.GonzalezAlberquilla@arm.com 25612109SRekai.GonzalezAlberquilla@arm.com vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>( 25712109SRekai.GonzalezAlberquilla@arm.com phys_reg->elemIndex()) = val; 25812109SRekai.GonzalezAlberquilla@arm.com } 25912109SRekai.GonzalezAlberquilla@arm.com 26012109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector element. */ 26113557Sgabeblack@google.com const VecElem & 26213557Sgabeblack@google.com readVecElem(PhysRegIdPtr phys_reg) const 26312109SRekai.GonzalezAlberquilla@arm.com { 26412109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysElem()); 26512109SRekai.GonzalezAlberquilla@arm.com auto ret = vectorRegFile[phys_reg->index()].as<VecElem>(); 26612109SRekai.GonzalezAlberquilla@arm.com const VecElem& val = ret[phys_reg->elemIndex()]; 26712109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Access to element %d of vector register %i," 26812109SRekai.GonzalezAlberquilla@arm.com " has data %#x\n", phys_reg->elemIndex(), 26912109SRekai.GonzalezAlberquilla@arm.com int(phys_reg->index()), val); 27012109SRekai.GonzalezAlberquilla@arm.com 27112109SRekai.GonzalezAlberquilla@arm.com return val; 27212109SRekai.GonzalezAlberquilla@arm.com } 27312109SRekai.GonzalezAlberquilla@arm.com 27413610Sgiacomo.gabrielli@arm.com /** Reads a predicate register. */ 27513610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& readVecPredReg(PhysRegIdPtr phys_reg) const 27613610Sgiacomo.gabrielli@arm.com { 27713610Sgiacomo.gabrielli@arm.com assert(phys_reg->isVecPredPhysReg()); 27813610Sgiacomo.gabrielli@arm.com 27913610Sgiacomo.gabrielli@arm.com DPRINTF(IEW, "RegFile: Access to predicate register %i, has " 28013610Sgiacomo.gabrielli@arm.com "data %s\n", int(phys_reg->index()), 28113610Sgiacomo.gabrielli@arm.com vecPredRegFile[phys_reg->index()].print()); 28213610Sgiacomo.gabrielli@arm.com 28313610Sgiacomo.gabrielli@arm.com return vecPredRegFile[phys_reg->index()]; 28413610Sgiacomo.gabrielli@arm.com } 28513610Sgiacomo.gabrielli@arm.com 28613610Sgiacomo.gabrielli@arm.com VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr phys_reg) 28713610Sgiacomo.gabrielli@arm.com { 28813610Sgiacomo.gabrielli@arm.com /* const_cast for not duplicating code above. */ 28913610Sgiacomo.gabrielli@arm.com return const_cast<VecPredRegContainer&>(readVecPredReg(phys_reg)); 29013610Sgiacomo.gabrielli@arm.com } 29113610Sgiacomo.gabrielli@arm.com 2929920Syasuko.eckert@amd.com /** Reads a condition-code register. */ 29313557Sgabeblack@google.com CCReg 29413557Sgabeblack@google.com readCCReg(PhysRegIdPtr phys_reg) 2959920Syasuko.eckert@amd.com { 29612105Snathanael.premillieu@arm.com assert(phys_reg->isCCPhysReg()); 2979920Syasuko.eckert@amd.com 2989920Syasuko.eckert@amd.com DPRINTF(IEW, "RegFile: Access to cc register %i, has " 29912106SRekai.GonzalezAlberquilla@arm.com "data %#x\n", phys_reg->index(), 30012106SRekai.GonzalezAlberquilla@arm.com ccRegFile[phys_reg->index()]); 3019920Syasuko.eckert@amd.com 30212106SRekai.GonzalezAlberquilla@arm.com return ccRegFile[phys_reg->index()]; 3039920Syasuko.eckert@amd.com } 3049920Syasuko.eckert@amd.com 3052292SN/A /** Sets an integer register to the given value. */ 30613557Sgabeblack@google.com void 30713557Sgabeblack@google.com setIntReg(PhysRegIdPtr phys_reg, RegVal val) 3081060SN/A { 30912105Snathanael.premillieu@arm.com assert(phys_reg->isIntPhysReg()); 3101061SN/A 3112690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 31212106SRekai.GonzalezAlberquilla@arm.com phys_reg->index(), val); 3131060SN/A 31412105Snathanael.premillieu@arm.com if (!phys_reg->isZeroReg()) 31512106SRekai.GonzalezAlberquilla@arm.com intRegFile[phys_reg->index()] = val; 3161060SN/A } 3171060SN/A 31813557Sgabeblack@google.com void 31913557Sgabeblack@google.com setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val) 3202455SN/A { 32112105Snathanael.premillieu@arm.com assert(phys_reg->isFloatPhysReg()); 3222455SN/A 3232690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 32412106SRekai.GonzalezAlberquilla@arm.com phys_reg->index(), (uint64_t)val); 3252455SN/A 32612109SRekai.GonzalezAlberquilla@arm.com if (!phys_reg->isZeroReg()) 32713501Sgabeblack@google.com floatRegFile[phys_reg->index()] = val; 32812109SRekai.GonzalezAlberquilla@arm.com } 32912109SRekai.GonzalezAlberquilla@arm.com 33012109SRekai.GonzalezAlberquilla@arm.com /** Sets a vector register to the given value. */ 33113557Sgabeblack@google.com void 33213557Sgabeblack@google.com setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) 33312109SRekai.GonzalezAlberquilla@arm.com { 33412109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysReg()); 33512109SRekai.GonzalezAlberquilla@arm.com 33612109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n", 33712109SRekai.GonzalezAlberquilla@arm.com int(phys_reg->index()), val.print()); 33812109SRekai.GonzalezAlberquilla@arm.com 33912109SRekai.GonzalezAlberquilla@arm.com vectorRegFile[phys_reg->index()] = val; 34012109SRekai.GonzalezAlberquilla@arm.com } 34112109SRekai.GonzalezAlberquilla@arm.com 34212109SRekai.GonzalezAlberquilla@arm.com /** Sets a vector register to the given value. */ 34313557Sgabeblack@google.com void 34413557Sgabeblack@google.com setVecElem(PhysRegIdPtr phys_reg, const VecElem val) 34512109SRekai.GonzalezAlberquilla@arm.com { 34612109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysElem()); 34712109SRekai.GonzalezAlberquilla@arm.com 34812109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to" 34912109SRekai.GonzalezAlberquilla@arm.com " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val); 35012109SRekai.GonzalezAlberquilla@arm.com 35112109SRekai.GonzalezAlberquilla@arm.com vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] = 35212109SRekai.GonzalezAlberquilla@arm.com val; 3531060SN/A } 3541060SN/A 35513610Sgiacomo.gabrielli@arm.com /** Sets a predicate register to the given value. */ 35613610Sgiacomo.gabrielli@arm.com void setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val) 35713610Sgiacomo.gabrielli@arm.com { 35813610Sgiacomo.gabrielli@arm.com assert(phys_reg->isVecPredPhysReg()); 35913610Sgiacomo.gabrielli@arm.com 36013610Sgiacomo.gabrielli@arm.com DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n", 36113610Sgiacomo.gabrielli@arm.com int(phys_reg->index()), val.print()); 36213610Sgiacomo.gabrielli@arm.com 36313610Sgiacomo.gabrielli@arm.com vecPredRegFile[phys_reg->index()] = val; 36413610Sgiacomo.gabrielli@arm.com } 36513610Sgiacomo.gabrielli@arm.com 3669920Syasuko.eckert@amd.com /** Sets a condition-code register to the given value. */ 36713557Sgabeblack@google.com void 36813557Sgabeblack@google.com setCCReg(PhysRegIdPtr phys_reg, CCReg val) 3699920Syasuko.eckert@amd.com { 37012105Snathanael.premillieu@arm.com assert(phys_reg->isCCPhysReg()); 3719920Syasuko.eckert@amd.com 3729920Syasuko.eckert@amd.com DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n", 37312106SRekai.GonzalezAlberquilla@arm.com phys_reg->index(), (uint64_t)val); 3749920Syasuko.eckert@amd.com 37512106SRekai.GonzalezAlberquilla@arm.com ccRegFile[phys_reg->index()] = val; 3769920Syasuko.eckert@amd.com } 37712109SRekai.GonzalezAlberquilla@arm.com 37812109SRekai.GonzalezAlberquilla@arm.com /** Get the PhysRegIds of the elems of a vector register. 37912109SRekai.GonzalezAlberquilla@arm.com * Auxiliary function to transition from Full vector mode to Elem mode. 38012109SRekai.GonzalezAlberquilla@arm.com */ 38112109SRekai.GonzalezAlberquilla@arm.com IdRange getRegElemIds(PhysRegIdPtr reg); 38212109SRekai.GonzalezAlberquilla@arm.com 38312109SRekai.GonzalezAlberquilla@arm.com /** 38412109SRekai.GonzalezAlberquilla@arm.com * Get the PhysRegIds of the elems of all vector registers. 38512109SRekai.GonzalezAlberquilla@arm.com * Auxiliary function to transition from Full vector mode to Elem mode 38612109SRekai.GonzalezAlberquilla@arm.com * and to initialise the rename map. 38712109SRekai.GonzalezAlberquilla@arm.com */ 38812109SRekai.GonzalezAlberquilla@arm.com IdRange getRegIds(RegClass cls); 38912109SRekai.GonzalezAlberquilla@arm.com 39013557Sgabeblack@google.com /** 39113557Sgabeblack@google.com * Get the true physical register id. 39213557Sgabeblack@google.com * As many parts work with PhysRegIdPtr, we need to be able to produce 39313557Sgabeblack@google.com * the pointer out of just class and register idx. 39413557Sgabeblack@google.com */ 39513557Sgabeblack@google.com PhysRegIdPtr getTrueId(PhysRegIdPtr reg); 3961060SN/A}; 3971060SN/A 3989915Ssteve.reinhardt@amd.com 3999915Ssteve.reinhardt@amd.com#endif //__CPU_O3_REGFILE_HH__ 400