regfile.hh revision 13501
11689SN/A/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2016 ARM Limited 312109SRekai.GonzalezAlberquilla@arm.com * All rights reserved 412109SRekai.GonzalezAlberquilla@arm.com * 512109SRekai.GonzalezAlberquilla@arm.com * The license below extends only to copyright in the software and shall 612109SRekai.GonzalezAlberquilla@arm.com * not be construed as granting a license to any other intellectual 712109SRekai.GonzalezAlberquilla@arm.com * property including but not limited to intellectual property relating 812109SRekai.GonzalezAlberquilla@arm.com * to a hardware implementation of the functionality of the software 912109SRekai.GonzalezAlberquilla@arm.com * licensed hereunder. You may use the software subject to the license 1012109SRekai.GonzalezAlberquilla@arm.com * terms below provided that you ensure that this notice is replicated 1112109SRekai.GonzalezAlberquilla@arm.com * unmodified and in its entirety in all distributions of the software, 1212109SRekai.GonzalezAlberquilla@arm.com * modified or unmodified, in source code or in binary form. 1312109SRekai.GonzalezAlberquilla@arm.com * 141689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 159915Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422665Ssaidi@eecs.umich.edu * Gabe Black 431689SN/A */ 441689SN/A 452292SN/A#ifndef __CPU_O3_REGFILE_HH__ 462292SN/A#define __CPU_O3_REGFILE_HH__ 471060SN/A 486658Snate@binkert.org#include <vector> 496658Snate@binkert.org 502165SN/A#include "arch/isa_traits.hh" 518793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 522669Sktlim@umich.edu#include "arch/types.hh" 531681SN/A#include "base/trace.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 551717SN/A#include "cpu/o3/comm.hh" 568232Snate@binkert.org#include "debug/IEW.hh" 5712109SRekai.GonzalezAlberquilla@arm.com#include "enums/VecRegRenameMode.hh" 581060SN/A 599919Ssteve.reinhardt@amd.comclass UnifiedFreeList; 609919Ssteve.reinhardt@amd.com 612292SN/A/** 622292SN/A * Simple physical register file class. 632292SN/A */ 641060SN/Aclass PhysRegFile 651060SN/A{ 669915Ssteve.reinhardt@amd.com private: 679915Ssteve.reinhardt@amd.com 682107SN/A typedef TheISA::IntReg IntReg; 692107SN/A typedef TheISA::FloatReg FloatReg; 702669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 719920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 7212109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 7312109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 7412109SRekai.GonzalezAlberquilla@arm.com using PhysIds = std::vector<PhysRegId>; 7512109SRekai.GonzalezAlberquilla@arm.com using VecMode = Enums::VecRegRenameMode; 7612109SRekai.GonzalezAlberquilla@arm.com public: 7712109SRekai.GonzalezAlberquilla@arm.com using IdRange = std::pair<PhysIds::const_iterator, 7812109SRekai.GonzalezAlberquilla@arm.com PhysIds::const_iterator>; 7912109SRekai.GonzalezAlberquilla@arm.com private: 8012109SRekai.GonzalezAlberquilla@arm.com static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; 812159SN/A 829915Ssteve.reinhardt@amd.com /** Integer register file. */ 839919Ssteve.reinhardt@amd.com std::vector<IntReg> intRegFile; 8412105Snathanael.premillieu@arm.com std::vector<PhysRegId> intRegIds; 851060SN/A 869915Ssteve.reinhardt@amd.com /** Floating point register file. */ 8713501Sgabeblack@google.com std::vector<FloatRegBits> floatRegFile; 8812105Snathanael.premillieu@arm.com std::vector<PhysRegId> floatRegIds; 899915Ssteve.reinhardt@amd.com 9012109SRekai.GonzalezAlberquilla@arm.com /** Vector register file. */ 9112109SRekai.GonzalezAlberquilla@arm.com std::vector<VecRegContainer> vectorRegFile; 9212109SRekai.GonzalezAlberquilla@arm.com std::vector<PhysRegId> vecRegIds; 9312109SRekai.GonzalezAlberquilla@arm.com std::vector<PhysRegId> vecElemIds; 9412109SRekai.GonzalezAlberquilla@arm.com 959920Syasuko.eckert@amd.com /** Condition-code register file. */ 969920Syasuko.eckert@amd.com std::vector<CCReg> ccRegFile; 9712105Snathanael.premillieu@arm.com std::vector<PhysRegId> ccRegIds; 9812105Snathanael.premillieu@arm.com 9912105Snathanael.premillieu@arm.com /** Misc Reg Ids */ 10012105Snathanael.premillieu@arm.com std::vector<PhysRegId> miscRegIds; 1019920Syasuko.eckert@amd.com 1029915Ssteve.reinhardt@amd.com /** 10312105Snathanael.premillieu@arm.com * Number of physical general purpose registers 1049915Ssteve.reinhardt@amd.com */ 10512105Snathanael.premillieu@arm.com unsigned numPhysicalIntRegs; 1069915Ssteve.reinhardt@amd.com 1079920Syasuko.eckert@amd.com /** 10812109SRekai.GonzalezAlberquilla@arm.com * Number of physical floating point registers 1099920Syasuko.eckert@amd.com */ 11012105Snathanael.premillieu@arm.com unsigned numPhysicalFloatRegs; 11112105Snathanael.premillieu@arm.com 11212105Snathanael.premillieu@arm.com /** 11312109SRekai.GonzalezAlberquilla@arm.com * Number of physical vector registers 11412109SRekai.GonzalezAlberquilla@arm.com */ 11512109SRekai.GonzalezAlberquilla@arm.com unsigned numPhysicalVecRegs; 11612109SRekai.GonzalezAlberquilla@arm.com 11712109SRekai.GonzalezAlberquilla@arm.com /** 11812109SRekai.GonzalezAlberquilla@arm.com * Number of physical vector element registers 11912109SRekai.GonzalezAlberquilla@arm.com */ 12012109SRekai.GonzalezAlberquilla@arm.com unsigned numPhysicalVecElemRegs; 12112109SRekai.GonzalezAlberquilla@arm.com 12212109SRekai.GonzalezAlberquilla@arm.com /** 12312109SRekai.GonzalezAlberquilla@arm.com * Number of physical CC registers 12412105Snathanael.premillieu@arm.com */ 12512105Snathanael.premillieu@arm.com unsigned numPhysicalCCRegs; 1269920Syasuko.eckert@amd.com 1279915Ssteve.reinhardt@amd.com /** Total number of physical registers. */ 1289915Ssteve.reinhardt@amd.com unsigned totalNumRegs; 1299915Ssteve.reinhardt@amd.com 13012109SRekai.GonzalezAlberquilla@arm.com /** Mode in which vector registers are addressed. */ 13112109SRekai.GonzalezAlberquilla@arm.com VecMode vecMode; 13212109SRekai.GonzalezAlberquilla@arm.com 1331060SN/A public: 1342292SN/A /** 1352292SN/A * Constructs a physical register file with the specified amount of 1362292SN/A * integer and floating point registers. 1372292SN/A */ 1389915Ssteve.reinhardt@amd.com PhysRegFile(unsigned _numPhysicalIntRegs, 1399920Syasuko.eckert@amd.com unsigned _numPhysicalFloatRegs, 14012109SRekai.GonzalezAlberquilla@arm.com unsigned _numPhysicalVecRegs, 14112109SRekai.GonzalezAlberquilla@arm.com unsigned _numPhysicalCCRegs, 14212109SRekai.GonzalezAlberquilla@arm.com VecMode vmode 14312109SRekai.GonzalezAlberquilla@arm.com ); 1441060SN/A 1459086Sandreas.hansson@arm.com /** 1469086Sandreas.hansson@arm.com * Destructor to free resources 1479086Sandreas.hansson@arm.com */ 1489919Ssteve.reinhardt@amd.com ~PhysRegFile() {} 1499919Ssteve.reinhardt@amd.com 1509919Ssteve.reinhardt@amd.com /** Initialize the free list */ 1519919Ssteve.reinhardt@amd.com void initFreeList(UnifiedFreeList *freeList); 1529086Sandreas.hansson@arm.com 1539915Ssteve.reinhardt@amd.com /** @return the number of integer physical registers. */ 15412105Snathanael.premillieu@arm.com unsigned numIntPhysRegs() const { return numPhysicalIntRegs; } 1559915Ssteve.reinhardt@amd.com 1569915Ssteve.reinhardt@amd.com /** @return the number of floating-point physical registers. */ 15712105Snathanael.premillieu@arm.com unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; } 15812109SRekai.GonzalezAlberquilla@arm.com /** @return the number of vector physical registers. */ 15912109SRekai.GonzalezAlberquilla@arm.com unsigned numVecPhysRegs() const { return numPhysicalVecRegs; } 16012109SRekai.GonzalezAlberquilla@arm.com 16112109SRekai.GonzalezAlberquilla@arm.com /** @return the number of vector physical registers. */ 16212109SRekai.GonzalezAlberquilla@arm.com unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; } 1639920Syasuko.eckert@amd.com 1649920Syasuko.eckert@amd.com /** @return the number of condition-code physical registers. */ 16512105Snathanael.premillieu@arm.com unsigned numCCPhysRegs() const { return numPhysicalCCRegs; } 1669915Ssteve.reinhardt@amd.com 1679915Ssteve.reinhardt@amd.com /** @return the total number of physical registers. */ 1689915Ssteve.reinhardt@amd.com unsigned totalNumPhysRegs() const { return totalNumRegs; } 1699915Ssteve.reinhardt@amd.com 17012105Snathanael.premillieu@arm.com /** Gets a misc register PhysRegIdPtr. */ 17112105Snathanael.premillieu@arm.com PhysRegIdPtr getMiscRegId(RegIndex reg_idx) { 17212105Snathanael.premillieu@arm.com return &miscRegIds[reg_idx]; 1739915Ssteve.reinhardt@amd.com } 1741060SN/A 1752292SN/A /** Reads an integer register. */ 17612105Snathanael.premillieu@arm.com uint64_t readIntReg(PhysRegIdPtr phys_reg) const 1771060SN/A { 17812105Snathanael.premillieu@arm.com assert(phys_reg->isIntPhysReg()); 1791061SN/A 1801060SN/A DPRINTF(IEW, "RegFile: Access to int register %i, has data " 18112106SRekai.GonzalezAlberquilla@arm.com "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]); 18212106SRekai.GonzalezAlberquilla@arm.com return intRegFile[phys_reg->index()]; 1831060SN/A } 1841060SN/A 18512105Snathanael.premillieu@arm.com FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg) const 1862455SN/A { 18712105Snathanael.premillieu@arm.com assert(phys_reg->isFloatPhysReg()); 1889915Ssteve.reinhardt@amd.com 18913501Sgabeblack@google.com FloatRegBits floatRegBits = floatRegFile[phys_reg->index()]; 1902455SN/A 1912455SN/A DPRINTF(IEW, "RegFile: Access to float register %i as int, " 19212106SRekai.GonzalezAlberquilla@arm.com "has data %#x\n", phys_reg->index(), 19312105Snathanael.premillieu@arm.com (uint64_t)floatRegBits); 1942455SN/A 1952455SN/A return floatRegBits; 1961060SN/A } 1971060SN/A 19812109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register. */ 19912109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecReg(PhysRegIdPtr phys_reg) const 20012109SRekai.GonzalezAlberquilla@arm.com { 20112109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysReg()); 20212109SRekai.GonzalezAlberquilla@arm.com 20312109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Access to vector register %i, has " 20412109SRekai.GonzalezAlberquilla@arm.com "data %s\n", int(phys_reg->index()), 20512109SRekai.GonzalezAlberquilla@arm.com vectorRegFile[phys_reg->index()].as<VecElem>().print()); 20612109SRekai.GonzalezAlberquilla@arm.com 20712109SRekai.GonzalezAlberquilla@arm.com return vectorRegFile[phys_reg->index()]; 20812109SRekai.GonzalezAlberquilla@arm.com } 20912109SRekai.GonzalezAlberquilla@arm.com 21012109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register for modification. */ 21112109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecReg(PhysRegIdPtr phys_reg) 21212109SRekai.GonzalezAlberquilla@arm.com { 21312109SRekai.GonzalezAlberquilla@arm.com /* const_cast for not duplicating code above. */ 21412109SRekai.GonzalezAlberquilla@arm.com return const_cast<VecRegContainer&>(readVecReg(phys_reg)); 21512109SRekai.GonzalezAlberquilla@arm.com } 21612109SRekai.GonzalezAlberquilla@arm.com 21712109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register lane. */ 21812109SRekai.GonzalezAlberquilla@arm.com template <typename VecElem, int LaneIdx> 21912109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 22012109SRekai.GonzalezAlberquilla@arm.com readVecLane(PhysRegIdPtr phys_reg) const 22112109SRekai.GonzalezAlberquilla@arm.com { 22212109SRekai.GonzalezAlberquilla@arm.com return readVecReg(phys_reg).laneView<VecElem, LaneIdx>(); 22312109SRekai.GonzalezAlberquilla@arm.com } 22412109SRekai.GonzalezAlberquilla@arm.com 22512109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register lane. */ 22612109SRekai.GonzalezAlberquilla@arm.com template <typename VecElem> 22712109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 22812109SRekai.GonzalezAlberquilla@arm.com readVecLane(PhysRegIdPtr phys_reg) const 22912109SRekai.GonzalezAlberquilla@arm.com { 23012109SRekai.GonzalezAlberquilla@arm.com return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex()); 23112109SRekai.GonzalezAlberquilla@arm.com } 23212109SRekai.GonzalezAlberquilla@arm.com 23312109SRekai.GonzalezAlberquilla@arm.com /** Get a vector register lane for modification. */ 23412109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 23512109SRekai.GonzalezAlberquilla@arm.com void 23612109SRekai.GonzalezAlberquilla@arm.com setVecLane(PhysRegIdPtr phys_reg, const LD& val) 23712109SRekai.GonzalezAlberquilla@arm.com { 23812109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysReg()); 23912109SRekai.GonzalezAlberquilla@arm.com 24012109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n", 24112109SRekai.GonzalezAlberquilla@arm.com int(phys_reg->index()), phys_reg->elemIndex(), val); 24212109SRekai.GonzalezAlberquilla@arm.com 24312109SRekai.GonzalezAlberquilla@arm.com vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>( 24412109SRekai.GonzalezAlberquilla@arm.com phys_reg->elemIndex()) = val; 24512109SRekai.GonzalezAlberquilla@arm.com } 24612109SRekai.GonzalezAlberquilla@arm.com 24712109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector element. */ 24812109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElem(PhysRegIdPtr phys_reg) const 24912109SRekai.GonzalezAlberquilla@arm.com { 25012109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysElem()); 25112109SRekai.GonzalezAlberquilla@arm.com auto ret = vectorRegFile[phys_reg->index()].as<VecElem>(); 25212109SRekai.GonzalezAlberquilla@arm.com const VecElem& val = ret[phys_reg->elemIndex()]; 25312109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Access to element %d of vector register %i," 25412109SRekai.GonzalezAlberquilla@arm.com " has data %#x\n", phys_reg->elemIndex(), 25512109SRekai.GonzalezAlberquilla@arm.com int(phys_reg->index()), val); 25612109SRekai.GonzalezAlberquilla@arm.com 25712109SRekai.GonzalezAlberquilla@arm.com return val; 25812109SRekai.GonzalezAlberquilla@arm.com } 25912109SRekai.GonzalezAlberquilla@arm.com 2609920Syasuko.eckert@amd.com /** Reads a condition-code register. */ 26112105Snathanael.premillieu@arm.com CCReg readCCReg(PhysRegIdPtr phys_reg) 2629920Syasuko.eckert@amd.com { 26312105Snathanael.premillieu@arm.com assert(phys_reg->isCCPhysReg()); 2649920Syasuko.eckert@amd.com 2659920Syasuko.eckert@amd.com DPRINTF(IEW, "RegFile: Access to cc register %i, has " 26612106SRekai.GonzalezAlberquilla@arm.com "data %#x\n", phys_reg->index(), 26712106SRekai.GonzalezAlberquilla@arm.com ccRegFile[phys_reg->index()]); 2689920Syasuko.eckert@amd.com 26912106SRekai.GonzalezAlberquilla@arm.com return ccRegFile[phys_reg->index()]; 2709920Syasuko.eckert@amd.com } 2719920Syasuko.eckert@amd.com 2722292SN/A /** Sets an integer register to the given value. */ 27312105Snathanael.premillieu@arm.com void setIntReg(PhysRegIdPtr phys_reg, uint64_t val) 2741060SN/A { 27512105Snathanael.premillieu@arm.com assert(phys_reg->isIntPhysReg()); 2761061SN/A 2772690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 27812106SRekai.GonzalezAlberquilla@arm.com phys_reg->index(), val); 2791060SN/A 28012105Snathanael.premillieu@arm.com if (!phys_reg->isZeroReg()) 28112106SRekai.GonzalezAlberquilla@arm.com intRegFile[phys_reg->index()] = val; 2821060SN/A } 2831060SN/A 28412105Snathanael.premillieu@arm.com void setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val) 2852455SN/A { 28612105Snathanael.premillieu@arm.com assert(phys_reg->isFloatPhysReg()); 2872455SN/A 2882690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 28912106SRekai.GonzalezAlberquilla@arm.com phys_reg->index(), (uint64_t)val); 2902455SN/A 29112109SRekai.GonzalezAlberquilla@arm.com if (!phys_reg->isZeroReg()) 29213501Sgabeblack@google.com floatRegFile[phys_reg->index()] = val; 29312109SRekai.GonzalezAlberquilla@arm.com } 29412109SRekai.GonzalezAlberquilla@arm.com 29512109SRekai.GonzalezAlberquilla@arm.com /** Sets a vector register to the given value. */ 29612109SRekai.GonzalezAlberquilla@arm.com void setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) 29712109SRekai.GonzalezAlberquilla@arm.com { 29812109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysReg()); 29912109SRekai.GonzalezAlberquilla@arm.com 30012109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n", 30112109SRekai.GonzalezAlberquilla@arm.com int(phys_reg->index()), val.print()); 30212109SRekai.GonzalezAlberquilla@arm.com 30312109SRekai.GonzalezAlberquilla@arm.com vectorRegFile[phys_reg->index()] = val; 30412109SRekai.GonzalezAlberquilla@arm.com } 30512109SRekai.GonzalezAlberquilla@arm.com 30612109SRekai.GonzalezAlberquilla@arm.com /** Sets a vector register to the given value. */ 30712109SRekai.GonzalezAlberquilla@arm.com void setVecElem(PhysRegIdPtr phys_reg, const VecElem val) 30812109SRekai.GonzalezAlberquilla@arm.com { 30912109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysElem()); 31012109SRekai.GonzalezAlberquilla@arm.com 31112109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to" 31212109SRekai.GonzalezAlberquilla@arm.com " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val); 31312109SRekai.GonzalezAlberquilla@arm.com 31412109SRekai.GonzalezAlberquilla@arm.com vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] = 31512109SRekai.GonzalezAlberquilla@arm.com val; 3161060SN/A } 3171060SN/A 3189920Syasuko.eckert@amd.com /** Sets a condition-code register to the given value. */ 31912105Snathanael.premillieu@arm.com void setCCReg(PhysRegIdPtr phys_reg, CCReg val) 3209920Syasuko.eckert@amd.com { 32112105Snathanael.premillieu@arm.com assert(phys_reg->isCCPhysReg()); 3229920Syasuko.eckert@amd.com 3239920Syasuko.eckert@amd.com DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n", 32412106SRekai.GonzalezAlberquilla@arm.com phys_reg->index(), (uint64_t)val); 3259920Syasuko.eckert@amd.com 32612106SRekai.GonzalezAlberquilla@arm.com ccRegFile[phys_reg->index()] = val; 3279920Syasuko.eckert@amd.com } 32812109SRekai.GonzalezAlberquilla@arm.com 32912109SRekai.GonzalezAlberquilla@arm.com /** Get the PhysRegIds of the elems of a vector register. 33012109SRekai.GonzalezAlberquilla@arm.com * Auxiliary function to transition from Full vector mode to Elem mode. 33112109SRekai.GonzalezAlberquilla@arm.com */ 33212109SRekai.GonzalezAlberquilla@arm.com IdRange getRegElemIds(PhysRegIdPtr reg); 33312109SRekai.GonzalezAlberquilla@arm.com 33412109SRekai.GonzalezAlberquilla@arm.com /** 33512109SRekai.GonzalezAlberquilla@arm.com * Get the PhysRegIds of the elems of all vector registers. 33612109SRekai.GonzalezAlberquilla@arm.com * Auxiliary function to transition from Full vector mode to Elem mode 33712109SRekai.GonzalezAlberquilla@arm.com * and to initialise the rename map. 33812109SRekai.GonzalezAlberquilla@arm.com */ 33912109SRekai.GonzalezAlberquilla@arm.com IdRange getRegIds(RegClass cls); 34012109SRekai.GonzalezAlberquilla@arm.com 34112109SRekai.GonzalezAlberquilla@arm.com /** 34212109SRekai.GonzalezAlberquilla@arm.com * Get the true physical register id. 34312109SRekai.GonzalezAlberquilla@arm.com * As many parts work with PhysRegIdPtr, we need to be able to produce 34412109SRekai.GonzalezAlberquilla@arm.com * the pointer out of just class and register idx. 34512109SRekai.GonzalezAlberquilla@arm.com */ 34612109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr getTrueId(PhysRegIdPtr reg); 3471060SN/A}; 3481060SN/A 3499915Ssteve.reinhardt@amd.com 3509915Ssteve.reinhardt@amd.com#endif //__CPU_O3_REGFILE_HH__ 351