regfile.hh revision 12109
11689SN/A/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2016 ARM Limited 312109SRekai.GonzalezAlberquilla@arm.com * All rights reserved 412109SRekai.GonzalezAlberquilla@arm.com * 512109SRekai.GonzalezAlberquilla@arm.com * The license below extends only to copyright in the software and shall 612109SRekai.GonzalezAlberquilla@arm.com * not be construed as granting a license to any other intellectual 712109SRekai.GonzalezAlberquilla@arm.com * property including but not limited to intellectual property relating 812109SRekai.GonzalezAlberquilla@arm.com * to a hardware implementation of the functionality of the software 912109SRekai.GonzalezAlberquilla@arm.com * licensed hereunder. You may use the software subject to the license 1012109SRekai.GonzalezAlberquilla@arm.com * terms below provided that you ensure that this notice is replicated 1112109SRekai.GonzalezAlberquilla@arm.com * unmodified and in its entirety in all distributions of the software, 1212109SRekai.GonzalezAlberquilla@arm.com * modified or unmodified, in source code or in binary form. 1312109SRekai.GonzalezAlberquilla@arm.com * 141689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 159915Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422665Ssaidi@eecs.umich.edu * Gabe Black 431689SN/A */ 441689SN/A 452292SN/A#ifndef __CPU_O3_REGFILE_HH__ 462292SN/A#define __CPU_O3_REGFILE_HH__ 471060SN/A 486658Snate@binkert.org#include <vector> 496658Snate@binkert.org 502165SN/A#include "arch/isa_traits.hh" 518793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 522669Sktlim@umich.edu#include "arch/types.hh" 531681SN/A#include "base/trace.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 551717SN/A#include "cpu/o3/comm.hh" 568232Snate@binkert.org#include "debug/IEW.hh" 5712109SRekai.GonzalezAlberquilla@arm.com#include "enums/VecRegRenameMode.hh" 581060SN/A 599919Ssteve.reinhardt@amd.comclass UnifiedFreeList; 609919Ssteve.reinhardt@amd.com 612292SN/A/** 622292SN/A * Simple physical register file class. 632292SN/A */ 641060SN/Aclass PhysRegFile 651060SN/A{ 669915Ssteve.reinhardt@amd.com private: 679915Ssteve.reinhardt@amd.com 682107SN/A typedef TheISA::IntReg IntReg; 692107SN/A typedef TheISA::FloatReg FloatReg; 702669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 719920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 7212109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 7312109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 7412109SRekai.GonzalezAlberquilla@arm.com using PhysIds = std::vector<PhysRegId>; 7512109SRekai.GonzalezAlberquilla@arm.com using VecMode = Enums::VecRegRenameMode; 7612109SRekai.GonzalezAlberquilla@arm.com public: 7712109SRekai.GonzalezAlberquilla@arm.com using IdRange = std::pair<PhysIds::const_iterator, 7812109SRekai.GonzalezAlberquilla@arm.com PhysIds::const_iterator>; 7912109SRekai.GonzalezAlberquilla@arm.com private: 8012109SRekai.GonzalezAlberquilla@arm.com static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; 812159SN/A 822669Sktlim@umich.edu typedef union { 832669Sktlim@umich.edu FloatReg d; 842669Sktlim@umich.edu FloatRegBits q; 852669Sktlim@umich.edu } PhysFloatReg; 861060SN/A 879915Ssteve.reinhardt@amd.com /** Integer register file. */ 889919Ssteve.reinhardt@amd.com std::vector<IntReg> intRegFile; 8912105Snathanael.premillieu@arm.com std::vector<PhysRegId> intRegIds; 901060SN/A 919915Ssteve.reinhardt@amd.com /** Floating point register file. */ 929919Ssteve.reinhardt@amd.com std::vector<PhysFloatReg> floatRegFile; 9312105Snathanael.premillieu@arm.com std::vector<PhysRegId> floatRegIds; 949915Ssteve.reinhardt@amd.com 9512109SRekai.GonzalezAlberquilla@arm.com /** Vector register file. */ 9612109SRekai.GonzalezAlberquilla@arm.com std::vector<VecRegContainer> vectorRegFile; 9712109SRekai.GonzalezAlberquilla@arm.com std::vector<PhysRegId> vecRegIds; 9812109SRekai.GonzalezAlberquilla@arm.com std::vector<PhysRegId> vecElemIds; 9912109SRekai.GonzalezAlberquilla@arm.com 1009920Syasuko.eckert@amd.com /** Condition-code register file. */ 1019920Syasuko.eckert@amd.com std::vector<CCReg> ccRegFile; 10212105Snathanael.premillieu@arm.com std::vector<PhysRegId> ccRegIds; 10312105Snathanael.premillieu@arm.com 10412105Snathanael.premillieu@arm.com /** Misc Reg Ids */ 10512105Snathanael.premillieu@arm.com std::vector<PhysRegId> miscRegIds; 1069920Syasuko.eckert@amd.com 1079915Ssteve.reinhardt@amd.com /** 10812105Snathanael.premillieu@arm.com * Number of physical general purpose registers 1099915Ssteve.reinhardt@amd.com */ 11012105Snathanael.premillieu@arm.com unsigned numPhysicalIntRegs; 1119915Ssteve.reinhardt@amd.com 1129920Syasuko.eckert@amd.com /** 11312109SRekai.GonzalezAlberquilla@arm.com * Number of physical floating point registers 1149920Syasuko.eckert@amd.com */ 11512105Snathanael.premillieu@arm.com unsigned numPhysicalFloatRegs; 11612105Snathanael.premillieu@arm.com 11712105Snathanael.premillieu@arm.com /** 11812109SRekai.GonzalezAlberquilla@arm.com * Number of physical vector registers 11912109SRekai.GonzalezAlberquilla@arm.com */ 12012109SRekai.GonzalezAlberquilla@arm.com unsigned numPhysicalVecRegs; 12112109SRekai.GonzalezAlberquilla@arm.com 12212109SRekai.GonzalezAlberquilla@arm.com /** 12312109SRekai.GonzalezAlberquilla@arm.com * Number of physical vector element registers 12412109SRekai.GonzalezAlberquilla@arm.com */ 12512109SRekai.GonzalezAlberquilla@arm.com unsigned numPhysicalVecElemRegs; 12612109SRekai.GonzalezAlberquilla@arm.com 12712109SRekai.GonzalezAlberquilla@arm.com /** 12812109SRekai.GonzalezAlberquilla@arm.com * Number of physical CC registers 12912105Snathanael.premillieu@arm.com */ 13012105Snathanael.premillieu@arm.com unsigned numPhysicalCCRegs; 1319920Syasuko.eckert@amd.com 1329915Ssteve.reinhardt@amd.com /** Total number of physical registers. */ 1339915Ssteve.reinhardt@amd.com unsigned totalNumRegs; 1349915Ssteve.reinhardt@amd.com 13512109SRekai.GonzalezAlberquilla@arm.com /** Mode in which vector registers are addressed. */ 13612109SRekai.GonzalezAlberquilla@arm.com VecMode vecMode; 13712109SRekai.GonzalezAlberquilla@arm.com 1381060SN/A public: 1392292SN/A /** 1402292SN/A * Constructs a physical register file with the specified amount of 1412292SN/A * integer and floating point registers. 1422292SN/A */ 1439915Ssteve.reinhardt@amd.com PhysRegFile(unsigned _numPhysicalIntRegs, 1449920Syasuko.eckert@amd.com unsigned _numPhysicalFloatRegs, 14512109SRekai.GonzalezAlberquilla@arm.com unsigned _numPhysicalVecRegs, 14612109SRekai.GonzalezAlberquilla@arm.com unsigned _numPhysicalCCRegs, 14712109SRekai.GonzalezAlberquilla@arm.com VecMode vmode 14812109SRekai.GonzalezAlberquilla@arm.com ); 1491060SN/A 1509086Sandreas.hansson@arm.com /** 1519086Sandreas.hansson@arm.com * Destructor to free resources 1529086Sandreas.hansson@arm.com */ 1539919Ssteve.reinhardt@amd.com ~PhysRegFile() {} 1549919Ssteve.reinhardt@amd.com 1559919Ssteve.reinhardt@amd.com /** Initialize the free list */ 1569919Ssteve.reinhardt@amd.com void initFreeList(UnifiedFreeList *freeList); 1579086Sandreas.hansson@arm.com 1589915Ssteve.reinhardt@amd.com /** @return the number of integer physical registers. */ 15912105Snathanael.premillieu@arm.com unsigned numIntPhysRegs() const { return numPhysicalIntRegs; } 1609915Ssteve.reinhardt@amd.com 1619915Ssteve.reinhardt@amd.com /** @return the number of floating-point physical registers. */ 16212105Snathanael.premillieu@arm.com unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; } 16312109SRekai.GonzalezAlberquilla@arm.com /** @return the number of vector physical registers. */ 16412109SRekai.GonzalezAlberquilla@arm.com unsigned numVecPhysRegs() const { return numPhysicalVecRegs; } 16512109SRekai.GonzalezAlberquilla@arm.com 16612109SRekai.GonzalezAlberquilla@arm.com /** @return the number of vector physical registers. */ 16712109SRekai.GonzalezAlberquilla@arm.com unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; } 1689920Syasuko.eckert@amd.com 1699920Syasuko.eckert@amd.com /** @return the number of condition-code physical registers. */ 17012105Snathanael.premillieu@arm.com unsigned numCCPhysRegs() const { return numPhysicalCCRegs; } 1719915Ssteve.reinhardt@amd.com 1729915Ssteve.reinhardt@amd.com /** @return the total number of physical registers. */ 1739915Ssteve.reinhardt@amd.com unsigned totalNumPhysRegs() const { return totalNumRegs; } 1749915Ssteve.reinhardt@amd.com 17512105Snathanael.premillieu@arm.com /** Gets a misc register PhysRegIdPtr. */ 17612105Snathanael.premillieu@arm.com PhysRegIdPtr getMiscRegId(RegIndex reg_idx) { 17712105Snathanael.premillieu@arm.com return &miscRegIds[reg_idx]; 1789915Ssteve.reinhardt@amd.com } 1791060SN/A 1802292SN/A /** Reads an integer register. */ 18112105Snathanael.premillieu@arm.com uint64_t readIntReg(PhysRegIdPtr phys_reg) const 1821060SN/A { 18312105Snathanael.premillieu@arm.com assert(phys_reg->isIntPhysReg()); 1841061SN/A 1851060SN/A DPRINTF(IEW, "RegFile: Access to int register %i, has data " 18612106SRekai.GonzalezAlberquilla@arm.com "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]); 18712106SRekai.GonzalezAlberquilla@arm.com return intRegFile[phys_reg->index()]; 1881060SN/A } 1891060SN/A 1902292SN/A /** Reads a floating point register (double precision). */ 19112105Snathanael.premillieu@arm.com FloatReg readFloatReg(PhysRegIdPtr phys_reg) const 1921060SN/A { 19312105Snathanael.premillieu@arm.com assert(phys_reg->isFloatPhysReg()); 1941060SN/A 1952455SN/A DPRINTF(IEW, "RegFile: Access to float register %i, has " 19612106SRekai.GonzalezAlberquilla@arm.com "data %#x\n", phys_reg->index(), 19712106SRekai.GonzalezAlberquilla@arm.com floatRegFile[phys_reg->index()].q); 1982455SN/A 19912106SRekai.GonzalezAlberquilla@arm.com return floatRegFile[phys_reg->index()].d; 2001060SN/A } 2011060SN/A 20212105Snathanael.premillieu@arm.com FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg) const 2032455SN/A { 20412105Snathanael.premillieu@arm.com assert(phys_reg->isFloatPhysReg()); 2059915Ssteve.reinhardt@amd.com 20612106SRekai.GonzalezAlberquilla@arm.com FloatRegBits floatRegBits = floatRegFile[phys_reg->index()].q; 2072455SN/A 2082455SN/A DPRINTF(IEW, "RegFile: Access to float register %i as int, " 20912106SRekai.GonzalezAlberquilla@arm.com "has data %#x\n", phys_reg->index(), 21012105Snathanael.premillieu@arm.com (uint64_t)floatRegBits); 2112455SN/A 2122455SN/A return floatRegBits; 2131060SN/A } 2141060SN/A 21512109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register. */ 21612109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecReg(PhysRegIdPtr phys_reg) const 21712109SRekai.GonzalezAlberquilla@arm.com { 21812109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysReg()); 21912109SRekai.GonzalezAlberquilla@arm.com 22012109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Access to vector register %i, has " 22112109SRekai.GonzalezAlberquilla@arm.com "data %s\n", int(phys_reg->index()), 22212109SRekai.GonzalezAlberquilla@arm.com vectorRegFile[phys_reg->index()].as<VecElem>().print()); 22312109SRekai.GonzalezAlberquilla@arm.com 22412109SRekai.GonzalezAlberquilla@arm.com return vectorRegFile[phys_reg->index()]; 22512109SRekai.GonzalezAlberquilla@arm.com } 22612109SRekai.GonzalezAlberquilla@arm.com 22712109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register for modification. */ 22812109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecReg(PhysRegIdPtr phys_reg) 22912109SRekai.GonzalezAlberquilla@arm.com { 23012109SRekai.GonzalezAlberquilla@arm.com /* const_cast for not duplicating code above. */ 23112109SRekai.GonzalezAlberquilla@arm.com return const_cast<VecRegContainer&>(readVecReg(phys_reg)); 23212109SRekai.GonzalezAlberquilla@arm.com } 23312109SRekai.GonzalezAlberquilla@arm.com 23412109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register lane. */ 23512109SRekai.GonzalezAlberquilla@arm.com template <typename VecElem, int LaneIdx> 23612109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 23712109SRekai.GonzalezAlberquilla@arm.com readVecLane(PhysRegIdPtr phys_reg) const 23812109SRekai.GonzalezAlberquilla@arm.com { 23912109SRekai.GonzalezAlberquilla@arm.com return readVecReg(phys_reg).laneView<VecElem, LaneIdx>(); 24012109SRekai.GonzalezAlberquilla@arm.com } 24112109SRekai.GonzalezAlberquilla@arm.com 24212109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector register lane. */ 24312109SRekai.GonzalezAlberquilla@arm.com template <typename VecElem> 24412109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 24512109SRekai.GonzalezAlberquilla@arm.com readVecLane(PhysRegIdPtr phys_reg) const 24612109SRekai.GonzalezAlberquilla@arm.com { 24712109SRekai.GonzalezAlberquilla@arm.com return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex()); 24812109SRekai.GonzalezAlberquilla@arm.com } 24912109SRekai.GonzalezAlberquilla@arm.com 25012109SRekai.GonzalezAlberquilla@arm.com /** Get a vector register lane for modification. */ 25112109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 25212109SRekai.GonzalezAlberquilla@arm.com void 25312109SRekai.GonzalezAlberquilla@arm.com setVecLane(PhysRegIdPtr phys_reg, const LD& val) 25412109SRekai.GonzalezAlberquilla@arm.com { 25512109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysReg()); 25612109SRekai.GonzalezAlberquilla@arm.com 25712109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n", 25812109SRekai.GonzalezAlberquilla@arm.com int(phys_reg->index()), phys_reg->elemIndex(), val); 25912109SRekai.GonzalezAlberquilla@arm.com 26012109SRekai.GonzalezAlberquilla@arm.com vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>( 26112109SRekai.GonzalezAlberquilla@arm.com phys_reg->elemIndex()) = val; 26212109SRekai.GonzalezAlberquilla@arm.com } 26312109SRekai.GonzalezAlberquilla@arm.com 26412109SRekai.GonzalezAlberquilla@arm.com /** Reads a vector element. */ 26512109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElem(PhysRegIdPtr phys_reg) const 26612109SRekai.GonzalezAlberquilla@arm.com { 26712109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysElem()); 26812109SRekai.GonzalezAlberquilla@arm.com auto ret = vectorRegFile[phys_reg->index()].as<VecElem>(); 26912109SRekai.GonzalezAlberquilla@arm.com const VecElem& val = ret[phys_reg->elemIndex()]; 27012109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Access to element %d of vector register %i," 27112109SRekai.GonzalezAlberquilla@arm.com " has data %#x\n", phys_reg->elemIndex(), 27212109SRekai.GonzalezAlberquilla@arm.com int(phys_reg->index()), val); 27312109SRekai.GonzalezAlberquilla@arm.com 27412109SRekai.GonzalezAlberquilla@arm.com return val; 27512109SRekai.GonzalezAlberquilla@arm.com } 27612109SRekai.GonzalezAlberquilla@arm.com 2779920Syasuko.eckert@amd.com /** Reads a condition-code register. */ 27812105Snathanael.premillieu@arm.com CCReg readCCReg(PhysRegIdPtr phys_reg) 2799920Syasuko.eckert@amd.com { 28012105Snathanael.premillieu@arm.com assert(phys_reg->isCCPhysReg()); 2819920Syasuko.eckert@amd.com 2829920Syasuko.eckert@amd.com DPRINTF(IEW, "RegFile: Access to cc register %i, has " 28312106SRekai.GonzalezAlberquilla@arm.com "data %#x\n", phys_reg->index(), 28412106SRekai.GonzalezAlberquilla@arm.com ccRegFile[phys_reg->index()]); 2859920Syasuko.eckert@amd.com 28612106SRekai.GonzalezAlberquilla@arm.com return ccRegFile[phys_reg->index()]; 2879920Syasuko.eckert@amd.com } 2889920Syasuko.eckert@amd.com 2892292SN/A /** Sets an integer register to the given value. */ 29012105Snathanael.premillieu@arm.com void setIntReg(PhysRegIdPtr phys_reg, uint64_t val) 2911060SN/A { 29212105Snathanael.premillieu@arm.com assert(phys_reg->isIntPhysReg()); 2931061SN/A 2942690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 29512106SRekai.GonzalezAlberquilla@arm.com phys_reg->index(), val); 2961060SN/A 29712105Snathanael.premillieu@arm.com if (!phys_reg->isZeroReg()) 29812106SRekai.GonzalezAlberquilla@arm.com intRegFile[phys_reg->index()] = val; 2991060SN/A } 3001060SN/A 3012292SN/A /** Sets a double precision floating point register to the given value. */ 30212105Snathanael.premillieu@arm.com void setFloatReg(PhysRegIdPtr phys_reg, FloatReg val) 3031060SN/A { 30412105Snathanael.premillieu@arm.com assert(phys_reg->isFloatPhysReg()); 3051061SN/A 3062690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 30712106SRekai.GonzalezAlberquilla@arm.com phys_reg->index(), (uint64_t)val); 3081060SN/A 30912105Snathanael.premillieu@arm.com if (!phys_reg->isZeroReg()) 31012106SRekai.GonzalezAlberquilla@arm.com floatRegFile[phys_reg->index()].d = val; 3111060SN/A } 3121060SN/A 31312105Snathanael.premillieu@arm.com void setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val) 3142455SN/A { 31512105Snathanael.premillieu@arm.com assert(phys_reg->isFloatPhysReg()); 3162455SN/A 3172690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 31812106SRekai.GonzalezAlberquilla@arm.com phys_reg->index(), (uint64_t)val); 3192455SN/A 32012109SRekai.GonzalezAlberquilla@arm.com if (!phys_reg->isZeroReg()) 32112109SRekai.GonzalezAlberquilla@arm.com floatRegFile[phys_reg->index()].q = val; 32212109SRekai.GonzalezAlberquilla@arm.com } 32312109SRekai.GonzalezAlberquilla@arm.com 32412109SRekai.GonzalezAlberquilla@arm.com /** Sets a vector register to the given value. */ 32512109SRekai.GonzalezAlberquilla@arm.com void setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) 32612109SRekai.GonzalezAlberquilla@arm.com { 32712109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysReg()); 32812109SRekai.GonzalezAlberquilla@arm.com 32912109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n", 33012109SRekai.GonzalezAlberquilla@arm.com int(phys_reg->index()), val.print()); 33112109SRekai.GonzalezAlberquilla@arm.com 33212109SRekai.GonzalezAlberquilla@arm.com vectorRegFile[phys_reg->index()] = val; 33312109SRekai.GonzalezAlberquilla@arm.com } 33412109SRekai.GonzalezAlberquilla@arm.com 33512109SRekai.GonzalezAlberquilla@arm.com /** Sets a vector register to the given value. */ 33612109SRekai.GonzalezAlberquilla@arm.com void setVecElem(PhysRegIdPtr phys_reg, const VecElem val) 33712109SRekai.GonzalezAlberquilla@arm.com { 33812109SRekai.GonzalezAlberquilla@arm.com assert(phys_reg->isVectorPhysElem()); 33912109SRekai.GonzalezAlberquilla@arm.com 34012109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to" 34112109SRekai.GonzalezAlberquilla@arm.com " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val); 34212109SRekai.GonzalezAlberquilla@arm.com 34312109SRekai.GonzalezAlberquilla@arm.com vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] = 34412109SRekai.GonzalezAlberquilla@arm.com val; 3451060SN/A } 3461060SN/A 3479920Syasuko.eckert@amd.com /** Sets a condition-code register to the given value. */ 34812105Snathanael.premillieu@arm.com void setCCReg(PhysRegIdPtr phys_reg, CCReg val) 3499920Syasuko.eckert@amd.com { 35012105Snathanael.premillieu@arm.com assert(phys_reg->isCCPhysReg()); 3519920Syasuko.eckert@amd.com 3529920Syasuko.eckert@amd.com DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n", 35312106SRekai.GonzalezAlberquilla@arm.com phys_reg->index(), (uint64_t)val); 3549920Syasuko.eckert@amd.com 35512106SRekai.GonzalezAlberquilla@arm.com ccRegFile[phys_reg->index()] = val; 3569920Syasuko.eckert@amd.com } 35712109SRekai.GonzalezAlberquilla@arm.com 35812109SRekai.GonzalezAlberquilla@arm.com /** Get the PhysRegIds of the elems of a vector register. 35912109SRekai.GonzalezAlberquilla@arm.com * Auxiliary function to transition from Full vector mode to Elem mode. 36012109SRekai.GonzalezAlberquilla@arm.com */ 36112109SRekai.GonzalezAlberquilla@arm.com IdRange getRegElemIds(PhysRegIdPtr reg); 36212109SRekai.GonzalezAlberquilla@arm.com 36312109SRekai.GonzalezAlberquilla@arm.com /** 36412109SRekai.GonzalezAlberquilla@arm.com * Get the PhysRegIds of the elems of all vector registers. 36512109SRekai.GonzalezAlberquilla@arm.com * Auxiliary function to transition from Full vector mode to Elem mode 36612109SRekai.GonzalezAlberquilla@arm.com * and to initialise the rename map. 36712109SRekai.GonzalezAlberquilla@arm.com */ 36812109SRekai.GonzalezAlberquilla@arm.com IdRange getRegIds(RegClass cls); 36912109SRekai.GonzalezAlberquilla@arm.com 37012109SRekai.GonzalezAlberquilla@arm.com /** 37112109SRekai.GonzalezAlberquilla@arm.com * Get the true physical register id. 37212109SRekai.GonzalezAlberquilla@arm.com * As many parts work with PhysRegIdPtr, we need to be able to produce 37312109SRekai.GonzalezAlberquilla@arm.com * the pointer out of just class and register idx. 37412109SRekai.GonzalezAlberquilla@arm.com */ 37512109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr getTrueId(PhysRegIdPtr reg); 3761060SN/A}; 3771060SN/A 3789915Ssteve.reinhardt@amd.com 3799915Ssteve.reinhardt@amd.com#endif //__CPU_O3_REGFILE_HH__ 380