mem_dep_unit_impl.hh revision 8516:a9c0d2ab490a
12817Sksewell@umich.edu/*
22817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan
32817Sksewell@umich.edu * All rights reserved.
42817Sksewell@umich.edu *
52817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without
62817Sksewell@umich.edu * modification, are permitted provided that the following conditions are
72817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright
82817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer;
92817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright
102817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the
112817Sksewell@umich.edu * documentation and/or other materials provided with the distribution;
122817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its
132817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from
142817Sksewell@umich.edu * this software without specific prior written permission.
152817Sksewell@umich.edu *
162817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272817Sksewell@umich.edu *
282817Sksewell@umich.edu * Authors: Kevin Lim
292817Sksewell@umich.edu */
302817Sksewell@umich.edu
312817Sksewell@umich.edu#include <map>
322817Sksewell@umich.edu
332817Sksewell@umich.edu#include "cpu/o3/inst_queue.hh"
342935Sksewell@umich.edu#include "cpu/o3/mem_dep_unit.hh"
352817Sksewell@umich.edu#include "debug/MemDepUnit.hh"
362817Sksewell@umich.edu#include "params/DerivO3CPU.hh"
372834Sksewell@umich.edu
382834Sksewell@umich.edutemplate <class MemDepPred, class Impl>
392834Sksewell@umich.eduMemDepUnit<MemDepPred, Impl>::MemDepUnit()
402834Sksewell@umich.edu    : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
412834Sksewell@umich.edu      storeBarrierSN(0), iqPtr(NULL)
422834Sksewell@umich.edu{
432834Sksewell@umich.edu}
442817Sksewell@umich.edu
452817Sksewell@umich.edutemplate <class MemDepPred, class Impl>
462817Sksewell@umich.eduMemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
472817Sksewell@umich.edu    : _name(params->name + ".memdepunit"),
482817Sksewell@umich.edu      depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
492817Sksewell@umich.edu      loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
502817Sksewell@umich.edu{
512817Sksewell@umich.edu    DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
522817Sksewell@umich.edu}
532817Sksewell@umich.edu
542817Sksewell@umich.edutemplate <class MemDepPred, class Impl>
552817Sksewell@umich.eduMemDepUnit<MemDepPred, Impl>::~MemDepUnit()
562817Sksewell@umich.edu{
572817Sksewell@umich.edu    for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
582817Sksewell@umich.edu
592817Sksewell@umich.edu        ListIt inst_list_it = instList[tid].begin();
602817Sksewell@umich.edu
612817Sksewell@umich.edu        MemDepHashIt hash_it;
622817Sksewell@umich.edu
632817Sksewell@umich.edu        while (!instList[tid].empty()) {
642817Sksewell@umich.edu            hash_it = memDepHash.find((*inst_list_it)->seqNum);
652817Sksewell@umich.edu
662817Sksewell@umich.edu            assert(hash_it != memDepHash.end());
672817Sksewell@umich.edu
682817Sksewell@umich.edu            memDepHash.erase(hash_it);
692817Sksewell@umich.edu
702817Sksewell@umich.edu            instList[tid].erase(inst_list_it++);
712817Sksewell@umich.edu        }
722817Sksewell@umich.edu    }
732817Sksewell@umich.edu
742817Sksewell@umich.edu#ifdef DEBUG
752817Sksewell@umich.edu    assert(MemDepEntry::memdep_count == 0);
762817Sksewell@umich.edu#endif
772817Sksewell@umich.edu}
782817Sksewell@umich.edu
792817Sksewell@umich.edutemplate <class MemDepPred, class Impl>
802817Sksewell@umich.eduvoid
812817Sksewell@umich.eduMemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid)
822817Sksewell@umich.edu{
832817Sksewell@umich.edu    DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
842817Sksewell@umich.edu
852817Sksewell@umich.edu    _name = csprintf("%s.memDep%d", params->name, tid);
862817Sksewell@umich.edu    id = tid;
872817Sksewell@umich.edu
882817Sksewell@umich.edu    depPred.init(params->SSITSize, params->LFSTSize);
892817Sksewell@umich.edu}
902817Sksewell@umich.edu
912817Sksewell@umich.edutemplate <class MemDepPred, class Impl>
922817Sksewell@umich.eduvoid
932817Sksewell@umich.eduMemDepUnit<MemDepPred, Impl>::regStats()
942817Sksewell@umich.edu{
952817Sksewell@umich.edu    insertedLoads
962817Sksewell@umich.edu        .name(name() + ".insertedLoads")
972817Sksewell@umich.edu        .desc("Number of loads inserted to the mem dependence unit.");
982817Sksewell@umich.edu
992817Sksewell@umich.edu    insertedStores
1002817Sksewell@umich.edu        .name(name() + ".insertedStores")
1012817Sksewell@umich.edu        .desc("Number of stores inserted to the mem dependence unit.");
1022817Sksewell@umich.edu
1032817Sksewell@umich.edu    conflictingLoads
1042817Sksewell@umich.edu        .name(name() + ".conflictingLoads")
1052817Sksewell@umich.edu        .desc("Number of conflicting loads.");
1062817Sksewell@umich.edu
1072817Sksewell@umich.edu    conflictingStores
1082817Sksewell@umich.edu        .name(name() + ".conflictingStores")
1092817Sksewell@umich.edu        .desc("Number of conflicting stores.");
1102817Sksewell@umich.edu}
1112817Sksewell@umich.edu
1122817Sksewell@umich.edutemplate <class MemDepPred, class Impl>
1132817Sksewell@umich.eduvoid
1142817Sksewell@umich.eduMemDepUnit<MemDepPred, Impl>::switchOut()
1152875Sksewell@umich.edu{
1162817Sksewell@umich.edu    assert(instList[0].empty());
1172817Sksewell@umich.edu    assert(instsToReplay.empty());
1182817Sksewell@umich.edu    assert(memDepHash.empty());
1192817Sksewell@umich.edu    // Clear any state.
1202817Sksewell@umich.edu    for (int i = 0; i < Impl::MaxThreads; ++i) {
1212817Sksewell@umich.edu        instList[i].clear();
1222817Sksewell@umich.edu    }
1232817Sksewell@umich.edu    instsToReplay.clear();
1242817Sksewell@umich.edu    memDepHash.clear();
1252817Sksewell@umich.edu}
1262817Sksewell@umich.edu
1272817Sksewell@umich.edutemplate <class MemDepPred, class Impl>
1282817Sksewell@umich.eduvoid
1292817Sksewell@umich.eduMemDepUnit<MemDepPred, Impl>::takeOverFrom()
1302817Sksewell@umich.edu{
1312817Sksewell@umich.edu    // Be sure to reset all state.
1322817Sksewell@umich.edu    loadBarrier = storeBarrier = false;
1332817Sksewell@umich.edu    loadBarrierSN = storeBarrierSN = 0;
1342817Sksewell@umich.edu    depPred.clear();
1352817Sksewell@umich.edu}
1362817Sksewell@umich.edu
1372817Sksewell@umich.edutemplate <class MemDepPred, class Impl>
1382817Sksewell@umich.eduvoid
1392817Sksewell@umich.eduMemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
1402817Sksewell@umich.edu{
1412817Sksewell@umich.edu    iqPtr = iq_ptr;
1422817Sksewell@umich.edu}
1432817Sksewell@umich.edu
1442817Sksewell@umich.edutemplate <class MemDepPred, class Impl>
1452817Sksewell@umich.eduvoid
1462817Sksewell@umich.eduMemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
1472817Sksewell@umich.edu{
1482817Sksewell@umich.edu    ThreadID tid = inst->threadNumber;
1492817Sksewell@umich.edu
1502817Sksewell@umich.edu    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
1512817Sksewell@umich.edu
1522817Sksewell@umich.edu    // Add the MemDepEntry to the hash.
1532817Sksewell@umich.edu    memDepHash.insert(
1542817Sksewell@umich.edu        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
1552817Sksewell@umich.edu#ifdef DEBUG
1562817Sksewell@umich.edu    MemDepEntry::memdep_insert++;
1572817Sksewell@umich.edu#endif
1582817Sksewell@umich.edu
1592817Sksewell@umich.edu    instList[tid].push_back(inst);
1602817Sksewell@umich.edu
1612817Sksewell@umich.edu    inst_entry->listIt = --(instList[tid].end());
1622817Sksewell@umich.edu
1632817Sksewell@umich.edu    // Check any barriers and the dependence predictor for any
1642817Sksewell@umich.edu    // producing memrefs/stores.
1652817Sksewell@umich.edu    InstSeqNum producing_store;
1662817Sksewell@umich.edu    if (inst->isLoad() && loadBarrier) {
1672817Sksewell@umich.edu        DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
1682817Sksewell@umich.edu                loadBarrierSN);
1692817Sksewell@umich.edu        producing_store = loadBarrierSN;
1702817Sksewell@umich.edu    } else if (inst->isStore() && storeBarrier) {
1712817Sksewell@umich.edu        DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
1722817Sksewell@umich.edu                storeBarrierSN);
1732817Sksewell@umich.edu        producing_store = storeBarrierSN;
1742817Sksewell@umich.edu    } else {
1752817Sksewell@umich.edu        producing_store = depPred.checkInst(inst->instAddr());
1762817Sksewell@umich.edu    }
1772817Sksewell@umich.edu
1782817Sksewell@umich.edu    MemDepEntryPtr store_entry = NULL;
1792817Sksewell@umich.edu
1802817Sksewell@umich.edu    // If there is a producing store, try to find the entry.
1812817Sksewell@umich.edu    if (producing_store != 0) {
1822817Sksewell@umich.edu        DPRINTF(MemDepUnit, "Searching for producer\n");
1832817Sksewell@umich.edu        MemDepHashIt hash_it = memDepHash.find(producing_store);
1842817Sksewell@umich.edu
1852817Sksewell@umich.edu        if (hash_it != memDepHash.end()) {
1862817Sksewell@umich.edu            store_entry = (*hash_it).second;
1872817Sksewell@umich.edu            DPRINTF(MemDepUnit, "Proucer found\n");
1882817Sksewell@umich.edu        }
1892817Sksewell@umich.edu    }
1902817Sksewell@umich.edu
1912817Sksewell@umich.edu    // If no store entry, then instruction can issue as soon as the registers
1922817Sksewell@umich.edu    // are ready.
1932817Sksewell@umich.edu    if (!store_entry) {
1942817Sksewell@umich.edu        DPRINTF(MemDepUnit, "No dependency for inst PC "
1952817Sksewell@umich.edu                "%s [sn:%lli].\n", inst->pcState(), inst->seqNum);
1962817Sksewell@umich.edu
1972817Sksewell@umich.edu        inst_entry->memDepReady = true;
1982817Sksewell@umich.edu
1992817Sksewell@umich.edu        if (inst->readyToIssue()) {
2002817Sksewell@umich.edu            inst_entry->regsReady = true;
2012817Sksewell@umich.edu
2022817Sksewell@umich.edu            moveToReady(inst_entry);
2032817Sksewell@umich.edu        }
2042817Sksewell@umich.edu    } else {
2052817Sksewell@umich.edu        // Otherwise make the instruction dependent on the store/barrier.
2062817Sksewell@umich.edu        DPRINTF(MemDepUnit, "Adding to dependency list; "
2072817Sksewell@umich.edu                "inst PC %s is dependent on [sn:%lli].\n",
2082817Sksewell@umich.edu                inst->pcState(), producing_store);
2092817Sksewell@umich.edu
2102817Sksewell@umich.edu        if (inst->readyToIssue()) {
2112817Sksewell@umich.edu            inst_entry->regsReady = true;
2122817Sksewell@umich.edu        }
2132817Sksewell@umich.edu
2142817Sksewell@umich.edu        // Clear the bit saying this instruction can issue.
2152817Sksewell@umich.edu        inst->clearCanIssue();
2162817Sksewell@umich.edu
2172817Sksewell@umich.edu        // Add this instruction to the list of dependents.
2182817Sksewell@umich.edu        store_entry->dependInsts.push_back(inst_entry);
2192817Sksewell@umich.edu
2202817Sksewell@umich.edu        if (inst->isLoad()) {
2212817Sksewell@umich.edu            ++conflictingLoads;
2222817Sksewell@umich.edu        } else {
2232817Sksewell@umich.edu            ++conflictingStores;
2242817Sksewell@umich.edu        }
2252817Sksewell@umich.edu    }
2262817Sksewell@umich.edu
2272817Sksewell@umich.edu    if (inst->isStore()) {
2282817Sksewell@umich.edu        DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
2292817Sksewell@umich.edu                inst->pcState(), inst->seqNum);
2302817Sksewell@umich.edu
2312817Sksewell@umich.edu        depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
2322817Sksewell@umich.edu
2332817Sksewell@umich.edu        ++insertedStores;
2342817Sksewell@umich.edu    } else if (inst->isLoad()) {
2352817Sksewell@umich.edu        ++insertedLoads;
2362817Sksewell@umich.edu    } else {
2372817Sksewell@umich.edu        panic("Unknown type! (most likely a barrier).");
2382817Sksewell@umich.edu    }
2392817Sksewell@umich.edu}
2402817Sksewell@umich.edu
2412817Sksewell@umich.edutemplate <class MemDepPred, class Impl>
2422817Sksewell@umich.eduvoid
2432817Sksewell@umich.eduMemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
2442817Sksewell@umich.edu{
2452817Sksewell@umich.edu    ThreadID tid = inst->threadNumber;
2462817Sksewell@umich.edu
2472817Sksewell@umich.edu    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
2482817Sksewell@umich.edu
2492817Sksewell@umich.edu    // Insert the MemDepEntry into the hash.
2502817Sksewell@umich.edu    memDepHash.insert(
251        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
252#ifdef DEBUG
253    MemDepEntry::memdep_insert++;
254#endif
255
256    // Add the instruction to the list.
257    instList[tid].push_back(inst);
258
259    inst_entry->listIt = --(instList[tid].end());
260
261    // Might want to turn this part into an inline function or something.
262    // It's shared between both insert functions.
263    if (inst->isStore()) {
264        DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
265                inst->pcState(), inst->seqNum);
266
267        depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
268
269        ++insertedStores;
270    } else if (inst->isLoad()) {
271        ++insertedLoads;
272    } else {
273        panic("Unknown type! (most likely a barrier).");
274    }
275}
276
277template <class MemDepPred, class Impl>
278void
279MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
280{
281    InstSeqNum barr_sn = barr_inst->seqNum;
282    // Memory barriers block loads and stores, write barriers only stores.
283    if (barr_inst->isMemBarrier()) {
284        loadBarrier = true;
285        loadBarrierSN = barr_sn;
286        storeBarrier = true;
287        storeBarrierSN = barr_sn;
288        DPRINTF(MemDepUnit, "Inserted a memory barrier %s SN:%lli\n",
289                barr_inst->pcState(),barr_sn);
290    } else if (barr_inst->isWriteBarrier()) {
291        storeBarrier = true;
292        storeBarrierSN = barr_sn;
293        DPRINTF(MemDepUnit, "Inserted a write barrier\n");
294    }
295
296    ThreadID tid = barr_inst->threadNumber;
297
298    MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
299
300    // Add the MemDepEntry to the hash.
301    memDepHash.insert(
302        std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
303#ifdef DEBUG
304    MemDepEntry::memdep_insert++;
305#endif
306
307    // Add the instruction to the instruction list.
308    instList[tid].push_back(barr_inst);
309
310    inst_entry->listIt = --(instList[tid].end());
311}
312
313template <class MemDepPred, class Impl>
314void
315MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
316{
317    DPRINTF(MemDepUnit, "Marking registers as ready for "
318            "instruction PC %s [sn:%lli].\n",
319            inst->pcState(), inst->seqNum);
320
321    MemDepEntryPtr inst_entry = findInHash(inst);
322
323    inst_entry->regsReady = true;
324
325    if (inst_entry->memDepReady) {
326        DPRINTF(MemDepUnit, "Instruction has its memory "
327                "dependencies resolved, adding it to the ready list.\n");
328
329        moveToReady(inst_entry);
330    } else {
331        DPRINTF(MemDepUnit, "Instruction still waiting on "
332                "memory dependency.\n");
333    }
334}
335
336template <class MemDepPred, class Impl>
337void
338MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
339{
340    DPRINTF(MemDepUnit, "Marking non speculative "
341            "instruction PC %s as ready [sn:%lli].\n",
342            inst->pcState(), inst->seqNum);
343
344    MemDepEntryPtr inst_entry = findInHash(inst);
345
346    moveToReady(inst_entry);
347}
348
349template <class MemDepPred, class Impl>
350void
351MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
352{
353    instsToReplay.push_back(inst);
354}
355
356template <class MemDepPred, class Impl>
357void
358MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
359{
360    DynInstPtr temp_inst;
361
362    // For now this replay function replays all waiting memory ops.
363    while (!instsToReplay.empty()) {
364        temp_inst = instsToReplay.front();
365
366        MemDepEntryPtr inst_entry = findInHash(temp_inst);
367
368        DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n",
369                temp_inst->pcState(), temp_inst->seqNum);
370
371        moveToReady(inst_entry);
372
373        instsToReplay.pop_front();
374    }
375}
376
377template <class MemDepPred, class Impl>
378void
379MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
380{
381    DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
382            inst->pcState(), inst->seqNum);
383
384    ThreadID tid = inst->threadNumber;
385
386    // Remove the instruction from the hash and the list.
387    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
388
389    assert(hash_it != memDepHash.end());
390
391    instList[tid].erase((*hash_it).second->listIt);
392
393    (*hash_it).second = NULL;
394
395    memDepHash.erase(hash_it);
396#ifdef DEBUG
397    MemDepEntry::memdep_erase++;
398#endif
399}
400
401template <class MemDepPred, class Impl>
402void
403MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
404{
405    wakeDependents(inst);
406    completed(inst);
407
408    InstSeqNum barr_sn = inst->seqNum;
409    DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
410            inst->seqNum);
411    if (inst->isMemBarrier()) {
412        if (loadBarrierSN == barr_sn)
413            loadBarrier = false;
414        if (storeBarrierSN == barr_sn)
415            storeBarrier = false;
416    } else if (inst->isWriteBarrier()) {
417        if (storeBarrierSN == barr_sn)
418            storeBarrier = false;
419    }
420}
421
422template <class MemDepPred, class Impl>
423void
424MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
425{
426    // Only stores and barriers have dependents.
427    if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
428        return;
429    }
430
431    MemDepEntryPtr inst_entry = findInHash(inst);
432
433    for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
434        MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
435
436        if (!woken_inst->inst) {
437            // Potentially removed mem dep entries could be on this list
438            continue;
439        }
440
441        DPRINTF(MemDepUnit, "Waking up a dependent inst, "
442                "[sn:%lli].\n",
443                woken_inst->inst->seqNum);
444
445        if (woken_inst->regsReady && !woken_inst->squashed) {
446            moveToReady(woken_inst);
447        } else {
448            woken_inst->memDepReady = true;
449        }
450    }
451
452    inst_entry->dependInsts.clear();
453}
454
455template <class MemDepPred, class Impl>
456void
457MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
458                                     ThreadID tid)
459{
460    if (!instsToReplay.empty()) {
461        ListIt replay_it = instsToReplay.begin();
462        while (replay_it != instsToReplay.end()) {
463            if ((*replay_it)->threadNumber == tid &&
464                (*replay_it)->seqNum > squashed_num) {
465                instsToReplay.erase(replay_it++);
466            } else {
467                ++replay_it;
468            }
469        }
470    }
471
472    ListIt squash_it = instList[tid].end();
473    --squash_it;
474
475    MemDepHashIt hash_it;
476
477    while (!instList[tid].empty() &&
478           (*squash_it)->seqNum > squashed_num) {
479
480        DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
481                (*squash_it)->seqNum);
482
483        if ((*squash_it)->seqNum == loadBarrierSN)
484              loadBarrier = false;
485
486        if ((*squash_it)->seqNum == storeBarrierSN)
487              storeBarrier = false;
488
489        hash_it = memDepHash.find((*squash_it)->seqNum);
490
491        assert(hash_it != memDepHash.end());
492
493        (*hash_it).second->squashed = true;
494
495        (*hash_it).second = NULL;
496
497        memDepHash.erase(hash_it);
498#ifdef DEBUG
499        MemDepEntry::memdep_erase++;
500#endif
501
502        instList[tid].erase(squash_it--);
503    }
504
505    // Tell the dependency predictor to squash as well.
506    depPred.squash(squashed_num, tid);
507}
508
509template <class MemDepPred, class Impl>
510void
511MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
512                                        DynInstPtr &violating_load)
513{
514    DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
515            " load: %#x, store: %#x\n", violating_load->instAddr(),
516            store_inst->instAddr());
517    // Tell the memory dependence unit of the violation.
518    depPred.violation(store_inst->instAddr(), violating_load->instAddr());
519}
520
521template <class MemDepPred, class Impl>
522void
523MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
524{
525    DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
526            inst->instAddr(), inst->seqNum);
527
528    depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
529}
530
531template <class MemDepPred, class Impl>
532inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
533MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
534{
535    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
536
537    assert(hash_it != memDepHash.end());
538
539    return (*hash_it).second;
540}
541
542template <class MemDepPred, class Impl>
543inline void
544MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
545{
546    DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
547            "to the ready list.\n", woken_inst_entry->inst->seqNum);
548
549    assert(!woken_inst_entry->squashed);
550
551    iqPtr->addReadyMemInst(woken_inst_entry->inst);
552}
553
554
555template <class MemDepPred, class Impl>
556void
557MemDepUnit<MemDepPred, Impl>::dumpLists()
558{
559    for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
560        cprintf("Instruction list %i size: %i\n",
561                tid, instList[tid].size());
562
563        ListIt inst_list_it = instList[tid].begin();
564        int num = 0;
565
566        while (inst_list_it != instList[tid].end()) {
567            cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
568                    "Squashed:%i\n\n",
569                    num, (*inst_list_it)->pcState(),
570                    (*inst_list_it)->seqNum,
571                    (*inst_list_it)->threadNumber,
572                    (*inst_list_it)->isIssued(),
573                    (*inst_list_it)->isSquashed());
574            inst_list_it++;
575            ++num;
576        }
577    }
578
579    cprintf("Memory dependence hash size: %i\n", memDepHash.size());
580
581#ifdef DEBUG
582    cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
583#endif
584}
585