mem_dep_unit_impl.hh revision 5529:9ae69b9cd7fd 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <map>
32
33#include "cpu/o3/inst_queue.hh"
34#include "cpu/o3/mem_dep_unit.hh"
35
36#include "params/DerivO3CPU.hh"
37
38template <class MemDepPred, class Impl>
39MemDepUnit<MemDepPred, Impl>::MemDepUnit()
40    : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
41      storeBarrierSN(0), iqPtr(NULL)
42{
43}
44
45template <class MemDepPred, class Impl>
46MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
47    : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
48      loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
49{
50    DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
51}
52
53template <class MemDepPred, class Impl>
54MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
55{
56    for (int tid=0; tid < Impl::MaxThreads; tid++) {
57
58        ListIt inst_list_it = instList[tid].begin();
59
60        MemDepHashIt hash_it;
61
62        while (!instList[tid].empty()) {
63            hash_it = memDepHash.find((*inst_list_it)->seqNum);
64
65            assert(hash_it != memDepHash.end());
66
67            memDepHash.erase(hash_it);
68
69            instList[tid].erase(inst_list_it++);
70        }
71    }
72
73#ifdef DEBUG
74    assert(MemDepEntry::memdep_count == 0);
75#endif
76}
77
78template <class MemDepPred, class Impl>
79std::string
80MemDepUnit<MemDepPred, Impl>::name() const
81{
82    return "memdepunit";
83}
84
85template <class MemDepPred, class Impl>
86void
87MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, int tid)
88{
89    DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
90
91    id = tid;
92
93    depPred.init(params->SSITSize, params->LFSTSize);
94}
95
96template <class MemDepPred, class Impl>
97void
98MemDepUnit<MemDepPred, Impl>::regStats()
99{
100    insertedLoads
101        .name(name() + ".memDep.insertedLoads")
102        .desc("Number of loads inserted to the mem dependence unit.");
103
104    insertedStores
105        .name(name() + ".memDep.insertedStores")
106        .desc("Number of stores inserted to the mem dependence unit.");
107
108    conflictingLoads
109        .name(name() + ".memDep.conflictingLoads")
110        .desc("Number of conflicting loads.");
111
112    conflictingStores
113        .name(name() + ".memDep.conflictingStores")
114        .desc("Number of conflicting stores.");
115}
116
117template <class MemDepPred, class Impl>
118void
119MemDepUnit<MemDepPred, Impl>::switchOut()
120{
121    assert(instList[0].empty());
122    assert(instsToReplay.empty());
123    assert(memDepHash.empty());
124    // Clear any state.
125    for (int i = 0; i < Impl::MaxThreads; ++i) {
126        instList[i].clear();
127    }
128    instsToReplay.clear();
129    memDepHash.clear();
130}
131
132template <class MemDepPred, class Impl>
133void
134MemDepUnit<MemDepPred, Impl>::takeOverFrom()
135{
136    // Be sure to reset all state.
137    loadBarrier = storeBarrier = false;
138    loadBarrierSN = storeBarrierSN = 0;
139    depPred.clear();
140}
141
142template <class MemDepPred, class Impl>
143void
144MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
145{
146    iqPtr = iq_ptr;
147}
148
149template <class MemDepPred, class Impl>
150void
151MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
152{
153    unsigned tid = inst->threadNumber;
154
155    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
156
157    // Add the MemDepEntry to the hash.
158    memDepHash.insert(
159        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
160#ifdef DEBUG
161    MemDepEntry::memdep_insert++;
162#endif
163
164    instList[tid].push_back(inst);
165
166    inst_entry->listIt = --(instList[tid].end());
167
168    // Check any barriers and the dependence predictor for any
169    // producing memrefs/stores.
170    InstSeqNum producing_store;
171    if (inst->isLoad() && loadBarrier) {
172        DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
173                loadBarrierSN);
174        producing_store = loadBarrierSN;
175    } else if (inst->isStore() && storeBarrier) {
176        DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
177                storeBarrierSN);
178        producing_store = storeBarrierSN;
179    } else {
180        producing_store = depPred.checkInst(inst->readPC());
181    }
182
183    MemDepEntryPtr store_entry = NULL;
184
185    // If there is a producing store, try to find the entry.
186    if (producing_store != 0) {
187        DPRINTF(MemDepUnit, "Searching for producer\n");
188        MemDepHashIt hash_it = memDepHash.find(producing_store);
189
190        if (hash_it != memDepHash.end()) {
191            store_entry = (*hash_it).second;
192            DPRINTF(MemDepUnit, "Proucer found\n");
193        }
194    }
195
196    // If no store entry, then instruction can issue as soon as the registers
197    // are ready.
198    if (!store_entry) {
199        DPRINTF(MemDepUnit, "No dependency for inst PC "
200                "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
201
202        inst_entry->memDepReady = true;
203
204        if (inst->readyToIssue()) {
205            inst_entry->regsReady = true;
206
207            moveToReady(inst_entry);
208        }
209    } else {
210        // Otherwise make the instruction dependent on the store/barrier.
211        DPRINTF(MemDepUnit, "Adding to dependency list; "
212                "inst PC %#x is dependent on [sn:%lli].\n",
213                inst->readPC(), producing_store);
214
215        if (inst->readyToIssue()) {
216            inst_entry->regsReady = true;
217        }
218
219        // Clear the bit saying this instruction can issue.
220        inst->clearCanIssue();
221
222        // Add this instruction to the list of dependents.
223        store_entry->dependInsts.push_back(inst_entry);
224
225        if (inst->isLoad()) {
226            ++conflictingLoads;
227        } else {
228            ++conflictingStores;
229        }
230    }
231
232    if (inst->isStore()) {
233        DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
234                inst->readPC(), inst->seqNum);
235
236        depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
237
238        ++insertedStores;
239    } else if (inst->isLoad()) {
240        ++insertedLoads;
241    } else {
242        panic("Unknown type! (most likely a barrier).");
243    }
244}
245
246template <class MemDepPred, class Impl>
247void
248MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
249{
250    unsigned tid = inst->threadNumber;
251
252    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
253
254    // Insert the MemDepEntry into the hash.
255    memDepHash.insert(
256        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
257#ifdef DEBUG
258    MemDepEntry::memdep_insert++;
259#endif
260
261    // Add the instruction to the list.
262    instList[tid].push_back(inst);
263
264    inst_entry->listIt = --(instList[tid].end());
265
266    // Might want to turn this part into an inline function or something.
267    // It's shared between both insert functions.
268    if (inst->isStore()) {
269        DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
270                inst->readPC(), inst->seqNum);
271
272        depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
273
274        ++insertedStores;
275    } else if (inst->isLoad()) {
276        ++insertedLoads;
277    } else {
278        panic("Unknown type! (most likely a barrier).");
279    }
280}
281
282template <class MemDepPred, class Impl>
283void
284MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
285{
286    InstSeqNum barr_sn = barr_inst->seqNum;
287    // Memory barriers block loads and stores, write barriers only stores.
288    if (barr_inst->isMemBarrier()) {
289        loadBarrier = true;
290        loadBarrierSN = barr_sn;
291        storeBarrier = true;
292        storeBarrierSN = barr_sn;
293        DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
294    } else if (barr_inst->isWriteBarrier()) {
295        storeBarrier = true;
296        storeBarrierSN = barr_sn;
297        DPRINTF(MemDepUnit, "Inserted a write barrier\n");
298    }
299
300    unsigned tid = barr_inst->threadNumber;
301
302    MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
303
304    // Add the MemDepEntry to the hash.
305    memDepHash.insert(
306        std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
307#ifdef DEBUG
308    MemDepEntry::memdep_insert++;
309#endif
310
311    // Add the instruction to the instruction list.
312    instList[tid].push_back(barr_inst);
313
314    inst_entry->listIt = --(instList[tid].end());
315}
316
317template <class MemDepPred, class Impl>
318void
319MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
320{
321    DPRINTF(MemDepUnit, "Marking registers as ready for "
322            "instruction PC %#x [sn:%lli].\n",
323            inst->readPC(), inst->seqNum);
324
325    MemDepEntryPtr inst_entry = findInHash(inst);
326
327    inst_entry->regsReady = true;
328
329    if (inst_entry->memDepReady) {
330        DPRINTF(MemDepUnit, "Instruction has its memory "
331                "dependencies resolved, adding it to the ready list.\n");
332
333        moveToReady(inst_entry);
334    } else {
335        DPRINTF(MemDepUnit, "Instruction still waiting on "
336                "memory dependency.\n");
337    }
338}
339
340template <class MemDepPred, class Impl>
341void
342MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
343{
344    DPRINTF(MemDepUnit, "Marking non speculative "
345            "instruction PC %#x as ready [sn:%lli].\n",
346            inst->readPC(), inst->seqNum);
347
348    MemDepEntryPtr inst_entry = findInHash(inst);
349
350    moveToReady(inst_entry);
351}
352
353template <class MemDepPred, class Impl>
354void
355MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
356{
357    instsToReplay.push_back(inst);
358}
359
360template <class MemDepPred, class Impl>
361void
362MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
363{
364    DynInstPtr temp_inst;
365
366    // For now this replay function replays all waiting memory ops.
367    while (!instsToReplay.empty()) {
368        temp_inst = instsToReplay.front();
369
370        MemDepEntryPtr inst_entry = findInHash(temp_inst);
371
372        DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
373                "[sn:%lli].\n",
374                temp_inst->readPC(), temp_inst->seqNum);
375
376        moveToReady(inst_entry);
377
378        instsToReplay.pop_front();
379    }
380}
381
382template <class MemDepPred, class Impl>
383void
384MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
385{
386    DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
387            "[sn:%lli].\n",
388            inst->readPC(), inst->seqNum);
389
390    unsigned tid = inst->threadNumber;
391
392    // Remove the instruction from the hash and the list.
393    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
394
395    assert(hash_it != memDepHash.end());
396
397    instList[tid].erase((*hash_it).second->listIt);
398
399    (*hash_it).second = NULL;
400
401    memDepHash.erase(hash_it);
402#ifdef DEBUG
403    MemDepEntry::memdep_erase++;
404#endif
405}
406
407template <class MemDepPred, class Impl>
408void
409MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
410{
411    wakeDependents(inst);
412    completed(inst);
413
414    InstSeqNum barr_sn = inst->seqNum;
415
416    if (inst->isMemBarrier()) {
417        assert(loadBarrier && storeBarrier);
418        if (loadBarrierSN == barr_sn)
419            loadBarrier = false;
420        if (storeBarrierSN == barr_sn)
421            storeBarrier = false;
422    } else if (inst->isWriteBarrier()) {
423        assert(storeBarrier);
424        if (storeBarrierSN == barr_sn)
425            storeBarrier = false;
426    }
427}
428
429template <class MemDepPred, class Impl>
430void
431MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
432{
433    // Only stores and barriers have dependents.
434    if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
435        return;
436    }
437
438    MemDepEntryPtr inst_entry = findInHash(inst);
439
440    for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
441        MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
442
443        if (!woken_inst->inst) {
444            // Potentially removed mem dep entries could be on this list
445            continue;
446        }
447
448        DPRINTF(MemDepUnit, "Waking up a dependent inst, "
449                "[sn:%lli].\n",
450                woken_inst->inst->seqNum);
451
452        if (woken_inst->regsReady && !woken_inst->squashed) {
453            moveToReady(woken_inst);
454        } else {
455            woken_inst->memDepReady = true;
456        }
457    }
458
459    inst_entry->dependInsts.clear();
460}
461
462template <class MemDepPred, class Impl>
463void
464MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
465                                     unsigned tid)
466{
467    if (!instsToReplay.empty()) {
468        ListIt replay_it = instsToReplay.begin();
469        while (replay_it != instsToReplay.end()) {
470            if ((*replay_it)->threadNumber == tid &&
471                (*replay_it)->seqNum > squashed_num) {
472                instsToReplay.erase(replay_it++);
473            } else {
474                ++replay_it;
475            }
476        }
477    }
478
479    ListIt squash_it = instList[tid].end();
480    --squash_it;
481
482    MemDepHashIt hash_it;
483
484    while (!instList[tid].empty() &&
485           (*squash_it)->seqNum > squashed_num) {
486
487        DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
488                (*squash_it)->seqNum);
489
490        hash_it = memDepHash.find((*squash_it)->seqNum);
491
492        assert(hash_it != memDepHash.end());
493
494        (*hash_it).second->squashed = true;
495
496        (*hash_it).second = NULL;
497
498        memDepHash.erase(hash_it);
499#ifdef DEBUG
500        MemDepEntry::memdep_erase++;
501#endif
502
503        instList[tid].erase(squash_it--);
504    }
505
506    // Tell the dependency predictor to squash as well.
507    depPred.squash(squashed_num, tid);
508}
509
510template <class MemDepPred, class Impl>
511void
512MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
513                                        DynInstPtr &violating_load)
514{
515    DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
516            " load: %#x, store: %#x\n", violating_load->readPC(),
517            store_inst->readPC());
518    // Tell the memory dependence unit of the violation.
519    depPred.violation(violating_load->readPC(), store_inst->readPC());
520}
521
522template <class MemDepPred, class Impl>
523void
524MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
525{
526    DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
527            inst->readPC(), inst->seqNum);
528
529    depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
530}
531
532template <class MemDepPred, class Impl>
533inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
534MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
535{
536    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
537
538    assert(hash_it != memDepHash.end());
539
540    return (*hash_it).second;
541}
542
543template <class MemDepPred, class Impl>
544inline void
545MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
546{
547    DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
548            "to the ready list.\n", woken_inst_entry->inst->seqNum);
549
550    assert(!woken_inst_entry->squashed);
551
552    iqPtr->addReadyMemInst(woken_inst_entry->inst);
553}
554
555
556template <class MemDepPred, class Impl>
557void
558MemDepUnit<MemDepPred, Impl>::dumpLists()
559{
560    for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
561        cprintf("Instruction list %i size: %i\n",
562                tid, instList[tid].size());
563
564        ListIt inst_list_it = instList[tid].begin();
565        int num = 0;
566
567        while (inst_list_it != instList[tid].end()) {
568            cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
569                    "Squashed:%i\n\n",
570                    num, (*inst_list_it)->readPC(),
571                    (*inst_list_it)->seqNum,
572                    (*inst_list_it)->threadNumber,
573                    (*inst_list_it)->isIssued(),
574                    (*inst_list_it)->isSquashed());
575            inst_list_it++;
576            ++num;
577        }
578    }
579
580    cprintf("Memory dependence hash size: %i\n", memDepHash.size());
581
582#ifdef DEBUG
583    cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
584#endif
585}
586