mem_dep_unit_impl.hh revision 2674:6d4afef73a20 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <map>
32
33#include "cpu/o3/inst_queue.hh"
34#include "cpu/o3/mem_dep_unit.hh"
35
36template <class MemDepPred, class Impl>
37MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
38    : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
39      loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
40{
41    DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
42}
43
44template <class MemDepPred, class Impl>
45MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
46{
47    for (int tid=0; tid < Impl::MaxThreads; tid++) {
48
49        ListIt inst_list_it = instList[tid].begin();
50
51        MemDepHashIt hash_it;
52
53        while (!instList[tid].empty()) {
54            hash_it = memDepHash.find((*inst_list_it)->seqNum);
55
56            assert(hash_it != memDepHash.end());
57
58            memDepHash.erase(hash_it);
59
60            instList[tid].erase(inst_list_it++);
61        }
62    }
63
64    assert(MemDepEntry::memdep_count == 0);
65}
66
67template <class MemDepPred, class Impl>
68std::string
69MemDepUnit<MemDepPred, Impl>::name() const
70{
71    return "memdepunit";
72}
73
74template <class MemDepPred, class Impl>
75void
76MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
77{
78    DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
79
80    id = tid;
81
82    depPred.init(params->SSITSize, params->LFSTSize);
83}
84
85template <class MemDepPred, class Impl>
86void
87MemDepUnit<MemDepPred, Impl>::regStats()
88{
89    insertedLoads
90        .name(name() + ".memDep.insertedLoads")
91        .desc("Number of loads inserted to the mem dependence unit.");
92
93    insertedStores
94        .name(name() + ".memDep.insertedStores")
95        .desc("Number of stores inserted to the mem dependence unit.");
96
97    conflictingLoads
98        .name(name() + ".memDep.conflictingLoads")
99        .desc("Number of conflicting loads.");
100
101    conflictingStores
102        .name(name() + ".memDep.conflictingStores")
103        .desc("Number of conflicting stores.");
104}
105
106template <class MemDepPred, class Impl>
107void
108MemDepUnit<MemDepPred, Impl>::switchOut()
109{
110    // Clear any state.
111    for (int i = 0; i < Impl::MaxThreads; ++i) {
112        instList[i].clear();
113    }
114    instsToReplay.clear();
115    memDepHash.clear();
116}
117
118template <class MemDepPred, class Impl>
119void
120MemDepUnit<MemDepPred, Impl>::takeOverFrom()
121{
122    // Be sure to reset all state.
123    loadBarrier = storeBarrier = false;
124    loadBarrierSN = storeBarrierSN = 0;
125    depPred.clear();
126}
127
128template <class MemDepPred, class Impl>
129void
130MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
131{
132    iqPtr = iq_ptr;
133}
134
135template <class MemDepPred, class Impl>
136void
137MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
138{
139    unsigned tid = inst->threadNumber;
140
141    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
142
143    // Add the MemDepEntry to the hash.
144    memDepHash.insert(
145        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
146    MemDepEntry::memdep_insert++;
147
148    instList[tid].push_back(inst);
149
150    inst_entry->listIt = --(instList[tid].end());
151
152    // Check any barriers and the dependence predictor for any
153    // producing memrefs/stores.
154    InstSeqNum producing_store;
155    if (inst->isLoad() && loadBarrier) {
156        producing_store = loadBarrierSN;
157    } else if (inst->isStore() && storeBarrier) {
158        producing_store = storeBarrierSN;
159    } else {
160        producing_store = depPred.checkInst(inst->readPC());
161    }
162
163    MemDepEntryPtr store_entry = NULL;
164
165    // If there is a producing store, try to find the entry.
166    if (producing_store != 0) {
167        MemDepHashIt hash_it = memDepHash.find(producing_store);
168
169        if (hash_it != memDepHash.end()) {
170            store_entry = (*hash_it).second;
171        }
172    }
173
174    // If no store entry, then instruction can issue as soon as the registers
175    // are ready.
176    if (!store_entry) {
177        DPRINTF(MemDepUnit, "No dependency for inst PC "
178                "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
179
180        inst_entry->memDepReady = true;
181
182        if (inst->readyToIssue()) {
183            inst_entry->regsReady = true;
184
185            moveToReady(inst_entry);
186        }
187    } else {
188        // Otherwise make the instruction dependent on the store/barrier.
189        DPRINTF(MemDepUnit, "Adding to dependency list; "
190                "inst PC %#x is dependent on [sn:%lli].\n",
191                inst->readPC(), producing_store);
192
193        if (inst->readyToIssue()) {
194            inst_entry->regsReady = true;
195        }
196
197        // Add this instruction to the list of dependents.
198        store_entry->dependInsts.push_back(inst_entry);
199
200        if (inst->isLoad()) {
201            ++conflictingLoads;
202        } else {
203            ++conflictingStores;
204        }
205    }
206
207    if (inst->isStore()) {
208        DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
209                inst->readPC(), inst->seqNum);
210
211        depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
212
213        ++insertedStores;
214    } else if (inst->isLoad()) {
215        ++insertedLoads;
216    } else {
217        panic("Unknown type! (most likely a barrier).");
218    }
219}
220
221template <class MemDepPred, class Impl>
222void
223MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
224{
225    unsigned tid = inst->threadNumber;
226
227    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
228
229    // Insert the MemDepEntry into the hash.
230    memDepHash.insert(
231        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
232    MemDepEntry::memdep_insert++;
233
234    // Add the instruction to the list.
235    instList[tid].push_back(inst);
236
237    inst_entry->listIt = --(instList[tid].end());
238
239    // Might want to turn this part into an inline function or something.
240    // It's shared between both insert functions.
241    if (inst->isStore()) {
242        DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
243                inst->readPC(), inst->seqNum);
244
245        depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
246
247        ++insertedStores;
248    } else if (inst->isLoad()) {
249        ++insertedLoads;
250    } else {
251        panic("Unknown type! (most likely a barrier).");
252    }
253}
254
255template <class MemDepPred, class Impl>
256void
257MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
258{
259    InstSeqNum barr_sn = barr_inst->seqNum;
260    // Memory barriers block loads and stores, write barriers only stores.
261    if (barr_inst->isMemBarrier()) {
262        loadBarrier = true;
263        loadBarrierSN = barr_sn;
264        storeBarrier = true;
265        storeBarrierSN = barr_sn;
266        DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
267    } else if (barr_inst->isWriteBarrier()) {
268        storeBarrier = true;
269        storeBarrierSN = barr_sn;
270        DPRINTF(MemDepUnit, "Inserted a write barrier\n");
271    }
272
273    unsigned tid = barr_inst->threadNumber;
274
275    MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
276
277    // Add the MemDepEntry to the hash.
278    memDepHash.insert(
279        std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
280    MemDepEntry::memdep_insert++;
281
282    // Add the instruction to the instruction list.
283    instList[tid].push_back(barr_inst);
284
285    inst_entry->listIt = --(instList[tid].end());
286}
287
288template <class MemDepPred, class Impl>
289void
290MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
291{
292    DPRINTF(MemDepUnit, "Marking registers as ready for "
293            "instruction PC %#x [sn:%lli].\n",
294            inst->readPC(), inst->seqNum);
295
296    MemDepEntryPtr inst_entry = findInHash(inst);
297
298    inst_entry->regsReady = true;
299
300    if (inst_entry->memDepReady) {
301        DPRINTF(MemDepUnit, "Instruction has its memory "
302                "dependencies resolved, adding it to the ready list.\n");
303
304        moveToReady(inst_entry);
305    } else {
306        DPRINTF(MemDepUnit, "Instruction still waiting on "
307                "memory dependency.\n");
308    }
309}
310
311template <class MemDepPred, class Impl>
312void
313MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
314{
315    DPRINTF(MemDepUnit, "Marking non speculative "
316            "instruction PC %#x as ready [sn:%lli].\n",
317            inst->readPC(), inst->seqNum);
318
319    MemDepEntryPtr inst_entry = findInHash(inst);
320
321    moveToReady(inst_entry);
322}
323
324template <class MemDepPred, class Impl>
325void
326MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
327{
328    instsToReplay.push_back(inst);
329}
330
331template <class MemDepPred, class Impl>
332void
333MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
334{
335    DynInstPtr temp_inst;
336    bool found_inst = false;
337
338    // For now this replay function replays all waiting memory ops.
339    while (!instsToReplay.empty()) {
340        temp_inst = instsToReplay.front();
341
342        MemDepEntryPtr inst_entry = findInHash(temp_inst);
343
344        DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
345                "[sn:%lli].\n",
346                temp_inst->readPC(), temp_inst->seqNum);
347
348        moveToReady(inst_entry);
349
350        if (temp_inst == inst) {
351            found_inst = true;
352        }
353
354        instsToReplay.pop_front();
355    }
356
357    assert(found_inst);
358}
359
360template <class MemDepPred, class Impl>
361void
362MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
363{
364    DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
365            "[sn:%lli].\n",
366            inst->readPC(), inst->seqNum);
367
368    unsigned tid = inst->threadNumber;
369
370    // Remove the instruction from the hash and the list.
371    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
372
373    assert(hash_it != memDepHash.end());
374
375    instList[tid].erase((*hash_it).second->listIt);
376
377    (*hash_it).second = NULL;
378
379    memDepHash.erase(hash_it);
380    MemDepEntry::memdep_erase++;
381}
382
383template <class MemDepPred, class Impl>
384void
385MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
386{
387    wakeDependents(inst);
388    completed(inst);
389
390    InstSeqNum barr_sn = inst->seqNum;
391
392    if (inst->isMemBarrier()) {
393        assert(loadBarrier && storeBarrier);
394        if (loadBarrierSN == barr_sn)
395            loadBarrier = false;
396        if (storeBarrierSN == barr_sn)
397            storeBarrier = false;
398    } else if (inst->isWriteBarrier()) {
399        assert(storeBarrier);
400        if (storeBarrierSN == barr_sn)
401            storeBarrier = false;
402    }
403}
404
405template <class MemDepPred, class Impl>
406void
407MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
408{
409    // Only stores and barriers have dependents.
410    if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
411        return;
412    }
413
414    MemDepEntryPtr inst_entry = findInHash(inst);
415
416    for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
417        MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
418
419        if (!woken_inst->inst) {
420            // Potentially removed mem dep entries could be on this list
421            continue;
422        }
423
424        DPRINTF(MemDepUnit, "Waking up a dependent inst, "
425                "[sn:%lli].\n",
426                woken_inst->inst->seqNum);
427
428        if (woken_inst->regsReady && !woken_inst->squashed) {
429            moveToReady(woken_inst);
430        } else {
431            woken_inst->memDepReady = true;
432        }
433    }
434
435    inst_entry->dependInsts.clear();
436}
437
438template <class MemDepPred, class Impl>
439void
440MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
441                                     unsigned tid)
442{
443    if (!instsToReplay.empty()) {
444        ListIt replay_it = instsToReplay.begin();
445        while (replay_it != instsToReplay.end()) {
446            if ((*replay_it)->threadNumber == tid &&
447                (*replay_it)->seqNum > squashed_num) {
448                instsToReplay.erase(replay_it++);
449            } else {
450                ++replay_it;
451            }
452        }
453    }
454
455    ListIt squash_it = instList[tid].end();
456    --squash_it;
457
458    MemDepHashIt hash_it;
459
460    while (!instList[tid].empty() &&
461           (*squash_it)->seqNum > squashed_num) {
462
463        DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
464                (*squash_it)->seqNum);
465
466        hash_it = memDepHash.find((*squash_it)->seqNum);
467
468        assert(hash_it != memDepHash.end());
469
470        (*hash_it).second->squashed = true;
471
472        (*hash_it).second = NULL;
473
474        memDepHash.erase(hash_it);
475        MemDepEntry::memdep_erase++;
476
477        instList[tid].erase(squash_it--);
478    }
479
480    // Tell the dependency predictor to squash as well.
481    depPred.squash(squashed_num, tid);
482}
483
484template <class MemDepPred, class Impl>
485void
486MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
487                                        DynInstPtr &violating_load)
488{
489    DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
490            " load: %#x, store: %#x\n", violating_load->readPC(),
491            store_inst->readPC());
492    // Tell the memory dependence unit of the violation.
493    depPred.violation(violating_load->readPC(), store_inst->readPC());
494}
495
496template <class MemDepPred, class Impl>
497void
498MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
499{
500    DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
501            inst->readPC(), inst->seqNum);
502
503    depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
504}
505
506template <class MemDepPred, class Impl>
507inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
508MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
509{
510    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
511
512    assert(hash_it != memDepHash.end());
513
514    return (*hash_it).second;
515}
516
517template <class MemDepPred, class Impl>
518inline void
519MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
520{
521    DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
522            "to the ready list.\n", woken_inst_entry->inst->seqNum);
523
524    assert(!woken_inst_entry->squashed);
525
526    iqPtr->addReadyMemInst(woken_inst_entry->inst);
527}
528
529
530template <class MemDepPred, class Impl>
531void
532MemDepUnit<MemDepPred, Impl>::dumpLists()
533{
534    for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
535        cprintf("Instruction list %i size: %i\n",
536                tid, instList[tid].size());
537
538        ListIt inst_list_it = instList[tid].begin();
539        int num = 0;
540
541        while (inst_list_it != instList[tid].end()) {
542            cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
543                    "Squashed:%i\n\n",
544                    num, (*inst_list_it)->readPC(),
545                    (*inst_list_it)->seqNum,
546                    (*inst_list_it)->threadNumber,
547                    (*inst_list_it)->isIssued(),
548                    (*inst_list_it)->isSquashed());
549            inst_list_it++;
550            ++num;
551        }
552    }
553
554    cprintf("Memory dependence hash size: %i\n", memDepHash.size());
555
556    cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
557}
558