mem_dep_unit_impl.hh revision 5529
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301061SN/A 311061SN/A#include <map> 321061SN/A 332292SN/A#include "cpu/o3/inst_queue.hh" 341717SN/A#include "cpu/o3/mem_dep_unit.hh" 351061SN/A 365529Snate@binkert.org#include "params/DerivO3CPU.hh" 375529Snate@binkert.org 381061SN/Atemplate <class MemDepPred, class Impl> 393500Sktlim@umich.eduMemDepUnit<MemDepPred, Impl>::MemDepUnit() 403500Sktlim@umich.edu : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 413500Sktlim@umich.edu storeBarrierSN(0), iqPtr(NULL) 423500Sktlim@umich.edu{ 433500Sktlim@umich.edu} 443500Sktlim@umich.edu 453500Sktlim@umich.edutemplate <class MemDepPred, class Impl> 465529Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params) 472292SN/A : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), 482292SN/A loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL) 491061SN/A{ 502292SN/A DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); 512292SN/A} 522292SN/A 532292SN/Atemplate <class MemDepPred, class Impl> 542292SN/AMemDepUnit<MemDepPred, Impl>::~MemDepUnit() 552292SN/A{ 562292SN/A for (int tid=0; tid < Impl::MaxThreads; tid++) { 572292SN/A 582292SN/A ListIt inst_list_it = instList[tid].begin(); 592292SN/A 602292SN/A MemDepHashIt hash_it; 612292SN/A 622292SN/A while (!instList[tid].empty()) { 632292SN/A hash_it = memDepHash.find((*inst_list_it)->seqNum); 642292SN/A 652292SN/A assert(hash_it != memDepHash.end()); 662292SN/A 672292SN/A memDepHash.erase(hash_it); 682292SN/A 692292SN/A instList[tid].erase(inst_list_it++); 702292SN/A } 712292SN/A } 722292SN/A 732678Sktlim@umich.edu#ifdef DEBUG 742292SN/A assert(MemDepEntry::memdep_count == 0); 752678Sktlim@umich.edu#endif 762292SN/A} 772292SN/A 782292SN/Atemplate <class MemDepPred, class Impl> 792292SN/Astd::string 802292SN/AMemDepUnit<MemDepPred, Impl>::name() const 812292SN/A{ 822292SN/A return "memdepunit"; 832292SN/A} 842292SN/A 852292SN/Atemplate <class MemDepPred, class Impl> 862292SN/Avoid 875529Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, int tid) 882292SN/A{ 892292SN/A DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid); 902292SN/A 912292SN/A id = tid; 922292SN/A 932292SN/A depPred.init(params->SSITSize, params->LFSTSize); 941061SN/A} 951061SN/A 961061SN/Atemplate <class MemDepPred, class Impl> 971061SN/Avoid 981062SN/AMemDepUnit<MemDepPred, Impl>::regStats() 991062SN/A{ 1001062SN/A insertedLoads 1011062SN/A .name(name() + ".memDep.insertedLoads") 1021062SN/A .desc("Number of loads inserted to the mem dependence unit."); 1031062SN/A 1041062SN/A insertedStores 1051062SN/A .name(name() + ".memDep.insertedStores") 1061062SN/A .desc("Number of stores inserted to the mem dependence unit."); 1071062SN/A 1081062SN/A conflictingLoads 1091062SN/A .name(name() + ".memDep.conflictingLoads") 1101062SN/A .desc("Number of conflicting loads."); 1111062SN/A 1121062SN/A conflictingStores 1131062SN/A .name(name() + ".memDep.conflictingStores") 1141062SN/A .desc("Number of conflicting stores."); 1151062SN/A} 1161062SN/A 1171062SN/Atemplate <class MemDepPred, class Impl> 1181062SN/Avoid 1192307SN/AMemDepUnit<MemDepPred, Impl>::switchOut() 1202307SN/A{ 1212367SN/A assert(instList[0].empty()); 1222367SN/A assert(instsToReplay.empty()); 1232367SN/A assert(memDepHash.empty()); 1242348SN/A // Clear any state. 1252307SN/A for (int i = 0; i < Impl::MaxThreads; ++i) { 1262307SN/A instList[i].clear(); 1272307SN/A } 1282307SN/A instsToReplay.clear(); 1292307SN/A memDepHash.clear(); 1302307SN/A} 1312307SN/A 1322307SN/Atemplate <class MemDepPred, class Impl> 1332307SN/Avoid 1342307SN/AMemDepUnit<MemDepPred, Impl>::takeOverFrom() 1352307SN/A{ 1362348SN/A // Be sure to reset all state. 1372307SN/A loadBarrier = storeBarrier = false; 1382307SN/A loadBarrierSN = storeBarrierSN = 0; 1392307SN/A depPred.clear(); 1402307SN/A} 1412307SN/A 1422307SN/Atemplate <class MemDepPred, class Impl> 1432307SN/Avoid 1442292SN/AMemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) 1452292SN/A{ 1462292SN/A iqPtr = iq_ptr; 1472292SN/A} 1482292SN/A 1492292SN/Atemplate <class MemDepPred, class Impl> 1502292SN/Avoid 1511061SN/AMemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 1521061SN/A{ 1532292SN/A unsigned tid = inst->threadNumber; 1541061SN/A 1552292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(inst); 1561061SN/A 1572292SN/A // Add the MemDepEntry to the hash. 1582292SN/A memDepHash.insert( 1592292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 1602678Sktlim@umich.edu#ifdef DEBUG 1612292SN/A MemDepEntry::memdep_insert++; 1622678Sktlim@umich.edu#endif 1631061SN/A 1642292SN/A instList[tid].push_back(inst); 1651062SN/A 1662292SN/A inst_entry->listIt = --(instList[tid].end()); 1671062SN/A 1682329SN/A // Check any barriers and the dependence predictor for any 1692348SN/A // producing memrefs/stores. 1702292SN/A InstSeqNum producing_store; 1712292SN/A if (inst->isLoad() && loadBarrier) { 1723500Sktlim@umich.edu DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n", 1733500Sktlim@umich.edu loadBarrierSN); 1742292SN/A producing_store = loadBarrierSN; 1752292SN/A } else if (inst->isStore() && storeBarrier) { 1763500Sktlim@umich.edu DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n", 1773500Sktlim@umich.edu storeBarrierSN); 1782292SN/A producing_store = storeBarrierSN; 1792292SN/A } else { 1802292SN/A producing_store = depPred.checkInst(inst->readPC()); 1812292SN/A } 1822292SN/A 1832292SN/A MemDepEntryPtr store_entry = NULL; 1842292SN/A 1852292SN/A // If there is a producing store, try to find the entry. 1862292SN/A if (producing_store != 0) { 1873500Sktlim@umich.edu DPRINTF(MemDepUnit, "Searching for producer\n"); 1882292SN/A MemDepHashIt hash_it = memDepHash.find(producing_store); 1892292SN/A 1902292SN/A if (hash_it != memDepHash.end()) { 1912292SN/A store_entry = (*hash_it).second; 1923500Sktlim@umich.edu DPRINTF(MemDepUnit, "Proucer found\n"); 1932292SN/A } 1942292SN/A } 1952292SN/A 1962292SN/A // If no store entry, then instruction can issue as soon as the registers 1972292SN/A // are ready. 1982292SN/A if (!store_entry) { 1992292SN/A DPRINTF(MemDepUnit, "No dependency for inst PC " 2002292SN/A "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum); 2012292SN/A 2022292SN/A inst_entry->memDepReady = true; 2031062SN/A 2041062SN/A if (inst->readyToIssue()) { 2052292SN/A inst_entry->regsReady = true; 2061062SN/A 2072292SN/A moveToReady(inst_entry); 2081062SN/A } 2091061SN/A } else { 2102329SN/A // Otherwise make the instruction dependent on the store/barrier. 2112292SN/A DPRINTF(MemDepUnit, "Adding to dependency list; " 2122292SN/A "inst PC %#x is dependent on [sn:%lli].\n", 2131062SN/A inst->readPC(), producing_store); 2141062SN/A 2151062SN/A if (inst->readyToIssue()) { 2162292SN/A inst_entry->regsReady = true; 2171062SN/A } 2181062SN/A 2194033Sktlim@umich.edu // Clear the bit saying this instruction can issue. 2204033Sktlim@umich.edu inst->clearCanIssue(); 2214033Sktlim@umich.edu 2221062SN/A // Add this instruction to the list of dependents. 2232292SN/A store_entry->dependInsts.push_back(inst_entry); 2241062SN/A 2251062SN/A if (inst->isLoad()) { 2261062SN/A ++conflictingLoads; 2271062SN/A } else { 2281062SN/A ++conflictingStores; 2291062SN/A } 2301061SN/A } 2311061SN/A 2321061SN/A if (inst->isStore()) { 2332292SN/A DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n", 2342292SN/A inst->readPC(), inst->seqNum); 2351062SN/A 2362292SN/A depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber); 2371062SN/A 2381062SN/A ++insertedStores; 2391062SN/A } else if (inst->isLoad()) { 2401062SN/A ++insertedLoads; 2411062SN/A } else { 2422292SN/A panic("Unknown type! (most likely a barrier)."); 2431061SN/A } 2441062SN/A} 2451062SN/A 2461062SN/Atemplate <class MemDepPred, class Impl> 2471062SN/Avoid 2481062SN/AMemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 2491062SN/A{ 2502292SN/A unsigned tid = inst->threadNumber; 2511062SN/A 2522292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(inst); 2531062SN/A 2542292SN/A // Insert the MemDepEntry into the hash. 2552292SN/A memDepHash.insert( 2562292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 2572678Sktlim@umich.edu#ifdef DEBUG 2582292SN/A MemDepEntry::memdep_insert++; 2592678Sktlim@umich.edu#endif 2601062SN/A 2612292SN/A // Add the instruction to the list. 2622292SN/A instList[tid].push_back(inst); 2632292SN/A 2642292SN/A inst_entry->listIt = --(instList[tid].end()); 2651062SN/A 2661062SN/A // Might want to turn this part into an inline function or something. 2671062SN/A // It's shared between both insert functions. 2681062SN/A if (inst->isStore()) { 2692292SN/A DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n", 2702292SN/A inst->readPC(), inst->seqNum); 2711062SN/A 2722292SN/A depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber); 2731062SN/A 2741062SN/A ++insertedStores; 2751062SN/A } else if (inst->isLoad()) { 2761062SN/A ++insertedLoads; 2771062SN/A } else { 2782292SN/A panic("Unknown type! (most likely a barrier)."); 2791062SN/A } 2801062SN/A} 2811062SN/A 2821062SN/Atemplate <class MemDepPred, class Impl> 2831062SN/Avoid 2842292SN/AMemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) 2851062SN/A{ 2862292SN/A InstSeqNum barr_sn = barr_inst->seqNum; 2872348SN/A // Memory barriers block loads and stores, write barriers only stores. 2882292SN/A if (barr_inst->isMemBarrier()) { 2892292SN/A loadBarrier = true; 2902292SN/A loadBarrierSN = barr_sn; 2912292SN/A storeBarrier = true; 2922292SN/A storeBarrierSN = barr_sn; 2932292SN/A DPRINTF(MemDepUnit, "Inserted a memory barrier\n"); 2942292SN/A } else if (barr_inst->isWriteBarrier()) { 2952292SN/A storeBarrier = true; 2962292SN/A storeBarrierSN = barr_sn; 2972292SN/A DPRINTF(MemDepUnit, "Inserted a write barrier\n"); 2982292SN/A } 2991062SN/A 3002292SN/A unsigned tid = barr_inst->threadNumber; 3011062SN/A 3022292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst); 3031062SN/A 3042292SN/A // Add the MemDepEntry to the hash. 3052292SN/A memDepHash.insert( 3062292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry)); 3072678Sktlim@umich.edu#ifdef DEBUG 3082292SN/A MemDepEntry::memdep_insert++; 3092678Sktlim@umich.edu#endif 3101062SN/A 3112292SN/A // Add the instruction to the instruction list. 3122292SN/A instList[tid].push_back(barr_inst); 3132292SN/A 3142292SN/A inst_entry->listIt = --(instList[tid].end()); 3151062SN/A} 3161062SN/A 3171062SN/Atemplate <class MemDepPred, class Impl> 3181062SN/Avoid 3191062SN/AMemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) 3201062SN/A{ 3212292SN/A DPRINTF(MemDepUnit, "Marking registers as ready for " 3222292SN/A "instruction PC %#x [sn:%lli].\n", 3232292SN/A inst->readPC(), inst->seqNum); 3241062SN/A 3252292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 3261062SN/A 3272292SN/A inst_entry->regsReady = true; 3281062SN/A 3292292SN/A if (inst_entry->memDepReady) { 3302292SN/A DPRINTF(MemDepUnit, "Instruction has its memory " 3311062SN/A "dependencies resolved, adding it to the ready list.\n"); 3321062SN/A 3332292SN/A moveToReady(inst_entry); 3341062SN/A } else { 3352292SN/A DPRINTF(MemDepUnit, "Instruction still waiting on " 3361062SN/A "memory dependency.\n"); 3371062SN/A } 3381061SN/A} 3391061SN/A 3401061SN/Atemplate <class MemDepPred, class Impl> 3411062SN/Avoid 3421062SN/AMemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) 3431061SN/A{ 3442292SN/A DPRINTF(MemDepUnit, "Marking non speculative " 3452292SN/A "instruction PC %#x as ready [sn:%lli].\n", 3462292SN/A inst->readPC(), inst->seqNum); 3471062SN/A 3482292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 3491061SN/A 3502292SN/A moveToReady(inst_entry); 3511061SN/A} 3521061SN/A 3531061SN/Atemplate <class MemDepPred, class Impl> 3541061SN/Avoid 3552292SN/AMemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst) 3561061SN/A{ 3572292SN/A instsToReplay.push_back(inst); 3582292SN/A} 3591061SN/A 3602292SN/Atemplate <class MemDepPred, class Impl> 3612292SN/Avoid 3622292SN/AMemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst) 3632292SN/A{ 3642292SN/A DynInstPtr temp_inst; 3651062SN/A 3662348SN/A // For now this replay function replays all waiting memory ops. 3672292SN/A while (!instsToReplay.empty()) { 3682292SN/A temp_inst = instsToReplay.front(); 3691062SN/A 3702292SN/A MemDepEntryPtr inst_entry = findInHash(temp_inst); 3712292SN/A 3722292SN/A DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x " 3732292SN/A "[sn:%lli].\n", 3742292SN/A temp_inst->readPC(), temp_inst->seqNum); 3752292SN/A 3762292SN/A moveToReady(inst_entry); 3772292SN/A 3782292SN/A instsToReplay.pop_front(); 3792292SN/A } 3802292SN/A} 3812292SN/A 3822292SN/Atemplate <class MemDepPred, class Impl> 3832292SN/Avoid 3842292SN/AMemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst) 3852292SN/A{ 3862292SN/A DPRINTF(MemDepUnit, "Completed mem instruction PC %#x " 3872292SN/A "[sn:%lli].\n", 3882292SN/A inst->readPC(), inst->seqNum); 3892292SN/A 3902292SN/A unsigned tid = inst->threadNumber; 3912292SN/A 3922292SN/A // Remove the instruction from the hash and the list. 3932292SN/A MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 3942292SN/A 3952292SN/A assert(hash_it != memDepHash.end()); 3962292SN/A 3972292SN/A instList[tid].erase((*hash_it).second->listIt); 3982292SN/A 3992292SN/A (*hash_it).second = NULL; 4002292SN/A 4012292SN/A memDepHash.erase(hash_it); 4022678Sktlim@umich.edu#ifdef DEBUG 4032292SN/A MemDepEntry::memdep_erase++; 4042678Sktlim@umich.edu#endif 4052292SN/A} 4062292SN/A 4072292SN/Atemplate <class MemDepPred, class Impl> 4082292SN/Avoid 4092292SN/AMemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst) 4102292SN/A{ 4112292SN/A wakeDependents(inst); 4122292SN/A completed(inst); 4132292SN/A 4142292SN/A InstSeqNum barr_sn = inst->seqNum; 4152292SN/A 4162292SN/A if (inst->isMemBarrier()) { 4172292SN/A assert(loadBarrier && storeBarrier); 4182292SN/A if (loadBarrierSN == barr_sn) 4192292SN/A loadBarrier = false; 4202292SN/A if (storeBarrierSN == barr_sn) 4212292SN/A storeBarrier = false; 4222292SN/A } else if (inst->isWriteBarrier()) { 4232292SN/A assert(storeBarrier); 4242292SN/A if (storeBarrierSN == barr_sn) 4252292SN/A storeBarrier = false; 4262292SN/A } 4271061SN/A} 4281061SN/A 4291061SN/Atemplate <class MemDepPred, class Impl> 4301061SN/Avoid 4311061SN/AMemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 4321061SN/A{ 4332292SN/A // Only stores and barriers have dependents. 4342292SN/A if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) { 4351062SN/A return; 4361062SN/A } 4371062SN/A 4382292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 4391061SN/A 4402292SN/A for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) { 4412292SN/A MemDepEntryPtr woken_inst = inst_entry->dependInsts[i]; 4421062SN/A 4432292SN/A if (!woken_inst->inst) { 4442292SN/A // Potentially removed mem dep entries could be on this list 4452292SN/A continue; 4462292SN/A } 4471061SN/A 4482292SN/A DPRINTF(MemDepUnit, "Waking up a dependent inst, " 4492292SN/A "[sn:%lli].\n", 4502292SN/A woken_inst->inst->seqNum); 4511061SN/A 4522292SN/A if (woken_inst->regsReady && !woken_inst->squashed) { 4531062SN/A moveToReady(woken_inst); 4541062SN/A } else { 4552292SN/A woken_inst->memDepReady = true; 4561062SN/A } 4571061SN/A } 4581061SN/A 4592292SN/A inst_entry->dependInsts.clear(); 4601061SN/A} 4611061SN/A 4621061SN/Atemplate <class MemDepPred, class Impl> 4631061SN/Avoid 4642292SN/AMemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, 4652292SN/A unsigned tid) 4661061SN/A{ 4672292SN/A if (!instsToReplay.empty()) { 4682292SN/A ListIt replay_it = instsToReplay.begin(); 4692292SN/A while (replay_it != instsToReplay.end()) { 4702292SN/A if ((*replay_it)->threadNumber == tid && 4712292SN/A (*replay_it)->seqNum > squashed_num) { 4722292SN/A instsToReplay.erase(replay_it++); 4732292SN/A } else { 4742292SN/A ++replay_it; 4751062SN/A } 4761061SN/A } 4771061SN/A } 4781061SN/A 4792292SN/A ListIt squash_it = instList[tid].end(); 4802292SN/A --squash_it; 4811061SN/A 4822292SN/A MemDepHashIt hash_it; 4831061SN/A 4842292SN/A while (!instList[tid].empty() && 4852292SN/A (*squash_it)->seqNum > squashed_num) { 4861061SN/A 4872292SN/A DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n", 4882292SN/A (*squash_it)->seqNum); 4891061SN/A 4902292SN/A hash_it = memDepHash.find((*squash_it)->seqNum); 4911061SN/A 4922292SN/A assert(hash_it != memDepHash.end()); 4931062SN/A 4942292SN/A (*hash_it).second->squashed = true; 4951717SN/A 4962292SN/A (*hash_it).second = NULL; 4971717SN/A 4982292SN/A memDepHash.erase(hash_it); 4992678Sktlim@umich.edu#ifdef DEBUG 5002292SN/A MemDepEntry::memdep_erase++; 5012678Sktlim@umich.edu#endif 5021717SN/A 5032292SN/A instList[tid].erase(squash_it--); 5041061SN/A } 5051061SN/A 5061061SN/A // Tell the dependency predictor to squash as well. 5072292SN/A depPred.squash(squashed_num, tid); 5081061SN/A} 5091061SN/A 5101061SN/Atemplate <class MemDepPred, class Impl> 5111061SN/Avoid 5121061SN/AMemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 5131061SN/A DynInstPtr &violating_load) 5141061SN/A{ 5152292SN/A DPRINTF(MemDepUnit, "Passing violating PCs to store sets," 5161062SN/A " load: %#x, store: %#x\n", violating_load->readPC(), 5171062SN/A store_inst->readPC()); 5181061SN/A // Tell the memory dependence unit of the violation. 5191061SN/A depPred.violation(violating_load->readPC(), store_inst->readPC()); 5201061SN/A} 5211062SN/A 5221062SN/Atemplate <class MemDepPred, class Impl> 5232292SN/Avoid 5242292SN/AMemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 5252292SN/A{ 5262292SN/A DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", 5272292SN/A inst->readPC(), inst->seqNum); 5282292SN/A 5292292SN/A depPred.issued(inst->readPC(), inst->seqNum, inst->isStore()); 5302292SN/A} 5312292SN/A 5322292SN/Atemplate <class MemDepPred, class Impl> 5332292SN/Ainline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr & 5342292SN/AMemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst) 5352292SN/A{ 5362292SN/A MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 5372292SN/A 5382292SN/A assert(hash_it != memDepHash.end()); 5392292SN/A 5402292SN/A return (*hash_it).second; 5412292SN/A} 5422292SN/A 5432292SN/Atemplate <class MemDepPred, class Impl> 5441062SN/Ainline void 5452292SN/AMemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry) 5461062SN/A{ 5472292SN/A DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] " 5482292SN/A "to the ready list.\n", woken_inst_entry->inst->seqNum); 5491062SN/A 5502292SN/A assert(!woken_inst_entry->squashed); 5511062SN/A 5522292SN/A iqPtr->addReadyMemInst(woken_inst_entry->inst); 5531062SN/A} 5542292SN/A 5552292SN/A 5562292SN/Atemplate <class MemDepPred, class Impl> 5572292SN/Avoid 5582292SN/AMemDepUnit<MemDepPred, Impl>::dumpLists() 5592292SN/A{ 5602292SN/A for (unsigned tid=0; tid < Impl::MaxThreads; tid++) { 5612292SN/A cprintf("Instruction list %i size: %i\n", 5622292SN/A tid, instList[tid].size()); 5632292SN/A 5642292SN/A ListIt inst_list_it = instList[tid].begin(); 5652292SN/A int num = 0; 5662292SN/A 5672292SN/A while (inst_list_it != instList[tid].end()) { 5682292SN/A cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n" 5692292SN/A "Squashed:%i\n\n", 5702292SN/A num, (*inst_list_it)->readPC(), 5712292SN/A (*inst_list_it)->seqNum, 5722292SN/A (*inst_list_it)->threadNumber, 5732292SN/A (*inst_list_it)->isIssued(), 5742292SN/A (*inst_list_it)->isSquashed()); 5752292SN/A inst_list_it++; 5762292SN/A ++num; 5772292SN/A } 5782292SN/A } 5792292SN/A 5802292SN/A cprintf("Memory dependence hash size: %i\n", memDepHash.size()); 5812292SN/A 5822678Sktlim@umich.edu#ifdef DEBUG 5832292SN/A cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); 5842678Sktlim@umich.edu#endif 5852292SN/A} 586