mem_dep_unit_impl.hh revision 4033
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301061SN/A 311061SN/A#include <map> 321061SN/A 332292SN/A#include "cpu/o3/inst_queue.hh" 341717SN/A#include "cpu/o3/mem_dep_unit.hh" 351061SN/A 361061SN/Atemplate <class MemDepPred, class Impl> 373500Sktlim@umich.eduMemDepUnit<MemDepPred, Impl>::MemDepUnit() 383500Sktlim@umich.edu : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 393500Sktlim@umich.edu storeBarrierSN(0), iqPtr(NULL) 403500Sktlim@umich.edu{ 413500Sktlim@umich.edu} 423500Sktlim@umich.edu 433500Sktlim@umich.edutemplate <class MemDepPred, class Impl> 442292SN/AMemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params) 452292SN/A : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), 462292SN/A loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL) 471061SN/A{ 482292SN/A DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); 492292SN/A} 502292SN/A 512292SN/Atemplate <class MemDepPred, class Impl> 522292SN/AMemDepUnit<MemDepPred, Impl>::~MemDepUnit() 532292SN/A{ 542292SN/A for (int tid=0; tid < Impl::MaxThreads; tid++) { 552292SN/A 562292SN/A ListIt inst_list_it = instList[tid].begin(); 572292SN/A 582292SN/A MemDepHashIt hash_it; 592292SN/A 602292SN/A while (!instList[tid].empty()) { 612292SN/A hash_it = memDepHash.find((*inst_list_it)->seqNum); 622292SN/A 632292SN/A assert(hash_it != memDepHash.end()); 642292SN/A 652292SN/A memDepHash.erase(hash_it); 662292SN/A 672292SN/A instList[tid].erase(inst_list_it++); 682292SN/A } 692292SN/A } 702292SN/A 712678Sktlim@umich.edu#ifdef DEBUG 722292SN/A assert(MemDepEntry::memdep_count == 0); 732678Sktlim@umich.edu#endif 742292SN/A} 752292SN/A 762292SN/Atemplate <class MemDepPred, class Impl> 772292SN/Astd::string 782292SN/AMemDepUnit<MemDepPred, Impl>::name() const 792292SN/A{ 802292SN/A return "memdepunit"; 812292SN/A} 822292SN/A 832292SN/Atemplate <class MemDepPred, class Impl> 842292SN/Avoid 852292SN/AMemDepUnit<MemDepPred, Impl>::init(Params *params, int tid) 862292SN/A{ 872292SN/A DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid); 882292SN/A 892292SN/A id = tid; 902292SN/A 912292SN/A depPred.init(params->SSITSize, params->LFSTSize); 921061SN/A} 931061SN/A 941061SN/Atemplate <class MemDepPred, class Impl> 951061SN/Avoid 961062SN/AMemDepUnit<MemDepPred, Impl>::regStats() 971062SN/A{ 981062SN/A insertedLoads 991062SN/A .name(name() + ".memDep.insertedLoads") 1001062SN/A .desc("Number of loads inserted to the mem dependence unit."); 1011062SN/A 1021062SN/A insertedStores 1031062SN/A .name(name() + ".memDep.insertedStores") 1041062SN/A .desc("Number of stores inserted to the mem dependence unit."); 1051062SN/A 1061062SN/A conflictingLoads 1071062SN/A .name(name() + ".memDep.conflictingLoads") 1081062SN/A .desc("Number of conflicting loads."); 1091062SN/A 1101062SN/A conflictingStores 1111062SN/A .name(name() + ".memDep.conflictingStores") 1121062SN/A .desc("Number of conflicting stores."); 1131062SN/A} 1141062SN/A 1151062SN/Atemplate <class MemDepPred, class Impl> 1161062SN/Avoid 1172307SN/AMemDepUnit<MemDepPred, Impl>::switchOut() 1182307SN/A{ 1192367SN/A assert(instList[0].empty()); 1202367SN/A assert(instsToReplay.empty()); 1212367SN/A assert(memDepHash.empty()); 1222348SN/A // Clear any state. 1232307SN/A for (int i = 0; i < Impl::MaxThreads; ++i) { 1242307SN/A instList[i].clear(); 1252307SN/A } 1262307SN/A instsToReplay.clear(); 1272307SN/A memDepHash.clear(); 1282307SN/A} 1292307SN/A 1302307SN/Atemplate <class MemDepPred, class Impl> 1312307SN/Avoid 1322307SN/AMemDepUnit<MemDepPred, Impl>::takeOverFrom() 1332307SN/A{ 1342348SN/A // Be sure to reset all state. 1352307SN/A loadBarrier = storeBarrier = false; 1362307SN/A loadBarrierSN = storeBarrierSN = 0; 1372307SN/A depPred.clear(); 1382307SN/A} 1392307SN/A 1402307SN/Atemplate <class MemDepPred, class Impl> 1412307SN/Avoid 1422292SN/AMemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) 1432292SN/A{ 1442292SN/A iqPtr = iq_ptr; 1452292SN/A} 1462292SN/A 1472292SN/Atemplate <class MemDepPred, class Impl> 1482292SN/Avoid 1491061SN/AMemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 1501061SN/A{ 1512292SN/A unsigned tid = inst->threadNumber; 1521061SN/A 1532292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(inst); 1541061SN/A 1552292SN/A // Add the MemDepEntry to the hash. 1562292SN/A memDepHash.insert( 1572292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 1582678Sktlim@umich.edu#ifdef DEBUG 1592292SN/A MemDepEntry::memdep_insert++; 1602678Sktlim@umich.edu#endif 1611061SN/A 1622292SN/A instList[tid].push_back(inst); 1631062SN/A 1642292SN/A inst_entry->listIt = --(instList[tid].end()); 1651062SN/A 1662329SN/A // Check any barriers and the dependence predictor for any 1672348SN/A // producing memrefs/stores. 1682292SN/A InstSeqNum producing_store; 1692292SN/A if (inst->isLoad() && loadBarrier) { 1703500Sktlim@umich.edu DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n", 1713500Sktlim@umich.edu loadBarrierSN); 1722292SN/A producing_store = loadBarrierSN; 1732292SN/A } else if (inst->isStore() && storeBarrier) { 1743500Sktlim@umich.edu DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n", 1753500Sktlim@umich.edu storeBarrierSN); 1762292SN/A producing_store = storeBarrierSN; 1772292SN/A } else { 1782292SN/A producing_store = depPred.checkInst(inst->readPC()); 1792292SN/A } 1802292SN/A 1812292SN/A MemDepEntryPtr store_entry = NULL; 1822292SN/A 1832292SN/A // If there is a producing store, try to find the entry. 1842292SN/A if (producing_store != 0) { 1853500Sktlim@umich.edu DPRINTF(MemDepUnit, "Searching for producer\n"); 1862292SN/A MemDepHashIt hash_it = memDepHash.find(producing_store); 1872292SN/A 1882292SN/A if (hash_it != memDepHash.end()) { 1892292SN/A store_entry = (*hash_it).second; 1903500Sktlim@umich.edu DPRINTF(MemDepUnit, "Proucer found\n"); 1912292SN/A } 1922292SN/A } 1932292SN/A 1942292SN/A // If no store entry, then instruction can issue as soon as the registers 1952292SN/A // are ready. 1962292SN/A if (!store_entry) { 1972292SN/A DPRINTF(MemDepUnit, "No dependency for inst PC " 1982292SN/A "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum); 1992292SN/A 2002292SN/A inst_entry->memDepReady = true; 2011062SN/A 2021062SN/A if (inst->readyToIssue()) { 2032292SN/A inst_entry->regsReady = true; 2041062SN/A 2052292SN/A moveToReady(inst_entry); 2061062SN/A } 2071061SN/A } else { 2082329SN/A // Otherwise make the instruction dependent on the store/barrier. 2092292SN/A DPRINTF(MemDepUnit, "Adding to dependency list; " 2102292SN/A "inst PC %#x is dependent on [sn:%lli].\n", 2111062SN/A inst->readPC(), producing_store); 2121062SN/A 2131062SN/A if (inst->readyToIssue()) { 2142292SN/A inst_entry->regsReady = true; 2151062SN/A } 2161062SN/A 2174033Sktlim@umich.edu // Clear the bit saying this instruction can issue. 2184033Sktlim@umich.edu inst->clearCanIssue(); 2194033Sktlim@umich.edu 2201062SN/A // Add this instruction to the list of dependents. 2212292SN/A store_entry->dependInsts.push_back(inst_entry); 2221062SN/A 2231062SN/A if (inst->isLoad()) { 2241062SN/A ++conflictingLoads; 2251062SN/A } else { 2261062SN/A ++conflictingStores; 2271062SN/A } 2281061SN/A } 2291061SN/A 2301061SN/A if (inst->isStore()) { 2312292SN/A DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n", 2322292SN/A inst->readPC(), inst->seqNum); 2331062SN/A 2342292SN/A depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber); 2351062SN/A 2361062SN/A ++insertedStores; 2371062SN/A } else if (inst->isLoad()) { 2381062SN/A ++insertedLoads; 2391062SN/A } else { 2402292SN/A panic("Unknown type! (most likely a barrier)."); 2411061SN/A } 2421062SN/A} 2431062SN/A 2441062SN/Atemplate <class MemDepPred, class Impl> 2451062SN/Avoid 2461062SN/AMemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 2471062SN/A{ 2482292SN/A unsigned tid = inst->threadNumber; 2491062SN/A 2502292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(inst); 2511062SN/A 2522292SN/A // Insert the MemDepEntry into the hash. 2532292SN/A memDepHash.insert( 2542292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 2552678Sktlim@umich.edu#ifdef DEBUG 2562292SN/A MemDepEntry::memdep_insert++; 2572678Sktlim@umich.edu#endif 2581062SN/A 2592292SN/A // Add the instruction to the list. 2602292SN/A instList[tid].push_back(inst); 2612292SN/A 2622292SN/A inst_entry->listIt = --(instList[tid].end()); 2631062SN/A 2641062SN/A // Might want to turn this part into an inline function or something. 2651062SN/A // It's shared between both insert functions. 2661062SN/A if (inst->isStore()) { 2672292SN/A DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n", 2682292SN/A inst->readPC(), inst->seqNum); 2691062SN/A 2702292SN/A depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber); 2711062SN/A 2721062SN/A ++insertedStores; 2731062SN/A } else if (inst->isLoad()) { 2741062SN/A ++insertedLoads; 2751062SN/A } else { 2762292SN/A panic("Unknown type! (most likely a barrier)."); 2771062SN/A } 2781062SN/A} 2791062SN/A 2801062SN/Atemplate <class MemDepPred, class Impl> 2811062SN/Avoid 2822292SN/AMemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) 2831062SN/A{ 2842292SN/A InstSeqNum barr_sn = barr_inst->seqNum; 2852348SN/A // Memory barriers block loads and stores, write barriers only stores. 2862292SN/A if (barr_inst->isMemBarrier()) { 2872292SN/A loadBarrier = true; 2882292SN/A loadBarrierSN = barr_sn; 2892292SN/A storeBarrier = true; 2902292SN/A storeBarrierSN = barr_sn; 2912292SN/A DPRINTF(MemDepUnit, "Inserted a memory barrier\n"); 2922292SN/A } else if (barr_inst->isWriteBarrier()) { 2932292SN/A storeBarrier = true; 2942292SN/A storeBarrierSN = barr_sn; 2952292SN/A DPRINTF(MemDepUnit, "Inserted a write barrier\n"); 2962292SN/A } 2971062SN/A 2982292SN/A unsigned tid = barr_inst->threadNumber; 2991062SN/A 3002292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst); 3011062SN/A 3022292SN/A // Add the MemDepEntry to the hash. 3032292SN/A memDepHash.insert( 3042292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry)); 3052678Sktlim@umich.edu#ifdef DEBUG 3062292SN/A MemDepEntry::memdep_insert++; 3072678Sktlim@umich.edu#endif 3081062SN/A 3092292SN/A // Add the instruction to the instruction list. 3102292SN/A instList[tid].push_back(barr_inst); 3112292SN/A 3122292SN/A inst_entry->listIt = --(instList[tid].end()); 3131062SN/A} 3141062SN/A 3151062SN/Atemplate <class MemDepPred, class Impl> 3161062SN/Avoid 3171062SN/AMemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) 3181062SN/A{ 3192292SN/A DPRINTF(MemDepUnit, "Marking registers as ready for " 3202292SN/A "instruction PC %#x [sn:%lli].\n", 3212292SN/A inst->readPC(), inst->seqNum); 3221062SN/A 3232292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 3241062SN/A 3252292SN/A inst_entry->regsReady = true; 3261062SN/A 3272292SN/A if (inst_entry->memDepReady) { 3282292SN/A DPRINTF(MemDepUnit, "Instruction has its memory " 3291062SN/A "dependencies resolved, adding it to the ready list.\n"); 3301062SN/A 3312292SN/A moveToReady(inst_entry); 3321062SN/A } else { 3332292SN/A DPRINTF(MemDepUnit, "Instruction still waiting on " 3341062SN/A "memory dependency.\n"); 3351062SN/A } 3361061SN/A} 3371061SN/A 3381061SN/Atemplate <class MemDepPred, class Impl> 3391062SN/Avoid 3401062SN/AMemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) 3411061SN/A{ 3422292SN/A DPRINTF(MemDepUnit, "Marking non speculative " 3432292SN/A "instruction PC %#x as ready [sn:%lli].\n", 3442292SN/A inst->readPC(), inst->seqNum); 3451062SN/A 3462292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 3471061SN/A 3482292SN/A moveToReady(inst_entry); 3491061SN/A} 3501061SN/A 3511061SN/Atemplate <class MemDepPred, class Impl> 3521061SN/Avoid 3532292SN/AMemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst) 3541061SN/A{ 3552292SN/A instsToReplay.push_back(inst); 3562292SN/A} 3571061SN/A 3582292SN/Atemplate <class MemDepPred, class Impl> 3592292SN/Avoid 3602292SN/AMemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst) 3612292SN/A{ 3622292SN/A DynInstPtr temp_inst; 3631062SN/A 3642348SN/A // For now this replay function replays all waiting memory ops. 3652292SN/A while (!instsToReplay.empty()) { 3662292SN/A temp_inst = instsToReplay.front(); 3671062SN/A 3682292SN/A MemDepEntryPtr inst_entry = findInHash(temp_inst); 3692292SN/A 3702292SN/A DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x " 3712292SN/A "[sn:%lli].\n", 3722292SN/A temp_inst->readPC(), temp_inst->seqNum); 3732292SN/A 3742292SN/A moveToReady(inst_entry); 3752292SN/A 3762292SN/A instsToReplay.pop_front(); 3772292SN/A } 3782292SN/A} 3792292SN/A 3802292SN/Atemplate <class MemDepPred, class Impl> 3812292SN/Avoid 3822292SN/AMemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst) 3832292SN/A{ 3842292SN/A DPRINTF(MemDepUnit, "Completed mem instruction PC %#x " 3852292SN/A "[sn:%lli].\n", 3862292SN/A inst->readPC(), inst->seqNum); 3872292SN/A 3882292SN/A unsigned tid = inst->threadNumber; 3892292SN/A 3902292SN/A // Remove the instruction from the hash and the list. 3912292SN/A MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 3922292SN/A 3932292SN/A assert(hash_it != memDepHash.end()); 3942292SN/A 3952292SN/A instList[tid].erase((*hash_it).second->listIt); 3962292SN/A 3972292SN/A (*hash_it).second = NULL; 3982292SN/A 3992292SN/A memDepHash.erase(hash_it); 4002678Sktlim@umich.edu#ifdef DEBUG 4012292SN/A MemDepEntry::memdep_erase++; 4022678Sktlim@umich.edu#endif 4032292SN/A} 4042292SN/A 4052292SN/Atemplate <class MemDepPred, class Impl> 4062292SN/Avoid 4072292SN/AMemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst) 4082292SN/A{ 4092292SN/A wakeDependents(inst); 4102292SN/A completed(inst); 4112292SN/A 4122292SN/A InstSeqNum barr_sn = inst->seqNum; 4132292SN/A 4142292SN/A if (inst->isMemBarrier()) { 4152292SN/A assert(loadBarrier && storeBarrier); 4162292SN/A if (loadBarrierSN == barr_sn) 4172292SN/A loadBarrier = false; 4182292SN/A if (storeBarrierSN == barr_sn) 4192292SN/A storeBarrier = false; 4202292SN/A } else if (inst->isWriteBarrier()) { 4212292SN/A assert(storeBarrier); 4222292SN/A if (storeBarrierSN == barr_sn) 4232292SN/A storeBarrier = false; 4242292SN/A } 4251061SN/A} 4261061SN/A 4271061SN/Atemplate <class MemDepPred, class Impl> 4281061SN/Avoid 4291061SN/AMemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 4301061SN/A{ 4312292SN/A // Only stores and barriers have dependents. 4322292SN/A if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) { 4331062SN/A return; 4341062SN/A } 4351062SN/A 4362292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 4371061SN/A 4382292SN/A for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) { 4392292SN/A MemDepEntryPtr woken_inst = inst_entry->dependInsts[i]; 4401062SN/A 4412292SN/A if (!woken_inst->inst) { 4422292SN/A // Potentially removed mem dep entries could be on this list 4432292SN/A continue; 4442292SN/A } 4451061SN/A 4462292SN/A DPRINTF(MemDepUnit, "Waking up a dependent inst, " 4472292SN/A "[sn:%lli].\n", 4482292SN/A woken_inst->inst->seqNum); 4491061SN/A 4502292SN/A if (woken_inst->regsReady && !woken_inst->squashed) { 4511062SN/A moveToReady(woken_inst); 4521062SN/A } else { 4532292SN/A woken_inst->memDepReady = true; 4541062SN/A } 4551061SN/A } 4561061SN/A 4572292SN/A inst_entry->dependInsts.clear(); 4581061SN/A} 4591061SN/A 4601061SN/Atemplate <class MemDepPred, class Impl> 4611061SN/Avoid 4622292SN/AMemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, 4632292SN/A unsigned tid) 4641061SN/A{ 4652292SN/A if (!instsToReplay.empty()) { 4662292SN/A ListIt replay_it = instsToReplay.begin(); 4672292SN/A while (replay_it != instsToReplay.end()) { 4682292SN/A if ((*replay_it)->threadNumber == tid && 4692292SN/A (*replay_it)->seqNum > squashed_num) { 4702292SN/A instsToReplay.erase(replay_it++); 4712292SN/A } else { 4722292SN/A ++replay_it; 4731062SN/A } 4741061SN/A } 4751061SN/A } 4761061SN/A 4772292SN/A ListIt squash_it = instList[tid].end(); 4782292SN/A --squash_it; 4791061SN/A 4802292SN/A MemDepHashIt hash_it; 4811061SN/A 4822292SN/A while (!instList[tid].empty() && 4832292SN/A (*squash_it)->seqNum > squashed_num) { 4841061SN/A 4852292SN/A DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n", 4862292SN/A (*squash_it)->seqNum); 4871061SN/A 4882292SN/A hash_it = memDepHash.find((*squash_it)->seqNum); 4891061SN/A 4902292SN/A assert(hash_it != memDepHash.end()); 4911062SN/A 4922292SN/A (*hash_it).second->squashed = true; 4931717SN/A 4942292SN/A (*hash_it).second = NULL; 4951717SN/A 4962292SN/A memDepHash.erase(hash_it); 4972678Sktlim@umich.edu#ifdef DEBUG 4982292SN/A MemDepEntry::memdep_erase++; 4992678Sktlim@umich.edu#endif 5001717SN/A 5012292SN/A instList[tid].erase(squash_it--); 5021061SN/A } 5031061SN/A 5041061SN/A // Tell the dependency predictor to squash as well. 5052292SN/A depPred.squash(squashed_num, tid); 5061061SN/A} 5071061SN/A 5081061SN/Atemplate <class MemDepPred, class Impl> 5091061SN/Avoid 5101061SN/AMemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 5111061SN/A DynInstPtr &violating_load) 5121061SN/A{ 5132292SN/A DPRINTF(MemDepUnit, "Passing violating PCs to store sets," 5141062SN/A " load: %#x, store: %#x\n", violating_load->readPC(), 5151062SN/A store_inst->readPC()); 5161061SN/A // Tell the memory dependence unit of the violation. 5171061SN/A depPred.violation(violating_load->readPC(), store_inst->readPC()); 5181061SN/A} 5191062SN/A 5201062SN/Atemplate <class MemDepPred, class Impl> 5212292SN/Avoid 5222292SN/AMemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 5232292SN/A{ 5242292SN/A DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", 5252292SN/A inst->readPC(), inst->seqNum); 5262292SN/A 5272292SN/A depPred.issued(inst->readPC(), inst->seqNum, inst->isStore()); 5282292SN/A} 5292292SN/A 5302292SN/Atemplate <class MemDepPred, class Impl> 5312292SN/Ainline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr & 5322292SN/AMemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst) 5332292SN/A{ 5342292SN/A MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 5352292SN/A 5362292SN/A assert(hash_it != memDepHash.end()); 5372292SN/A 5382292SN/A return (*hash_it).second; 5392292SN/A} 5402292SN/A 5412292SN/Atemplate <class MemDepPred, class Impl> 5421062SN/Ainline void 5432292SN/AMemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry) 5441062SN/A{ 5452292SN/A DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] " 5462292SN/A "to the ready list.\n", woken_inst_entry->inst->seqNum); 5471062SN/A 5482292SN/A assert(!woken_inst_entry->squashed); 5491062SN/A 5502292SN/A iqPtr->addReadyMemInst(woken_inst_entry->inst); 5511062SN/A} 5522292SN/A 5532292SN/A 5542292SN/Atemplate <class MemDepPred, class Impl> 5552292SN/Avoid 5562292SN/AMemDepUnit<MemDepPred, Impl>::dumpLists() 5572292SN/A{ 5582292SN/A for (unsigned tid=0; tid < Impl::MaxThreads; tid++) { 5592292SN/A cprintf("Instruction list %i size: %i\n", 5602292SN/A tid, instList[tid].size()); 5612292SN/A 5622292SN/A ListIt inst_list_it = instList[tid].begin(); 5632292SN/A int num = 0; 5642292SN/A 5652292SN/A while (inst_list_it != instList[tid].end()) { 5662292SN/A cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n" 5672292SN/A "Squashed:%i\n\n", 5682292SN/A num, (*inst_list_it)->readPC(), 5692292SN/A (*inst_list_it)->seqNum, 5702292SN/A (*inst_list_it)->threadNumber, 5712292SN/A (*inst_list_it)->isIssued(), 5722292SN/A (*inst_list_it)->isSquashed()); 5732292SN/A inst_list_it++; 5742292SN/A ++num; 5752292SN/A } 5762292SN/A } 5772292SN/A 5782292SN/A cprintf("Memory dependence hash size: %i\n", memDepHash.size()); 5792292SN/A 5802678Sktlim@umich.edu#ifdef DEBUG 5812292SN/A cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); 5822678Sktlim@umich.edu#endif 5832292SN/A} 584