mem_dep_unit_impl.hh revision 2678
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301061SN/A 311061SN/A#include <map> 321061SN/A 332292SN/A#include "cpu/o3/inst_queue.hh" 341717SN/A#include "cpu/o3/mem_dep_unit.hh" 351061SN/A 361061SN/Atemplate <class MemDepPred, class Impl> 372292SN/AMemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params) 382292SN/A : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), 392292SN/A loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL) 401061SN/A{ 412292SN/A DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); 422292SN/A} 432292SN/A 442292SN/Atemplate <class MemDepPred, class Impl> 452292SN/AMemDepUnit<MemDepPred, Impl>::~MemDepUnit() 462292SN/A{ 472292SN/A for (int tid=0; tid < Impl::MaxThreads; tid++) { 482292SN/A 492292SN/A ListIt inst_list_it = instList[tid].begin(); 502292SN/A 512292SN/A MemDepHashIt hash_it; 522292SN/A 532292SN/A while (!instList[tid].empty()) { 542292SN/A hash_it = memDepHash.find((*inst_list_it)->seqNum); 552292SN/A 562292SN/A assert(hash_it != memDepHash.end()); 572292SN/A 582292SN/A memDepHash.erase(hash_it); 592292SN/A 602292SN/A instList[tid].erase(inst_list_it++); 612292SN/A } 622292SN/A } 632292SN/A 642678Sktlim@umich.edu#ifdef DEBUG 652292SN/A assert(MemDepEntry::memdep_count == 0); 662678Sktlim@umich.edu#endif 672292SN/A} 682292SN/A 692292SN/Atemplate <class MemDepPred, class Impl> 702292SN/Astd::string 712292SN/AMemDepUnit<MemDepPred, Impl>::name() const 722292SN/A{ 732292SN/A return "memdepunit"; 742292SN/A} 752292SN/A 762292SN/Atemplate <class MemDepPred, class Impl> 772292SN/Avoid 782292SN/AMemDepUnit<MemDepPred, Impl>::init(Params *params, int tid) 792292SN/A{ 802292SN/A DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid); 812292SN/A 822292SN/A id = tid; 832292SN/A 842292SN/A depPred.init(params->SSITSize, params->LFSTSize); 851061SN/A} 861061SN/A 871061SN/Atemplate <class MemDepPred, class Impl> 881061SN/Avoid 891062SN/AMemDepUnit<MemDepPred, Impl>::regStats() 901062SN/A{ 911062SN/A insertedLoads 921062SN/A .name(name() + ".memDep.insertedLoads") 931062SN/A .desc("Number of loads inserted to the mem dependence unit."); 941062SN/A 951062SN/A insertedStores 961062SN/A .name(name() + ".memDep.insertedStores") 971062SN/A .desc("Number of stores inserted to the mem dependence unit."); 981062SN/A 991062SN/A conflictingLoads 1001062SN/A .name(name() + ".memDep.conflictingLoads") 1011062SN/A .desc("Number of conflicting loads."); 1021062SN/A 1031062SN/A conflictingStores 1041062SN/A .name(name() + ".memDep.conflictingStores") 1051062SN/A .desc("Number of conflicting stores."); 1061062SN/A} 1071062SN/A 1081062SN/Atemplate <class MemDepPred, class Impl> 1091062SN/Avoid 1102307SN/AMemDepUnit<MemDepPred, Impl>::switchOut() 1112307SN/A{ 1122348SN/A // Clear any state. 1132307SN/A for (int i = 0; i < Impl::MaxThreads; ++i) { 1142307SN/A instList[i].clear(); 1152307SN/A } 1162307SN/A instsToReplay.clear(); 1172307SN/A memDepHash.clear(); 1182307SN/A} 1192307SN/A 1202307SN/Atemplate <class MemDepPred, class Impl> 1212307SN/Avoid 1222307SN/AMemDepUnit<MemDepPred, Impl>::takeOverFrom() 1232307SN/A{ 1242348SN/A // Be sure to reset all state. 1252307SN/A loadBarrier = storeBarrier = false; 1262307SN/A loadBarrierSN = storeBarrierSN = 0; 1272307SN/A depPred.clear(); 1282307SN/A} 1292307SN/A 1302307SN/Atemplate <class MemDepPred, class Impl> 1312307SN/Avoid 1322292SN/AMemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) 1332292SN/A{ 1342292SN/A iqPtr = iq_ptr; 1352292SN/A} 1362292SN/A 1372292SN/Atemplate <class MemDepPred, class Impl> 1382292SN/Avoid 1391061SN/AMemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 1401061SN/A{ 1412292SN/A unsigned tid = inst->threadNumber; 1421061SN/A 1432292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(inst); 1441061SN/A 1452292SN/A // Add the MemDepEntry to the hash. 1462292SN/A memDepHash.insert( 1472292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 1482678Sktlim@umich.edu#ifdef DEBUG 1492292SN/A MemDepEntry::memdep_insert++; 1502678Sktlim@umich.edu#endif 1511061SN/A 1522292SN/A instList[tid].push_back(inst); 1531062SN/A 1542292SN/A inst_entry->listIt = --(instList[tid].end()); 1551062SN/A 1562329SN/A // Check any barriers and the dependence predictor for any 1572348SN/A // producing memrefs/stores. 1582292SN/A InstSeqNum producing_store; 1592292SN/A if (inst->isLoad() && loadBarrier) { 1602292SN/A producing_store = loadBarrierSN; 1612292SN/A } else if (inst->isStore() && storeBarrier) { 1622292SN/A producing_store = storeBarrierSN; 1632292SN/A } else { 1642292SN/A producing_store = depPred.checkInst(inst->readPC()); 1652292SN/A } 1662292SN/A 1672292SN/A MemDepEntryPtr store_entry = NULL; 1682292SN/A 1692292SN/A // If there is a producing store, try to find the entry. 1702292SN/A if (producing_store != 0) { 1712292SN/A MemDepHashIt hash_it = memDepHash.find(producing_store); 1722292SN/A 1732292SN/A if (hash_it != memDepHash.end()) { 1742292SN/A store_entry = (*hash_it).second; 1752292SN/A } 1762292SN/A } 1772292SN/A 1782292SN/A // If no store entry, then instruction can issue as soon as the registers 1792292SN/A // are ready. 1802292SN/A if (!store_entry) { 1812292SN/A DPRINTF(MemDepUnit, "No dependency for inst PC " 1822292SN/A "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum); 1832292SN/A 1842292SN/A inst_entry->memDepReady = true; 1851062SN/A 1861062SN/A if (inst->readyToIssue()) { 1872292SN/A inst_entry->regsReady = true; 1881062SN/A 1892292SN/A moveToReady(inst_entry); 1901062SN/A } 1911061SN/A } else { 1922329SN/A // Otherwise make the instruction dependent on the store/barrier. 1932292SN/A DPRINTF(MemDepUnit, "Adding to dependency list; " 1942292SN/A "inst PC %#x is dependent on [sn:%lli].\n", 1951062SN/A inst->readPC(), producing_store); 1961062SN/A 1971062SN/A if (inst->readyToIssue()) { 1982292SN/A inst_entry->regsReady = true; 1991062SN/A } 2001062SN/A 2011062SN/A // Add this instruction to the list of dependents. 2022292SN/A store_entry->dependInsts.push_back(inst_entry); 2031062SN/A 2041062SN/A if (inst->isLoad()) { 2051062SN/A ++conflictingLoads; 2061062SN/A } else { 2071062SN/A ++conflictingStores; 2081062SN/A } 2091061SN/A } 2101061SN/A 2111061SN/A if (inst->isStore()) { 2122292SN/A DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n", 2132292SN/A inst->readPC(), inst->seqNum); 2141062SN/A 2152292SN/A depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber); 2161062SN/A 2171062SN/A ++insertedStores; 2181062SN/A } else if (inst->isLoad()) { 2191062SN/A ++insertedLoads; 2201062SN/A } else { 2212292SN/A panic("Unknown type! (most likely a barrier)."); 2221061SN/A } 2231062SN/A} 2241062SN/A 2251062SN/Atemplate <class MemDepPred, class Impl> 2261062SN/Avoid 2271062SN/AMemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 2281062SN/A{ 2292292SN/A unsigned tid = inst->threadNumber; 2301062SN/A 2312292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(inst); 2321062SN/A 2332292SN/A // Insert the MemDepEntry into the hash. 2342292SN/A memDepHash.insert( 2352292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 2362678Sktlim@umich.edu#ifdef DEBUG 2372292SN/A MemDepEntry::memdep_insert++; 2382678Sktlim@umich.edu#endif 2391062SN/A 2402292SN/A // Add the instruction to the list. 2412292SN/A instList[tid].push_back(inst); 2422292SN/A 2432292SN/A inst_entry->listIt = --(instList[tid].end()); 2441062SN/A 2451062SN/A // Might want to turn this part into an inline function or something. 2461062SN/A // It's shared between both insert functions. 2471062SN/A if (inst->isStore()) { 2482292SN/A DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n", 2492292SN/A inst->readPC(), inst->seqNum); 2501062SN/A 2512292SN/A depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber); 2521062SN/A 2531062SN/A ++insertedStores; 2541062SN/A } else if (inst->isLoad()) { 2551062SN/A ++insertedLoads; 2561062SN/A } else { 2572292SN/A panic("Unknown type! (most likely a barrier)."); 2581062SN/A } 2591062SN/A} 2601062SN/A 2611062SN/Atemplate <class MemDepPred, class Impl> 2621062SN/Avoid 2632292SN/AMemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) 2641062SN/A{ 2652292SN/A InstSeqNum barr_sn = barr_inst->seqNum; 2662348SN/A // Memory barriers block loads and stores, write barriers only stores. 2672292SN/A if (barr_inst->isMemBarrier()) { 2682292SN/A loadBarrier = true; 2692292SN/A loadBarrierSN = barr_sn; 2702292SN/A storeBarrier = true; 2712292SN/A storeBarrierSN = barr_sn; 2722292SN/A DPRINTF(MemDepUnit, "Inserted a memory barrier\n"); 2732292SN/A } else if (barr_inst->isWriteBarrier()) { 2742292SN/A storeBarrier = true; 2752292SN/A storeBarrierSN = barr_sn; 2762292SN/A DPRINTF(MemDepUnit, "Inserted a write barrier\n"); 2772292SN/A } 2781062SN/A 2792292SN/A unsigned tid = barr_inst->threadNumber; 2801062SN/A 2812292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst); 2821062SN/A 2832292SN/A // Add the MemDepEntry to the hash. 2842292SN/A memDepHash.insert( 2852292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry)); 2862678Sktlim@umich.edu#ifdef DEBUG 2872292SN/A MemDepEntry::memdep_insert++; 2882678Sktlim@umich.edu#endif 2891062SN/A 2902292SN/A // Add the instruction to the instruction list. 2912292SN/A instList[tid].push_back(barr_inst); 2922292SN/A 2932292SN/A inst_entry->listIt = --(instList[tid].end()); 2941062SN/A} 2951062SN/A 2961062SN/Atemplate <class MemDepPred, class Impl> 2971062SN/Avoid 2981062SN/AMemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) 2991062SN/A{ 3002292SN/A DPRINTF(MemDepUnit, "Marking registers as ready for " 3012292SN/A "instruction PC %#x [sn:%lli].\n", 3022292SN/A inst->readPC(), inst->seqNum); 3031062SN/A 3042292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 3051062SN/A 3062292SN/A inst_entry->regsReady = true; 3071062SN/A 3082292SN/A if (inst_entry->memDepReady) { 3092292SN/A DPRINTF(MemDepUnit, "Instruction has its memory " 3101062SN/A "dependencies resolved, adding it to the ready list.\n"); 3111062SN/A 3122292SN/A moveToReady(inst_entry); 3131062SN/A } else { 3142292SN/A DPRINTF(MemDepUnit, "Instruction still waiting on " 3151062SN/A "memory dependency.\n"); 3161062SN/A } 3171061SN/A} 3181061SN/A 3191061SN/Atemplate <class MemDepPred, class Impl> 3201062SN/Avoid 3211062SN/AMemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) 3221061SN/A{ 3232292SN/A DPRINTF(MemDepUnit, "Marking non speculative " 3242292SN/A "instruction PC %#x as ready [sn:%lli].\n", 3252292SN/A inst->readPC(), inst->seqNum); 3261062SN/A 3272292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 3281061SN/A 3292292SN/A moveToReady(inst_entry); 3301061SN/A} 3311061SN/A 3321061SN/Atemplate <class MemDepPred, class Impl> 3331061SN/Avoid 3342292SN/AMemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst) 3351061SN/A{ 3362292SN/A instsToReplay.push_back(inst); 3372292SN/A} 3381061SN/A 3392292SN/Atemplate <class MemDepPred, class Impl> 3402292SN/Avoid 3412292SN/AMemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst) 3422292SN/A{ 3432292SN/A DynInstPtr temp_inst; 3442292SN/A bool found_inst = false; 3451062SN/A 3462348SN/A // For now this replay function replays all waiting memory ops. 3472292SN/A while (!instsToReplay.empty()) { 3482292SN/A temp_inst = instsToReplay.front(); 3491062SN/A 3502292SN/A MemDepEntryPtr inst_entry = findInHash(temp_inst); 3512292SN/A 3522292SN/A DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x " 3532292SN/A "[sn:%lli].\n", 3542292SN/A temp_inst->readPC(), temp_inst->seqNum); 3552292SN/A 3562292SN/A moveToReady(inst_entry); 3572292SN/A 3582292SN/A if (temp_inst == inst) { 3592292SN/A found_inst = true; 3602292SN/A } 3612292SN/A 3622292SN/A instsToReplay.pop_front(); 3632292SN/A } 3642292SN/A 3652292SN/A assert(found_inst); 3662292SN/A} 3672292SN/A 3682292SN/Atemplate <class MemDepPred, class Impl> 3692292SN/Avoid 3702292SN/AMemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst) 3712292SN/A{ 3722292SN/A DPRINTF(MemDepUnit, "Completed mem instruction PC %#x " 3732292SN/A "[sn:%lli].\n", 3742292SN/A inst->readPC(), inst->seqNum); 3752292SN/A 3762292SN/A unsigned tid = inst->threadNumber; 3772292SN/A 3782292SN/A // Remove the instruction from the hash and the list. 3792292SN/A MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 3802292SN/A 3812292SN/A assert(hash_it != memDepHash.end()); 3822292SN/A 3832292SN/A instList[tid].erase((*hash_it).second->listIt); 3842292SN/A 3852292SN/A (*hash_it).second = NULL; 3862292SN/A 3872292SN/A memDepHash.erase(hash_it); 3882678Sktlim@umich.edu#ifdef DEBUG 3892292SN/A MemDepEntry::memdep_erase++; 3902678Sktlim@umich.edu#endif 3912292SN/A} 3922292SN/A 3932292SN/Atemplate <class MemDepPred, class Impl> 3942292SN/Avoid 3952292SN/AMemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst) 3962292SN/A{ 3972292SN/A wakeDependents(inst); 3982292SN/A completed(inst); 3992292SN/A 4002292SN/A InstSeqNum barr_sn = inst->seqNum; 4012292SN/A 4022292SN/A if (inst->isMemBarrier()) { 4032292SN/A assert(loadBarrier && storeBarrier); 4042292SN/A if (loadBarrierSN == barr_sn) 4052292SN/A loadBarrier = false; 4062292SN/A if (storeBarrierSN == barr_sn) 4072292SN/A storeBarrier = false; 4082292SN/A } else if (inst->isWriteBarrier()) { 4092292SN/A assert(storeBarrier); 4102292SN/A if (storeBarrierSN == barr_sn) 4112292SN/A storeBarrier = false; 4122292SN/A } 4131061SN/A} 4141061SN/A 4151061SN/Atemplate <class MemDepPred, class Impl> 4161061SN/Avoid 4171061SN/AMemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 4181061SN/A{ 4192292SN/A // Only stores and barriers have dependents. 4202292SN/A if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) { 4211062SN/A return; 4221062SN/A } 4231062SN/A 4242292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 4251061SN/A 4262292SN/A for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) { 4272292SN/A MemDepEntryPtr woken_inst = inst_entry->dependInsts[i]; 4281062SN/A 4292292SN/A if (!woken_inst->inst) { 4302292SN/A // Potentially removed mem dep entries could be on this list 4312292SN/A continue; 4322292SN/A } 4331061SN/A 4342292SN/A DPRINTF(MemDepUnit, "Waking up a dependent inst, " 4352292SN/A "[sn:%lli].\n", 4362292SN/A woken_inst->inst->seqNum); 4371061SN/A 4382292SN/A if (woken_inst->regsReady && !woken_inst->squashed) { 4391062SN/A moveToReady(woken_inst); 4401062SN/A } else { 4412292SN/A woken_inst->memDepReady = true; 4421062SN/A } 4431061SN/A } 4441061SN/A 4452292SN/A inst_entry->dependInsts.clear(); 4461061SN/A} 4471061SN/A 4481061SN/Atemplate <class MemDepPred, class Impl> 4491061SN/Avoid 4502292SN/AMemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, 4512292SN/A unsigned tid) 4521061SN/A{ 4532292SN/A if (!instsToReplay.empty()) { 4542292SN/A ListIt replay_it = instsToReplay.begin(); 4552292SN/A while (replay_it != instsToReplay.end()) { 4562292SN/A if ((*replay_it)->threadNumber == tid && 4572292SN/A (*replay_it)->seqNum > squashed_num) { 4582292SN/A instsToReplay.erase(replay_it++); 4592292SN/A } else { 4602292SN/A ++replay_it; 4611062SN/A } 4621061SN/A } 4631061SN/A } 4641061SN/A 4652292SN/A ListIt squash_it = instList[tid].end(); 4662292SN/A --squash_it; 4671061SN/A 4682292SN/A MemDepHashIt hash_it; 4691061SN/A 4702292SN/A while (!instList[tid].empty() && 4712292SN/A (*squash_it)->seqNum > squashed_num) { 4721061SN/A 4732292SN/A DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n", 4742292SN/A (*squash_it)->seqNum); 4751061SN/A 4762292SN/A hash_it = memDepHash.find((*squash_it)->seqNum); 4771061SN/A 4782292SN/A assert(hash_it != memDepHash.end()); 4791062SN/A 4802292SN/A (*hash_it).second->squashed = true; 4811717SN/A 4822292SN/A (*hash_it).second = NULL; 4831717SN/A 4842292SN/A memDepHash.erase(hash_it); 4852678Sktlim@umich.edu#ifdef DEBUG 4862292SN/A MemDepEntry::memdep_erase++; 4872678Sktlim@umich.edu#endif 4881717SN/A 4892292SN/A instList[tid].erase(squash_it--); 4901061SN/A } 4911061SN/A 4921061SN/A // Tell the dependency predictor to squash as well. 4932292SN/A depPred.squash(squashed_num, tid); 4941061SN/A} 4951061SN/A 4961061SN/Atemplate <class MemDepPred, class Impl> 4971061SN/Avoid 4981061SN/AMemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 4991061SN/A DynInstPtr &violating_load) 5001061SN/A{ 5012292SN/A DPRINTF(MemDepUnit, "Passing violating PCs to store sets," 5021062SN/A " load: %#x, store: %#x\n", violating_load->readPC(), 5031062SN/A store_inst->readPC()); 5041061SN/A // Tell the memory dependence unit of the violation. 5051061SN/A depPred.violation(violating_load->readPC(), store_inst->readPC()); 5061061SN/A} 5071062SN/A 5081062SN/Atemplate <class MemDepPred, class Impl> 5092292SN/Avoid 5102292SN/AMemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 5112292SN/A{ 5122292SN/A DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", 5132292SN/A inst->readPC(), inst->seqNum); 5142292SN/A 5152292SN/A depPred.issued(inst->readPC(), inst->seqNum, inst->isStore()); 5162292SN/A} 5172292SN/A 5182292SN/Atemplate <class MemDepPred, class Impl> 5192292SN/Ainline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr & 5202292SN/AMemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst) 5212292SN/A{ 5222292SN/A MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 5232292SN/A 5242292SN/A assert(hash_it != memDepHash.end()); 5252292SN/A 5262292SN/A return (*hash_it).second; 5272292SN/A} 5282292SN/A 5292292SN/Atemplate <class MemDepPred, class Impl> 5301062SN/Ainline void 5312292SN/AMemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry) 5321062SN/A{ 5332292SN/A DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] " 5342292SN/A "to the ready list.\n", woken_inst_entry->inst->seqNum); 5351062SN/A 5362292SN/A assert(!woken_inst_entry->squashed); 5371062SN/A 5382292SN/A iqPtr->addReadyMemInst(woken_inst_entry->inst); 5391062SN/A} 5402292SN/A 5412292SN/A 5422292SN/Atemplate <class MemDepPred, class Impl> 5432292SN/Avoid 5442292SN/AMemDepUnit<MemDepPred, Impl>::dumpLists() 5452292SN/A{ 5462292SN/A for (unsigned tid=0; tid < Impl::MaxThreads; tid++) { 5472292SN/A cprintf("Instruction list %i size: %i\n", 5482292SN/A tid, instList[tid].size()); 5492292SN/A 5502292SN/A ListIt inst_list_it = instList[tid].begin(); 5512292SN/A int num = 0; 5522292SN/A 5532292SN/A while (inst_list_it != instList[tid].end()) { 5542292SN/A cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n" 5552292SN/A "Squashed:%i\n\n", 5562292SN/A num, (*inst_list_it)->readPC(), 5572292SN/A (*inst_list_it)->seqNum, 5582292SN/A (*inst_list_it)->threadNumber, 5592292SN/A (*inst_list_it)->isIssued(), 5602292SN/A (*inst_list_it)->isSquashed()); 5612292SN/A inst_list_it++; 5622292SN/A ++num; 5632292SN/A } 5642292SN/A } 5652292SN/A 5662292SN/A cprintf("Memory dependence hash size: %i\n", memDepHash.size()); 5672292SN/A 5682678Sktlim@umich.edu#ifdef DEBUG 5692292SN/A cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); 5702678Sktlim@umich.edu#endif 5712292SN/A} 572