mem_dep_unit_impl.hh revision 2348 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <map>
30
31#include "cpu/o3/inst_queue.hh"
32#include "cpu/o3/mem_dep_unit.hh"
33
34template <class MemDepPred, class Impl>
35MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
36    : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
37      loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
38{
39    DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
40}
41
42template <class MemDepPred, class Impl>
43MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
44{
45    for (int tid=0; tid < Impl::MaxThreads; tid++) {
46
47        ListIt inst_list_it = instList[tid].begin();
48
49        MemDepHashIt hash_it;
50
51        while (!instList[tid].empty()) {
52            hash_it = memDepHash.find((*inst_list_it)->seqNum);
53
54            assert(hash_it != memDepHash.end());
55
56            memDepHash.erase(hash_it);
57
58            instList[tid].erase(inst_list_it++);
59        }
60    }
61
62    assert(MemDepEntry::memdep_count == 0);
63}
64
65template <class MemDepPred, class Impl>
66std::string
67MemDepUnit<MemDepPred, Impl>::name() const
68{
69    return "memdepunit";
70}
71
72template <class MemDepPred, class Impl>
73void
74MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
75{
76    DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
77
78    id = tid;
79
80    depPred.init(params->SSITSize, params->LFSTSize);
81}
82
83template <class MemDepPred, class Impl>
84void
85MemDepUnit<MemDepPred, Impl>::regStats()
86{
87    insertedLoads
88        .name(name() + ".memDep.insertedLoads")
89        .desc("Number of loads inserted to the mem dependence unit.");
90
91    insertedStores
92        .name(name() + ".memDep.insertedStores")
93        .desc("Number of stores inserted to the mem dependence unit.");
94
95    conflictingLoads
96        .name(name() + ".memDep.conflictingLoads")
97        .desc("Number of conflicting loads.");
98
99    conflictingStores
100        .name(name() + ".memDep.conflictingStores")
101        .desc("Number of conflicting stores.");
102}
103
104template <class MemDepPred, class Impl>
105void
106MemDepUnit<MemDepPred, Impl>::switchOut()
107{
108    // Clear any state.
109    for (int i = 0; i < Impl::MaxThreads; ++i) {
110        instList[i].clear();
111    }
112    instsToReplay.clear();
113    memDepHash.clear();
114}
115
116template <class MemDepPred, class Impl>
117void
118MemDepUnit<MemDepPred, Impl>::takeOverFrom()
119{
120    // Be sure to reset all state.
121    loadBarrier = storeBarrier = false;
122    loadBarrierSN = storeBarrierSN = 0;
123    depPred.clear();
124}
125
126template <class MemDepPred, class Impl>
127void
128MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
129{
130    iqPtr = iq_ptr;
131}
132
133template <class MemDepPred, class Impl>
134void
135MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
136{
137    unsigned tid = inst->threadNumber;
138
139    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
140
141    // Add the MemDepEntry to the hash.
142    memDepHash.insert(
143        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
144    MemDepEntry::memdep_insert++;
145
146    instList[tid].push_back(inst);
147
148    inst_entry->listIt = --(instList[tid].end());
149
150    // Check any barriers and the dependence predictor for any
151    // producing memrefs/stores.
152    InstSeqNum producing_store;
153    if (inst->isLoad() && loadBarrier) {
154        producing_store = loadBarrierSN;
155    } else if (inst->isStore() && storeBarrier) {
156        producing_store = storeBarrierSN;
157    } else {
158        producing_store = depPred.checkInst(inst->readPC());
159    }
160
161    MemDepEntryPtr store_entry = NULL;
162
163    // If there is a producing store, try to find the entry.
164    if (producing_store != 0) {
165        MemDepHashIt hash_it = memDepHash.find(producing_store);
166
167        if (hash_it != memDepHash.end()) {
168            store_entry = (*hash_it).second;
169        }
170    }
171
172    // If no store entry, then instruction can issue as soon as the registers
173    // are ready.
174    if (!store_entry) {
175        DPRINTF(MemDepUnit, "No dependency for inst PC "
176                "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
177
178        inst_entry->memDepReady = true;
179
180        if (inst->readyToIssue()) {
181            inst_entry->regsReady = true;
182
183            moveToReady(inst_entry);
184        }
185    } else {
186        // Otherwise make the instruction dependent on the store/barrier.
187        DPRINTF(MemDepUnit, "Adding to dependency list; "
188                "inst PC %#x is dependent on [sn:%lli].\n",
189                inst->readPC(), producing_store);
190
191        if (inst->readyToIssue()) {
192            inst_entry->regsReady = true;
193        }
194
195        // Add this instruction to the list of dependents.
196        store_entry->dependInsts.push_back(inst_entry);
197
198        if (inst->isLoad()) {
199            ++conflictingLoads;
200        } else {
201            ++conflictingStores;
202        }
203    }
204
205    if (inst->isStore()) {
206        DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
207                inst->readPC(), inst->seqNum);
208
209        depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
210
211        ++insertedStores;
212    } else if (inst->isLoad()) {
213        ++insertedLoads;
214    } else {
215        panic("Unknown type! (most likely a barrier).");
216    }
217}
218
219template <class MemDepPred, class Impl>
220void
221MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
222{
223    unsigned tid = inst->threadNumber;
224
225    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
226
227    // Insert the MemDepEntry into the hash.
228    memDepHash.insert(
229        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
230    MemDepEntry::memdep_insert++;
231
232    // Add the instruction to the list.
233    instList[tid].push_back(inst);
234
235    inst_entry->listIt = --(instList[tid].end());
236
237    // Might want to turn this part into an inline function or something.
238    // It's shared between both insert functions.
239    if (inst->isStore()) {
240        DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
241                inst->readPC(), inst->seqNum);
242
243        depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
244
245        ++insertedStores;
246    } else if (inst->isLoad()) {
247        ++insertedLoads;
248    } else {
249        panic("Unknown type! (most likely a barrier).");
250    }
251}
252
253template <class MemDepPred, class Impl>
254void
255MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
256{
257    InstSeqNum barr_sn = barr_inst->seqNum;
258    // Memory barriers block loads and stores, write barriers only stores.
259    if (barr_inst->isMemBarrier()) {
260        loadBarrier = true;
261        loadBarrierSN = barr_sn;
262        storeBarrier = true;
263        storeBarrierSN = barr_sn;
264        DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
265    } else if (barr_inst->isWriteBarrier()) {
266        storeBarrier = true;
267        storeBarrierSN = barr_sn;
268        DPRINTF(MemDepUnit, "Inserted a write barrier\n");
269    }
270
271    unsigned tid = barr_inst->threadNumber;
272
273    MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
274
275    // Add the MemDepEntry to the hash.
276    memDepHash.insert(
277        std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
278    MemDepEntry::memdep_insert++;
279
280    // Add the instruction to the instruction list.
281    instList[tid].push_back(barr_inst);
282
283    inst_entry->listIt = --(instList[tid].end());
284}
285
286template <class MemDepPred, class Impl>
287void
288MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
289{
290    DPRINTF(MemDepUnit, "Marking registers as ready for "
291            "instruction PC %#x [sn:%lli].\n",
292            inst->readPC(), inst->seqNum);
293
294    MemDepEntryPtr inst_entry = findInHash(inst);
295
296    inst_entry->regsReady = true;
297
298    if (inst_entry->memDepReady) {
299        DPRINTF(MemDepUnit, "Instruction has its memory "
300                "dependencies resolved, adding it to the ready list.\n");
301
302        moveToReady(inst_entry);
303    } else {
304        DPRINTF(MemDepUnit, "Instruction still waiting on "
305                "memory dependency.\n");
306    }
307}
308
309template <class MemDepPred, class Impl>
310void
311MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
312{
313    DPRINTF(MemDepUnit, "Marking non speculative "
314            "instruction PC %#x as ready [sn:%lli].\n",
315            inst->readPC(), inst->seqNum);
316
317    MemDepEntryPtr inst_entry = findInHash(inst);
318
319    moveToReady(inst_entry);
320}
321
322template <class MemDepPred, class Impl>
323void
324MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
325{
326    instsToReplay.push_back(inst);
327}
328
329template <class MemDepPred, class Impl>
330void
331MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
332{
333    DynInstPtr temp_inst;
334    bool found_inst = false;
335
336    // For now this replay function replays all waiting memory ops.
337    while (!instsToReplay.empty()) {
338        temp_inst = instsToReplay.front();
339
340        MemDepEntryPtr inst_entry = findInHash(temp_inst);
341
342        DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
343                "[sn:%lli].\n",
344                temp_inst->readPC(), temp_inst->seqNum);
345
346        moveToReady(inst_entry);
347
348        if (temp_inst == inst) {
349            found_inst = true;
350        }
351
352        instsToReplay.pop_front();
353    }
354
355    assert(found_inst);
356}
357
358template <class MemDepPred, class Impl>
359void
360MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
361{
362    DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
363            "[sn:%lli].\n",
364            inst->readPC(), inst->seqNum);
365
366    unsigned tid = inst->threadNumber;
367
368    // Remove the instruction from the hash and the list.
369    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
370
371    assert(hash_it != memDepHash.end());
372
373    instList[tid].erase((*hash_it).second->listIt);
374
375    (*hash_it).second = NULL;
376
377    memDepHash.erase(hash_it);
378    MemDepEntry::memdep_erase++;
379}
380
381template <class MemDepPred, class Impl>
382void
383MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
384{
385    wakeDependents(inst);
386    completed(inst);
387
388    InstSeqNum barr_sn = inst->seqNum;
389
390    if (inst->isMemBarrier()) {
391        assert(loadBarrier && storeBarrier);
392        if (loadBarrierSN == barr_sn)
393            loadBarrier = false;
394        if (storeBarrierSN == barr_sn)
395            storeBarrier = false;
396    } else if (inst->isWriteBarrier()) {
397        assert(storeBarrier);
398        if (storeBarrierSN == barr_sn)
399            storeBarrier = false;
400    }
401}
402
403template <class MemDepPred, class Impl>
404void
405MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
406{
407    // Only stores and barriers have dependents.
408    if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
409        return;
410    }
411
412    MemDepEntryPtr inst_entry = findInHash(inst);
413
414    for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
415        MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
416
417        if (!woken_inst->inst) {
418            // Potentially removed mem dep entries could be on this list
419            continue;
420        }
421
422        DPRINTF(MemDepUnit, "Waking up a dependent inst, "
423                "[sn:%lli].\n",
424                woken_inst->inst->seqNum);
425
426        if (woken_inst->regsReady && !woken_inst->squashed) {
427            moveToReady(woken_inst);
428        } else {
429            woken_inst->memDepReady = true;
430        }
431    }
432
433    inst_entry->dependInsts.clear();
434}
435
436template <class MemDepPred, class Impl>
437void
438MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
439                                     unsigned tid)
440{
441    if (!instsToReplay.empty()) {
442        ListIt replay_it = instsToReplay.begin();
443        while (replay_it != instsToReplay.end()) {
444            if ((*replay_it)->threadNumber == tid &&
445                (*replay_it)->seqNum > squashed_num) {
446                instsToReplay.erase(replay_it++);
447            } else {
448                ++replay_it;
449            }
450        }
451    }
452
453    ListIt squash_it = instList[tid].end();
454    --squash_it;
455
456    MemDepHashIt hash_it;
457
458    while (!instList[tid].empty() &&
459           (*squash_it)->seqNum > squashed_num) {
460
461        DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
462                (*squash_it)->seqNum);
463
464        hash_it = memDepHash.find((*squash_it)->seqNum);
465
466        assert(hash_it != memDepHash.end());
467
468        (*hash_it).second->squashed = true;
469
470        (*hash_it).second = NULL;
471
472        memDepHash.erase(hash_it);
473        MemDepEntry::memdep_erase++;
474
475        instList[tid].erase(squash_it--);
476    }
477
478    // Tell the dependency predictor to squash as well.
479    depPred.squash(squashed_num, tid);
480}
481
482template <class MemDepPred, class Impl>
483void
484MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
485                                        DynInstPtr &violating_load)
486{
487    DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
488            " load: %#x, store: %#x\n", violating_load->readPC(),
489            store_inst->readPC());
490    // Tell the memory dependence unit of the violation.
491    depPred.violation(violating_load->readPC(), store_inst->readPC());
492}
493
494template <class MemDepPred, class Impl>
495void
496MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
497{
498    DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
499            inst->readPC(), inst->seqNum);
500
501    depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
502}
503
504template <class MemDepPred, class Impl>
505inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
506MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
507{
508    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
509
510    assert(hash_it != memDepHash.end());
511
512    return (*hash_it).second;
513}
514
515template <class MemDepPred, class Impl>
516inline void
517MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
518{
519    DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
520            "to the ready list.\n", woken_inst_entry->inst->seqNum);
521
522    assert(!woken_inst_entry->squashed);
523
524    iqPtr->addReadyMemInst(woken_inst_entry->inst);
525}
526
527
528template <class MemDepPred, class Impl>
529void
530MemDepUnit<MemDepPred, Impl>::dumpLists()
531{
532    for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
533        cprintf("Instruction list %i size: %i\n",
534                tid, instList[tid].size());
535
536        ListIt inst_list_it = instList[tid].begin();
537        int num = 0;
538
539        while (inst_list_it != instList[tid].end()) {
540            cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
541                    "Squashed:%i\n\n",
542                    num, (*inst_list_it)->readPC(),
543                    (*inst_list_it)->seqNum,
544                    (*inst_list_it)->threadNumber,
545                    (*inst_list_it)->isIssued(),
546                    (*inst_list_it)->isSquashed());
547            inst_list_it++;
548            ++num;
549        }
550    }
551
552    cprintf("Memory dependence hash size: %i\n", memDepHash.size());
553
554    cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
555}
556