mem_dep_unit_impl.hh revision 2292 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <map>
30
31#include "cpu/o3/inst_queue.hh"
32#include "cpu/o3/mem_dep_unit.hh"
33
34template <class MemDepPred, class Impl>
35MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
36    : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
37      loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
38{
39    DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
40}
41
42template <class MemDepPred, class Impl>
43MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
44{
45    for (int tid=0; tid < Impl::MaxThreads; tid++) {
46
47        ListIt inst_list_it = instList[tid].begin();
48
49        MemDepHashIt hash_it;
50
51        while (!instList[tid].empty()) {
52            hash_it = memDepHash.find((*inst_list_it)->seqNum);
53
54            assert(hash_it != memDepHash.end());
55
56            memDepHash.erase(hash_it);
57
58            instList[tid].erase(inst_list_it++);
59        }
60    }
61
62    assert(MemDepEntry::memdep_count == 0);
63}
64
65template <class MemDepPred, class Impl>
66std::string
67MemDepUnit<MemDepPred, Impl>::name() const
68{
69    return "memdepunit";
70}
71
72template <class MemDepPred, class Impl>
73void
74MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
75{
76    DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
77
78    id = tid;
79
80    depPred.init(params->SSITSize, params->LFSTSize);
81}
82
83template <class MemDepPred, class Impl>
84void
85MemDepUnit<MemDepPred, Impl>::regStats()
86{
87    insertedLoads
88        .name(name() + ".memDep.insertedLoads")
89        .desc("Number of loads inserted to the mem dependence unit.");
90
91    insertedStores
92        .name(name() + ".memDep.insertedStores")
93        .desc("Number of stores inserted to the mem dependence unit.");
94
95    conflictingLoads
96        .name(name() + ".memDep.conflictingLoads")
97        .desc("Number of conflicting loads.");
98
99    conflictingStores
100        .name(name() + ".memDep.conflictingStores")
101        .desc("Number of conflicting stores.");
102}
103
104template <class MemDepPred, class Impl>
105void
106MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
107{
108    iqPtr = iq_ptr;
109}
110
111template <class MemDepPred, class Impl>
112void
113MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
114{
115    unsigned tid = inst->threadNumber;
116
117    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
118
119    // Add the MemDepEntry to the hash.
120    memDepHash.insert(
121        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
122    MemDepEntry::memdep_insert++;
123
124    // Add the instruction to the instruction list.
125    instList[tid].push_back(inst);
126
127    inst_entry->listIt = --(instList[tid].end());
128
129    // Check the dependence predictor for any producing stores.
130    InstSeqNum producing_store;
131    if (inst->isLoad() && loadBarrier) {
132        producing_store = loadBarrierSN;
133    } else if (inst->isStore() && storeBarrier) {
134        producing_store = storeBarrierSN;
135    } else {
136        producing_store = depPred.checkInst(inst->readPC());
137    }
138
139    MemDepEntryPtr store_entry = NULL;
140
141    // If there is a producing store, try to find the entry.
142    if (producing_store != 0) {
143        MemDepHashIt hash_it = memDepHash.find(producing_store);
144
145        if (hash_it != memDepHash.end()) {
146            store_entry = (*hash_it).second;
147        }
148    }
149
150    // If no store entry, then instruction can issue as soon as the registers
151    // are ready.
152    if (!store_entry) {
153        DPRINTF(MemDepUnit, "No dependency for inst PC "
154                "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
155
156        inst_entry->memDepReady = true;
157
158        if (inst->readyToIssue()) {
159            inst_entry->regsReady = true;
160
161            moveToReady(inst_entry);
162        }
163    } else {
164        // Otherwise make the instruction dependent on the store.
165        DPRINTF(MemDepUnit, "Adding to dependency list; "
166                "inst PC %#x is dependent on [sn:%lli].\n",
167                inst->readPC(), producing_store);
168
169        if (inst->readyToIssue()) {
170            inst_entry->regsReady = true;
171        }
172
173        // Add this instruction to the list of dependents.
174        store_entry->dependInsts.push_back(inst_entry);
175
176//        inst_entry->producingStore = store_entry;
177
178        if (inst->isLoad()) {
179            ++conflictingLoads;
180        } else {
181            ++conflictingStores;
182        }
183    }
184
185    if (inst->isStore()) {
186        DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
187                inst->readPC(), inst->seqNum);
188
189        depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
190
191        ++insertedStores;
192    } else if (inst->isLoad()) {
193        ++insertedLoads;
194    } else {
195        panic("Unknown type! (most likely a barrier).");
196    }
197}
198
199template <class MemDepPred, class Impl>
200void
201MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
202{
203    unsigned tid = inst->threadNumber;
204
205    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
206
207    // Insert the MemDepEntry into the hash.
208    memDepHash.insert(
209        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
210    MemDepEntry::memdep_insert++;
211
212    // Add the instruction to the list.
213    instList[tid].push_back(inst);
214
215    inst_entry->listIt = --(instList[tid].end());
216
217    // Might want to turn this part into an inline function or something.
218    // It's shared between both insert functions.
219    if (inst->isStore()) {
220        DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
221                inst->readPC(), inst->seqNum);
222
223        depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
224
225        ++insertedStores;
226    } else if (inst->isLoad()) {
227        ++insertedLoads;
228    } else {
229        panic("Unknown type! (most likely a barrier).");
230    }
231}
232
233template <class MemDepPred, class Impl>
234void
235MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
236{
237    InstSeqNum barr_sn = barr_inst->seqNum;
238    if (barr_inst->isMemBarrier()) {
239        loadBarrier = true;
240        loadBarrierSN = barr_sn;
241        storeBarrier = true;
242        storeBarrierSN = barr_sn;
243        DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
244    } else if (barr_inst->isWriteBarrier()) {
245        storeBarrier = true;
246        storeBarrierSN = barr_sn;
247        DPRINTF(MemDepUnit, "Inserted a write barrier\n");
248    }
249
250    unsigned tid = barr_inst->threadNumber;
251
252    MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
253
254    // Add the MemDepEntry to the hash.
255    memDepHash.insert(
256        std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
257    MemDepEntry::memdep_insert++;
258
259    // Add the instruction to the instruction list.
260    instList[tid].push_back(barr_inst);
261
262    inst_entry->listIt = --(instList[tid].end());
263}
264
265template <class MemDepPred, class Impl>
266void
267MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
268{
269    DPRINTF(MemDepUnit, "Marking registers as ready for "
270            "instruction PC %#x [sn:%lli].\n",
271            inst->readPC(), inst->seqNum);
272
273    MemDepEntryPtr inst_entry = findInHash(inst);
274
275    inst_entry->regsReady = true;
276
277    if (inst_entry->memDepReady) {
278        DPRINTF(MemDepUnit, "Instruction has its memory "
279                "dependencies resolved, adding it to the ready list.\n");
280
281        moveToReady(inst_entry);
282    } else {
283        DPRINTF(MemDepUnit, "Instruction still waiting on "
284                "memory dependency.\n");
285    }
286}
287
288template <class MemDepPred, class Impl>
289void
290MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
291{
292    DPRINTF(MemDepUnit, "Marking non speculative "
293            "instruction PC %#x as ready [sn:%lli].\n",
294            inst->readPC(), inst->seqNum);
295
296    MemDepEntryPtr inst_entry = findInHash(inst);
297
298    moveToReady(inst_entry);
299}
300
301template <class MemDepPred, class Impl>
302void
303MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
304{
305    instsToReplay.push_back(inst);
306}
307
308template <class MemDepPred, class Impl>
309void
310MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
311{
312    DynInstPtr temp_inst;
313    bool found_inst = false;
314
315    while (!instsToReplay.empty()) {
316        temp_inst = instsToReplay.front();
317
318        MemDepEntryPtr inst_entry = findInHash(temp_inst);
319
320        DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
321                "[sn:%lli].\n",
322                temp_inst->readPC(), temp_inst->seqNum);
323
324        moveToReady(inst_entry);
325
326        if (temp_inst == inst) {
327            found_inst = true;
328        }
329
330        instsToReplay.pop_front();
331    }
332
333    assert(found_inst);
334}
335
336template <class MemDepPred, class Impl>
337void
338MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
339{
340    DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
341            "[sn:%lli].\n",
342            inst->readPC(), inst->seqNum);
343
344    unsigned tid = inst->threadNumber;
345
346    // Remove the instruction from the hash and the list.
347    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
348
349    assert(hash_it != memDepHash.end());
350
351    instList[tid].erase((*hash_it).second->listIt);
352
353//    (*hash_it).second->inst = NULL;
354
355    (*hash_it).second = NULL;
356
357    memDepHash.erase(hash_it);
358    MemDepEntry::memdep_erase++;
359}
360
361template <class MemDepPred, class Impl>
362void
363MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
364{
365    wakeDependents(inst);
366    completed(inst);
367
368    InstSeqNum barr_sn = inst->seqNum;
369
370    if (inst->isMemBarrier()) {
371        assert(loadBarrier && storeBarrier);
372        if (loadBarrierSN == barr_sn)
373            loadBarrier = false;
374        if (storeBarrierSN == barr_sn)
375            storeBarrier = false;
376    } else if (inst->isWriteBarrier()) {
377        assert(storeBarrier);
378        if (storeBarrierSN == barr_sn)
379            storeBarrier = false;
380    }
381}
382
383template <class MemDepPred, class Impl>
384void
385MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
386{
387    // Only stores and barriers have dependents.
388    if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
389        return;
390    }
391
392    MemDepEntryPtr inst_entry = findInHash(inst);
393
394    for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
395        MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
396
397        if (!woken_inst->inst) {
398            // Potentially removed mem dep entries could be on this list
399//            inst_entry->dependInsts[i] = NULL;
400            continue;
401        }
402
403        DPRINTF(MemDepUnit, "Waking up a dependent inst, "
404                "[sn:%lli].\n",
405                woken_inst->inst->seqNum);
406
407        if (woken_inst->regsReady && !woken_inst->squashed) {
408            moveToReady(woken_inst);
409        } else {
410            woken_inst->memDepReady = true;
411        }
412//        inst_entry->dependInsts[i] = NULL;
413    }
414
415    inst_entry->dependInsts.clear();
416}
417
418template <class MemDepPred, class Impl>
419void
420MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
421                                     unsigned tid)
422{
423    if (!instsToReplay.empty()) {
424        ListIt replay_it = instsToReplay.begin();
425        while (replay_it != instsToReplay.end()) {
426            if ((*replay_it)->threadNumber == tid &&
427                (*replay_it)->seqNum > squashed_num) {
428                instsToReplay.erase(replay_it++);
429            } else {
430                ++replay_it;
431            }
432        }
433    }
434
435    ListIt squash_it = instList[tid].end();
436    --squash_it;
437
438    MemDepHashIt hash_it;
439
440    while (!instList[tid].empty() &&
441           (*squash_it)->seqNum > squashed_num) {
442
443        DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
444                (*squash_it)->seqNum);
445
446        hash_it = memDepHash.find((*squash_it)->seqNum);
447
448        assert(hash_it != memDepHash.end());
449
450        (*hash_it).second->squashed = true;
451/*
452        for (int i = 0; i < (*hash_it).second->dependInsts.size(); ++i) {
453            (*hash_it).second->dependInsts[i] = NULL;
454        }
455
456        (*hash_it).second->inst = NULL;
457*/
458        (*hash_it).second = NULL;
459
460        memDepHash.erase(hash_it);
461        MemDepEntry::memdep_erase++;
462
463        instList[tid].erase(squash_it--);
464    }
465
466    // Tell the dependency predictor to squash as well.
467    depPred.squash(squashed_num, tid);
468}
469
470template <class MemDepPred, class Impl>
471void
472MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
473                                        DynInstPtr &violating_load)
474{
475    DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
476            " load: %#x, store: %#x\n", violating_load->readPC(),
477            store_inst->readPC());
478    // Tell the memory dependence unit of the violation.
479    depPred.violation(violating_load->readPC(), store_inst->readPC());
480}
481
482template <class MemDepPred, class Impl>
483void
484MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
485{
486    DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
487            inst->readPC(), inst->seqNum);
488
489    depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
490}
491
492template <class MemDepPred, class Impl>
493inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
494MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
495{
496    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
497
498    assert(hash_it != memDepHash.end());
499
500    return (*hash_it).second;
501}
502
503template <class MemDepPred, class Impl>
504inline void
505MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
506{
507    DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
508            "to the ready list.\n", woken_inst_entry->inst->seqNum);
509
510    assert(!woken_inst_entry->squashed);
511
512    iqPtr->addReadyMemInst(woken_inst_entry->inst);
513}
514
515
516template <class MemDepPred, class Impl>
517void
518MemDepUnit<MemDepPred, Impl>::dumpLists()
519{
520    for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
521        cprintf("Instruction list %i size: %i\n",
522                tid, instList[tid].size());
523
524        ListIt inst_list_it = instList[tid].begin();
525        int num = 0;
526
527        while (inst_list_it != instList[tid].end()) {
528            cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
529                    "Squashed:%i\n\n",
530                    num, (*inst_list_it)->readPC(),
531                    (*inst_list_it)->seqNum,
532                    (*inst_list_it)->threadNumber,
533                    (*inst_list_it)->isIssued(),
534                    (*inst_list_it)->isSquashed());
535            inst_list_it++;
536            ++num;
537        }
538    }
539
540    cprintf("Memory dependence hash size: %i\n", memDepHash.size());
541
542    cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
543}
544