mem_dep_unit_impl.hh revision 1717
16657Snate@binkert.org/* 26657Snate@binkert.org * Copyright (c) 2004-2005 The Regents of The University of Michigan 36657Snate@binkert.org * All rights reserved. 46657Snate@binkert.org * 56657Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66657Snate@binkert.org * modification, are permitted provided that the following conditions are 76657Snate@binkert.org * met: redistributions of source code must retain the above copyright 86657Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96657Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106657Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116657Snate@binkert.org * documentation and/or other materials provided with the distribution; 126657Snate@binkert.org * neither the name of the copyright holders nor the names of its 136657Snate@binkert.org * contributors may be used to endorse or promote products derived from 146657Snate@binkert.org * this software without specific prior written permission. 156657Snate@binkert.org * 166657Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176657Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186657Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196657Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206657Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216657Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226657Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236657Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246657Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256657Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266657Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276657Snate@binkert.org */ 286999Snate@binkert.org 296657Snate@binkert.org#include <map> 306657Snate@binkert.org 316657Snate@binkert.org#include "cpu/o3/mem_dep_unit.hh" 326657Snate@binkert.org 338189SLisa.Hsu@amd.comtemplate <class MemDepPred, class Impl> 346657Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::MemDepUnit(Params ¶ms) 356882SBrad.Beckmann@amd.com : depPred(params.SSITSize, params.LFSTSize) 367055Snate@binkert.org{ 376882SBrad.Beckmann@amd.com DPRINTF(MemDepUnit, "MemDepUnit: Creating MemDepUnit object.\n"); 386882SBrad.Beckmann@amd.com} 398191SLisa.Hsu@amd.com 406882SBrad.Beckmann@amd.comtemplate <class MemDepPred, class Impl> 416882SBrad.Beckmann@amd.comvoid 426882SBrad.Beckmann@amd.comMemDepUnit<MemDepPred, Impl>::regStats() 436888SBrad.Beckmann@amd.com{ 446882SBrad.Beckmann@amd.com insertedLoads 456882SBrad.Beckmann@amd.com .name(name() + ".memDep.insertedLoads") 466657Snate@binkert.org .desc("Number of loads inserted to the mem dependence unit."); 476657Snate@binkert.org 486657Snate@binkert.org insertedStores 496657Snate@binkert.org .name(name() + ".memDep.insertedStores") 506657Snate@binkert.org .desc("Number of stores inserted to the mem dependence unit."); 517839Snilay@cs.wisc.edu 526657Snate@binkert.org conflictingLoads 536882SBrad.Beckmann@amd.com .name(name() + ".memDep.conflictingLoads") 546882SBrad.Beckmann@amd.com .desc("Number of conflicting loads."); 556882SBrad.Beckmann@amd.com 566882SBrad.Beckmann@amd.com conflictingStores 576882SBrad.Beckmann@amd.com .name(name() + ".memDep.conflictingStores") 586882SBrad.Beckmann@amd.com .desc("Number of conflicting stores."); 596657Snate@binkert.org} 606657Snate@binkert.org 616657Snate@binkert.orgtemplate <class MemDepPred, class Impl> 626657Snate@binkert.orgvoid 636657Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 646657Snate@binkert.org{ 656657Snate@binkert.org InstSeqNum inst_seq_num = inst->seqNum; 666657Snate@binkert.org 676657Snate@binkert.org Dependency unresolved_dependencies(inst_seq_num); 687839Snilay@cs.wisc.edu 697839Snilay@cs.wisc.edu InstSeqNum producing_store = depPred.checkInst(inst->readPC()); 706657Snate@binkert.org 716657Snate@binkert.org if (producing_store == 0 || 726657Snate@binkert.org storeDependents.find(producing_store) == storeDependents.end()) { 736657Snate@binkert.org 746657Snate@binkert.org DPRINTF(MemDepUnit, "MemDepUnit: No dependency for inst PC " 756657Snate@binkert.org "%#x.\n", inst->readPC()); 766657Snate@binkert.org 776657Snate@binkert.org unresolved_dependencies.storeDep = storeDependents.end(); 786657Snate@binkert.org 796657Snate@binkert.org if (inst->readyToIssue()) { 806657Snate@binkert.org readyInsts.insert(inst_seq_num); 816657Snate@binkert.org } else { 826657Snate@binkert.org unresolved_dependencies.memDepReady = true; 836657Snate@binkert.org 846657Snate@binkert.org waitingInsts.insert(unresolved_dependencies); 856657Snate@binkert.org } 866657Snate@binkert.org } else { 876657Snate@binkert.org DPRINTF(MemDepUnit, "MemDepUnit: Adding to dependency list; " 886657Snate@binkert.org "inst PC %#x is dependent on seq num %i.\n", 896657Snate@binkert.org inst->readPC(), producing_store); 906779SBrad.Beckmann@amd.com 916657Snate@binkert.org if (inst->readyToIssue()) { 926657Snate@binkert.org unresolved_dependencies.regsReady = true; 936657Snate@binkert.org } 946657Snate@binkert.org 956657Snate@binkert.org // Find the store that this instruction is dependent on. 966657Snate@binkert.org sd_it_t store_loc = storeDependents.find(producing_store); 976657Snate@binkert.org 986657Snate@binkert.org assert(store_loc != storeDependents.end()); 996657Snate@binkert.org 1006657Snate@binkert.org // Record the location of the store that this instruction is 1016657Snate@binkert.org // dependent on. 1026657Snate@binkert.org unresolved_dependencies.storeDep = store_loc; 1036657Snate@binkert.org 1046657Snate@binkert.org // If it's not already ready, then add it to the renamed 1056657Snate@binkert.org // list and the dependencies. 1066657Snate@binkert.org dep_it_t inst_loc = 1076657Snate@binkert.org (waitingInsts.insert(unresolved_dependencies)).first; 1086657Snate@binkert.org 1096657Snate@binkert.org // Add this instruction to the list of dependents. 1106657Snate@binkert.org (*store_loc).second.push_back(inst_loc); 1116657Snate@binkert.org 1126657Snate@binkert.org assert(!(*store_loc).second.empty()); 1136657Snate@binkert.org 1146657Snate@binkert.org if (inst->isLoad()) { 1157839Snilay@cs.wisc.edu ++conflictingLoads; 1167839Snilay@cs.wisc.edu } else { 1177839Snilay@cs.wisc.edu ++conflictingStores; 1187839Snilay@cs.wisc.edu } 1197839Snilay@cs.wisc.edu } 1207839Snilay@cs.wisc.edu 1217839Snilay@cs.wisc.edu if (inst->isStore()) { 1227839Snilay@cs.wisc.edu DPRINTF(MemDepUnit, "MemDepUnit: Inserting store PC %#x.\n", 1237839Snilay@cs.wisc.edu inst->readPC()); 1247839Snilay@cs.wisc.edu 1257839Snilay@cs.wisc.edu depPred.insertStore(inst->readPC(), inst_seq_num); 1267839Snilay@cs.wisc.edu 1277839Snilay@cs.wisc.edu // Make sure this store isn't already in this list. 1287839Snilay@cs.wisc.edu assert(storeDependents.find(inst_seq_num) == storeDependents.end()); 1297839Snilay@cs.wisc.edu 1306657Snate@binkert.org // Put a dependency entry in at the store's sequence number. 1316657Snate@binkert.org // Uh, not sure how this works...I want to create an entry but 1326657Snate@binkert.org // I don't have anything to put into the value yet. 1336657Snate@binkert.org storeDependents[inst_seq_num]; 1346657Snate@binkert.org 1356657Snate@binkert.org assert(storeDependents.size() != 0); 1366657Snate@binkert.org 1376657Snate@binkert.org ++insertedStores; 1386657Snate@binkert.org 1396657Snate@binkert.org } else if (inst->isLoad()) { 1406657Snate@binkert.org ++insertedLoads; 1416657Snate@binkert.org } else { 1426657Snate@binkert.org panic("MemDepUnit: Unknown type! (most likely a barrier)."); 1436657Snate@binkert.org } 1446657Snate@binkert.org 1456657Snate@binkert.org memInsts[inst_seq_num] = inst; 1466657Snate@binkert.org} 1476657Snate@binkert.org 1486657Snate@binkert.orgtemplate <class MemDepPred, class Impl> 1496657Snate@binkert.orgvoid 1506657Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 1516657Snate@binkert.org{ 1526657Snate@binkert.org InstSeqNum inst_seq_num = inst->seqNum; 1536657Snate@binkert.org 1546657Snate@binkert.org Dependency non_spec_inst(inst_seq_num); 1556657Snate@binkert.org 1566657Snate@binkert.org non_spec_inst.storeDep = storeDependents.end(); 1576657Snate@binkert.org 1586657Snate@binkert.org waitingInsts.insert(non_spec_inst); 1596657Snate@binkert.org 1606657Snate@binkert.org // Might want to turn this part into an inline function or something. 1616877Ssteve.reinhardt@amd.com // It's shared between both insert functions. 1626657Snate@binkert.org if (inst->isStore()) { 1636657Snate@binkert.org DPRINTF(MemDepUnit, "MemDepUnit: Inserting store PC %#x.\n", 1646657Snate@binkert.org inst->readPC()); 1656657Snate@binkert.org 1666657Snate@binkert.org depPred.insertStore(inst->readPC(), inst_seq_num); 1676657Snate@binkert.org 1687542SBrad.Beckmann@amd.com // Make sure this store isn't already in this list. 1697542SBrad.Beckmann@amd.com assert(storeDependents.find(inst_seq_num) == storeDependents.end()); 1706657Snate@binkert.org 1716657Snate@binkert.org // Put a dependency entry in at the store's sequence number. 1726657Snate@binkert.org // Uh, not sure how this works...I want to create an entry but 1736657Snate@binkert.org // I don't have anything to put into the value yet. 1746877Ssteve.reinhardt@amd.com storeDependents[inst_seq_num]; 1756999Snate@binkert.org 1766877Ssteve.reinhardt@amd.com assert(storeDependents.size() != 0); 1776877Ssteve.reinhardt@amd.com 1786877Ssteve.reinhardt@amd.com ++insertedStores; 1796877Ssteve.reinhardt@amd.com 1806877Ssteve.reinhardt@amd.com } else if (inst->isLoad()) { 1816877Ssteve.reinhardt@amd.com ++insertedLoads; 1826877Ssteve.reinhardt@amd.com } else { 1836877Ssteve.reinhardt@amd.com panic("MemDepUnit: Unknown type! (most likely a barrier)."); 1846877Ssteve.reinhardt@amd.com } 1856877Ssteve.reinhardt@amd.com 1866877Ssteve.reinhardt@amd.com memInsts[inst_seq_num] = inst; 1876877Ssteve.reinhardt@amd.com} 1886877Ssteve.reinhardt@amd.com 1896877Ssteve.reinhardt@amd.comtemplate <class MemDepPred, class Impl> 1906877Ssteve.reinhardt@amd.comtypename Impl::DynInstPtr & 1916877Ssteve.reinhardt@amd.comMemDepUnit<MemDepPred, Impl>::top() 1926882SBrad.Beckmann@amd.com{ 1936882SBrad.Beckmann@amd.com topInst = memInsts.find( (*readyInsts.begin()) ); 1946882SBrad.Beckmann@amd.com 1956882SBrad.Beckmann@amd.com DPRINTF(MemDepUnit, "MemDepUnit: Top instruction is PC %#x.\n", 1966882SBrad.Beckmann@amd.com (*topInst).second->readPC()); 1976882SBrad.Beckmann@amd.com 1986882SBrad.Beckmann@amd.com return (*topInst).second; 1996877Ssteve.reinhardt@amd.com} 2006877Ssteve.reinhardt@amd.com 2016877Ssteve.reinhardt@amd.comtemplate <class MemDepPred, class Impl> 2026877Ssteve.reinhardt@amd.comvoid 2036657Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::pop() 2046657Snate@binkert.org{ 2056999Snate@binkert.org DPRINTF(MemDepUnit, "MemDepUnit: Removing instruction PC %#x.\n", 2066657Snate@binkert.org (*topInst).second->readPC()); 2076657Snate@binkert.org 2086657Snate@binkert.org wakeDependents((*topInst).second); 2096657Snate@binkert.org 2106657Snate@binkert.org issue((*topInst).second); 2116657Snate@binkert.org 2127007Snate@binkert.org memInsts.erase(topInst); 2136657Snate@binkert.org 2146657Snate@binkert.org topInst = memInsts.end(); 2156657Snate@binkert.org} 2166657Snate@binkert.org 2176657Snate@binkert.orgtemplate <class MemDepPred, class Impl> 2187007Snate@binkert.orgvoid 2197007Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) 2206657Snate@binkert.org{ 2217002Snate@binkert.org DPRINTF(MemDepUnit, "MemDepUnit: Marking registers as ready for " 2227002Snate@binkert.org "instruction PC %#x.\n", 2237002Snate@binkert.org inst->readPC()); 2247002Snate@binkert.org 2258229Snate@binkert.org InstSeqNum inst_seq_num = inst->seqNum; 2268229Snate@binkert.org 2276657Snate@binkert.org Dependency inst_to_find(inst_seq_num); 2286657Snate@binkert.org 2298229Snate@binkert.org dep_it_t waiting_inst = waitingInsts.find(inst_to_find); 2308229Snate@binkert.org 2318229Snate@binkert.org assert(waiting_inst != waitingInsts.end()); 2328229Snate@binkert.org 2336657Snate@binkert.org if ((*waiting_inst).memDepReady) { 2346657Snate@binkert.org DPRINTF(MemDepUnit, "MemDepUnit: Instruction has its memory " 2356657Snate@binkert.org "dependencies resolved, adding it to the ready list.\n"); 2366657Snate@binkert.org 2376793SBrad.Beckmann@amd.com moveToReady(waiting_inst); 2386657Snate@binkert.org } else { 2396657Snate@binkert.org DPRINTF(MemDepUnit, "MemDepUnit: Instruction still waiting on " 2406657Snate@binkert.org "memory dependency.\n"); 2416657Snate@binkert.org 2426657Snate@binkert.org (*waiting_inst).regsReady = true; 2437002Snate@binkert.org } 2446657Snate@binkert.org} 2457007Snate@binkert.org 2467007Snate@binkert.orgtemplate <class MemDepPred, class Impl> 2477007Snate@binkert.orgvoid 2487007Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) 2497007Snate@binkert.org{ 2506657Snate@binkert.org DPRINTF(MemDepUnit, "MemDepUnit: Marking non speculative " 2516877Ssteve.reinhardt@amd.com "instruction PC %#x as ready.\n", 2526877Ssteve.reinhardt@amd.com inst->readPC()); 2536657Snate@binkert.org 2546877Ssteve.reinhardt@amd.com InstSeqNum inst_seq_num = inst->seqNum; 2556657Snate@binkert.org 2566657Snate@binkert.org Dependency inst_to_find(inst_seq_num); 2577002Snate@binkert.org 2587002Snate@binkert.org dep_it_t waiting_inst = waitingInsts.find(inst_to_find); 2596657Snate@binkert.org 2607567SBrad.Beckmann@amd.com assert(waiting_inst != waitingInsts.end()); 2617567SBrad.Beckmann@amd.com 2627922SBrad.Beckmann@amd.com moveToReady(waiting_inst); 2636881SBrad.Beckmann@amd.com} 2647002Snate@binkert.org 2657002Snate@binkert.orgtemplate <class MemDepPred, class Impl> 2666657Snate@binkert.orgvoid 2677002Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 2686902SBrad.Beckmann@amd.com{ 2696863Sdrh5@cs.wisc.edu assert(readyInsts.find(inst->seqNum) != readyInsts.end()); 2706863Sdrh5@cs.wisc.edu 2717007Snate@binkert.org DPRINTF(MemDepUnit, "MemDepUnit: Issuing instruction PC %#x.\n", 2726657Snate@binkert.org inst->readPC()); 2736657Snate@binkert.org 2746657Snate@binkert.org // Remove the instruction from the ready list. 2756657Snate@binkert.org readyInsts.erase(inst->seqNum); 2766657Snate@binkert.org 2776657Snate@binkert.org depPred.issued(inst->readPC(), inst->seqNum, inst->isStore()); 2786882SBrad.Beckmann@amd.com} 2796882SBrad.Beckmann@amd.com 2806882SBrad.Beckmann@amd.comtemplate <class MemDepPred, class Impl> 2816882SBrad.Beckmann@amd.comvoid 2826657Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 2836657Snate@binkert.org{ 2846657Snate@binkert.org // Only stores have dependents. 2856657Snate@binkert.org if (!inst->isStore()) { 2867007Snate@binkert.org return; 2877839Snilay@cs.wisc.edu } 2887839Snilay@cs.wisc.edu 2897839Snilay@cs.wisc.edu // Wake any dependencies. 2907839Snilay@cs.wisc.edu sd_it_t sd_it = storeDependents.find(inst->seqNum); 2917839Snilay@cs.wisc.edu 2927839Snilay@cs.wisc.edu // If there's no entry, then return. Really there should only be 2937839Snilay@cs.wisc.edu // no entry if the instruction is a load. 2947839Snilay@cs.wisc.edu if (sd_it == storeDependents.end()) { 2957839Snilay@cs.wisc.edu DPRINTF(MemDepUnit, "MemDepUnit: Instruction PC %#x, sequence " 2967839Snilay@cs.wisc.edu "number %i has no dependents.\n", 2977839Snilay@cs.wisc.edu inst->readPC(), inst->seqNum); 2987839Snilay@cs.wisc.edu 2997007Snate@binkert.org return; 3007007Snate@binkert.org } 3017007Snate@binkert.org 3027007Snate@binkert.org for (int i = 0; i < (*sd_it).second.size(); ++i ) { 3037007Snate@binkert.org dep_it_t woken_inst = (*sd_it).second[i]; 3047839Snilay@cs.wisc.edu 3057839Snilay@cs.wisc.edu DPRINTF(MemDepUnit, "MemDepUnit: Waking up a dependent inst, " 3067839Snilay@cs.wisc.edu "sequence number %i.\n", 3077839Snilay@cs.wisc.edu (*woken_inst).seqNum); 3087839Snilay@cs.wisc.edu#if 0 3097839Snilay@cs.wisc.edu // Should we have reached instructions that are actually squashed, 3107839Snilay@cs.wisc.edu // there will be no more useful instructions in this dependency 3117839Snilay@cs.wisc.edu // list. Break out early. 3127839Snilay@cs.wisc.edu if (waitingInsts.find(woken_inst) == waitingInsts.end()) { 3137839Snilay@cs.wisc.edu DPRINTF(MemDepUnit, "MemDepUnit: Dependents on inst PC %#x " 3147839Snilay@cs.wisc.edu "are squashed, starting at SN %i. Breaking early.\n", 3157839Snilay@cs.wisc.edu inst->readPC(), woken_inst); 3167007Snate@binkert.org break; 3177007Snate@binkert.org } 3187002Snate@binkert.org#endif 3196657Snate@binkert.org 3206657Snate@binkert.org if ((*woken_inst).regsReady) { 3216657Snate@binkert.org moveToReady(woken_inst); 3227055Snate@binkert.org } else { 3236657Snate@binkert.org (*woken_inst).memDepReady = true; 3246657Snate@binkert.org } 3256657Snate@binkert.org } 3266863Sdrh5@cs.wisc.edu 3277055Snate@binkert.org storeDependents.erase(sd_it); 3287567SBrad.Beckmann@amd.com} 3297567SBrad.Beckmann@amd.com 3307567SBrad.Beckmann@amd.comtemplate <class MemDepPred, class Impl> 3317567SBrad.Beckmann@amd.comvoid 3327567SBrad.Beckmann@amd.comMemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num) 3337542SBrad.Beckmann@amd.com{ 3347542SBrad.Beckmann@amd.com 3356657Snate@binkert.org if (!waitingInsts.empty()) { 3367007Snate@binkert.org dep_it_t waiting_it = waitingInsts.end(); 3376657Snate@binkert.org 3386657Snate@binkert.org --waiting_it; 3396657Snate@binkert.org 3406657Snate@binkert.org // Remove entries from the renamed list as long as we haven't reached 3416657Snate@binkert.org // the end and the entries continue to be younger than the squashed. 3426657Snate@binkert.org while (!waitingInsts.empty() && 3436657Snate@binkert.org (*waiting_it).seqNum > squashed_num) 3446657Snate@binkert.org { 3457839Snilay@cs.wisc.edu if (!(*waiting_it).memDepReady && 3467839Snilay@cs.wisc.edu (*waiting_it).storeDep != storeDependents.end()) { 3477839Snilay@cs.wisc.edu sd_it_t sd_it = (*waiting_it).storeDep; 3487839Snilay@cs.wisc.edu 3497839Snilay@cs.wisc.edu // Make sure the iterator that the store has pointing 3507839Snilay@cs.wisc.edu // back is actually to this instruction. 3517839Snilay@cs.wisc.edu assert((*sd_it).second.back() == waiting_it); 3527839Snilay@cs.wisc.edu 3537839Snilay@cs.wisc.edu // Now remove this from the store's list of dependent 3547839Snilay@cs.wisc.edu // instructions. 3557839Snilay@cs.wisc.edu (*sd_it).second.pop_back(); 3567839Snilay@cs.wisc.edu } 3577839Snilay@cs.wisc.edu 3587839Snilay@cs.wisc.edu waitingInsts.erase(waiting_it--); 3597839Snilay@cs.wisc.edu } 3607839Snilay@cs.wisc.edu } 3616657Snate@binkert.org 3626657Snate@binkert.org if (!readyInsts.empty()) { 3636657Snate@binkert.org sn_it_t ready_it = readyInsts.end(); 3646657Snate@binkert.org 3657839Snilay@cs.wisc.edu --ready_it; 3667839Snilay@cs.wisc.edu 3677839Snilay@cs.wisc.edu // Same for the ready list. 3687839Snilay@cs.wisc.edu while (!readyInsts.empty() && 3697839Snilay@cs.wisc.edu (*ready_it) > squashed_num) 3707839Snilay@cs.wisc.edu { 3717839Snilay@cs.wisc.edu readyInsts.erase(ready_it--); 3727839Snilay@cs.wisc.edu } 3737839Snilay@cs.wisc.edu } 3747839Snilay@cs.wisc.edu 3757839Snilay@cs.wisc.edu if (!storeDependents.empty()) { 3767839Snilay@cs.wisc.edu sd_it_t dep_it = storeDependents.end(); 3777839Snilay@cs.wisc.edu 3787839Snilay@cs.wisc.edu --dep_it; 3797839Snilay@cs.wisc.edu 3807839Snilay@cs.wisc.edu // Same for the dependencies list. 3816657Snate@binkert.org while (!storeDependents.empty() && 3826657Snate@binkert.org (*dep_it).first > squashed_num) 3836657Snate@binkert.org { 3846657Snate@binkert.org // This store's list of dependent instructions should be empty. 3857007Snate@binkert.org assert((*dep_it).second.empty()); 3866657Snate@binkert.org 3876657Snate@binkert.org storeDependents.erase(dep_it--); 3886657Snate@binkert.org } 3896657Snate@binkert.org } 3906657Snate@binkert.org 3916657Snate@binkert.org // Tell the dependency predictor to squash as well. 3926657Snate@binkert.org depPred.squash(squashed_num); 3936657Snate@binkert.org} 3946657Snate@binkert.org 3956657Snate@binkert.orgtemplate <class MemDepPred, class Impl> 3967007Snate@binkert.orgvoid 3976657Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 3986657Snate@binkert.org DynInstPtr &violating_load) 3996657Snate@binkert.org{ 4006657Snate@binkert.org DPRINTF(MemDepUnit, "MemDepUnit: Passing violating PCs to store sets," 4016657Snate@binkert.org " load: %#x, store: %#x\n", violating_load->readPC(), 4026999Snate@binkert.org store_inst->readPC()); 4036657Snate@binkert.org // Tell the memory dependence unit of the violation. 4046657Snate@binkert.org depPred.violation(violating_load->readPC(), store_inst->readPC()); 4056657Snate@binkert.org} 4066657Snate@binkert.org 4077007Snate@binkert.orgtemplate <class MemDepPred, class Impl> 4086657Snate@binkert.orginline void 4096657Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::moveToReady(dep_it_t &woken_inst) 4106657Snate@binkert.org{ 4116657Snate@binkert.org DPRINTF(MemDepUnit, "MemDepUnit: Adding instruction sequence number %i " 4126657Snate@binkert.org "to the ready list.\n", (*woken_inst).seqNum); 4137832Snate@binkert.org 4147002Snate@binkert.org // Add it to the ready list. 4157002Snate@binkert.org readyInsts.insert((*woken_inst).seqNum); 4167002Snate@binkert.org 4177056Snate@binkert.org // Remove it from the waiting instructions. 4188232Snate@binkert.org waitingInsts.erase(woken_inst); 4198232Snate@binkert.org} 4206657Snate@binkert.org