lsq_unit_impl.hh revision 9527:68154bc0e0ea
12SN/A/* 21762SN/A * Copyright (c) 2010-2012 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316216Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322439SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336216Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34146SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35146SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36146SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37146SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38146SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39146SN/A * 401717SN/A * Authors: Kevin Lim 41146SN/A * Korey Sewell 426216Snate@binkert.org */ 436658Snate@binkert.org 441717SN/A#include "arch/generic/debugfaults.hh" 45146SN/A#include "arch/locked_mem.hh" 461977SN/A#include "base/str.hh" 472623SN/A#include "config/the_isa.hh" 482683Sktlim@umich.edu#include "cpu/checker/cpu.hh" 491717SN/A#include "cpu/o3/lsq.hh" 50146SN/A#include "cpu/o3/lsq_unit.hh" 512683Sktlim@umich.edu#include "debug/Activity.hh" 523348Sbinkertn@umich.edu#include "debug/IEW.hh" 536105Ssteve.reinhardt@amd.com#include "debug/LSQUnit.hh" 546216Snate@binkert.org#include "debug/O3PipeView.hh" 552036SN/A#include "mem/packet.hh" 56146SN/A#include "mem/request.hh" 5756SN/A 5856SN/Atemplate<class Impl> 59695SN/ALSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 602901Ssaidi@eecs.umich.edu LSQUnit *lsq_ptr) 612SN/A : Event(Default_Pri, AutoDelete), 621858SN/A inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 633565Sgblack@eecs.umich.edu{ 643565Sgblack@eecs.umich.edu} 652171SN/A 662170SN/Atemplate<class Impl> 673562Sgblack@eecs.umich.eduvoid 68146SN/ALSQUnit<Impl>::WritebackEvent::process() 692462SN/A{ 70146SN/A assert(!lsqPtr->cpu->switchedOut()); 712SN/A 722SN/A lsqPtr->writeback(inst, pkt); 732449SN/A 741355SN/A if (pkt->senderState) 755529Snate@binkert.org delete pkt->senderState; 764495Sacolyte@umich.edu 77224SN/A delete pkt->req; 781858SN/A delete pkt; 792683Sktlim@umich.edu} 802420SN/A 815529Snate@binkert.orgtemplate<class Impl> 826331Sgblack@eecs.umich.educonst char * 832420SN/ALSQUnit<Impl>::WritebackEvent::description() const 842SN/A{ 856029Ssteve.reinhardt@amd.com return "Store writeback"; 862672Sktlim@umich.edu} 872683Sktlim@umich.edu 882SN/Atemplate<class Impl> 892SN/Avoid 90334SN/ALSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 91140SN/A{ 92334SN/A LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 932SN/A DynInstPtr inst = state->inst; 942SN/A DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 952SN/A DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 962680Sktlim@umich.edu 974377Sgblack@eecs.umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 985169Ssaidi@eecs.umich.edu 994377Sgblack@eecs.umich.edu // If this is a split access, wait until all packets are received. 1004377Sgblack@eecs.umich.edu if (TheISA::HasUnalignedMemAcc && !state->complete()) { 1012SN/A delete pkt->req; 1022SN/A delete pkt; 1032623SN/A return; 1042SN/A } 1052SN/A 1062SN/A assert(!cpu->switchedOut()); 107180SN/A if (inst->isSquashed()) { 1082623SN/A iewStage->decrWb(inst->seqNum); 109393SN/A } else { 110393SN/A if (!state->noWB) { 111393SN/A if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 112393SN/A !state->isLoad) { 113384SN/A writeback(inst, pkt); 114384SN/A } else { 115393SN/A writeback(inst, state->mainPkt); 1162623SN/A } 117393SN/A } 118393SN/A 119393SN/A if (inst->isStore()) { 120393SN/A completeStore(state->idx); 121384SN/A } 122189SN/A } 123189SN/A 1242623SN/A if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 1252SN/A delete state->mainPkt->req; 126729SN/A delete state->mainPkt; 127334SN/A } 1282SN/A delete state; 1292SN/A delete pkt->req; 1302SN/A delete pkt; 1312SN/A} 1322SN/A 1332SN/Atemplate <class Impl> 1342SN/ALSQUnit<Impl>::LSQUnit() 1352SN/A : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 1362SN/A isStoreBlocked(false), isLoadBlocked(false), 1372SN/A loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false) 1382SN/A{ 1392SN/A} 1401001SN/A 1411001SN/Atemplate<class Impl> 1421001SN/Avoid 1431001SN/ALSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1441001SN/A LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1452SN/A unsigned id) 1462SN/A{ 1472SN/A cpu = cpu_ptr; 1482SN/A iewStage = iew_ptr; 1492SN/A 1502SN/A DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1512SN/A 1522SN/A lsq = lsq_ptr; 1532SN/A 1542SN/A lsqID = id; 1552SN/A 1562SN/A // Add 1 for the sentinel entry (they are circular queues). 1572SN/A LQEntries = maxLQEntries + 1; 1582SN/A SQEntries = maxSQEntries + 1; 1592SN/A 1602SN/A loadQueue.resize(LQEntries); 1612SN/A storeQueue.resize(SQEntries); 1622390SN/A 1632390SN/A depCheckShift = params->LSQDepCheckShift; 1642390SN/A checkLoads = params->LSQCheckLoads; 1652390SN/A cachePorts = params->cachePorts; 1662390SN/A needsTSO = params->needsTSO; 1672390SN/A 1682390SN/A resetState(); 1692390SN/A} 1702390SN/A 1712390SN/A 1722390SN/Atemplate<class Impl> 1732390SN/Avoid 174385SN/ALSQUnit<Impl>::resetState() 1752SN/A{ 1762SN/A loads = stores = storesToWB = 0; 1772SN/A 1782623SN/A loadHead = loadTail = 0; 179334SN/A 1802361SN/A storeHead = storeWBIdx = storeTail = 0; 1815496Ssaidi@eecs.umich.edu 182334SN/A usedPorts = 0; 183334SN/A 184334SN/A retryPkt = NULL; 1852623SN/A memDepViolator = NULL; 1862SN/A 1875496Ssaidi@eecs.umich.edu blockedLoadSeqNum = 0; 188921SN/A 1892915Sktlim@umich.edu stalled = false; 1902915Sktlim@umich.edu isLoadBlocked = false; 1912683Sktlim@umich.edu loadBlockedHandled = false; 1922SN/A 1932SN/A cacheBlockMask = 0; 1942SN/A} 1952623SN/A 1962SN/Atemplate<class Impl> 1975496Ssaidi@eecs.umich.edustd::string 198921SN/ALSQUnit<Impl>::name() const 1992915Sktlim@umich.edu{ 2002915Sktlim@umich.edu if (Impl::MaxThreads == 1) { 2012SN/A return iewStage->name() + ".lsq"; 2022SN/A } else { 2032SN/A return iewStage->name() + ".lsq.thread" + to_string(lsqID); 2046221Snate@binkert.org } 2052SN/A} 2062SN/A 2072SN/Atemplate<class Impl> 208595SN/Avoid 2092623SN/ALSQUnit<Impl>::regStats() 210595SN/A{ 2112390SN/A lsqForwLoads 2121080SN/A .name(name() + ".forwLoads") 2136227Snate@binkert.org .desc("Number of loads that had data forwarded from stores"); 2146227Snate@binkert.org 2151080SN/A invAddrLoads 2161080SN/A .name(name() + ".invAddrLoads") 2171080SN/A .desc("Number of loads ignored due to an invalid address"); 2181080SN/A 2191080SN/A lsqSquashedLoads 2201121SN/A .name(name() + ".squashedLoads") 2212107SN/A .desc("Number of loads squashed"); 2221089SN/A 2231089SN/A lsqIgnoredResponses 2241080SN/A .name(name() + ".ignoredResponses") 2251080SN/A .desc("Number of memory responses ignored because the instruction is squashed"); 2261080SN/A 2271080SN/A lsqMemOrderViolation 228595SN/A .name(name() + ".memOrderViolation") 2292623SN/A .desc("Number of memory ordering violations"); 2302683Sktlim@umich.edu 231595SN/A lsqSquashedStores 2322090SN/A .name(name() + ".squashedStores") 2332683Sktlim@umich.edu .desc("Number of stores squashed"); 2342683Sktlim@umich.edu 235595SN/A invAddrSwpfs 2362205SN/A .name(name() + ".invAddrSwpfs") 2372205SN/A .desc("Number of software prefetches ignored due to an invalid address"); 2382683Sktlim@umich.edu 2392683Sktlim@umich.edu lsqBlockedLoads 240595SN/A .name(name() + ".blockedLoads") 241595SN/A .desc("Number of blocked loads due to partial load-store forwarding"); 2422390SN/A 2432423SN/A lsqRescheduledLoads 2442390SN/A .name(name() + ".rescheduledLoads") 245595SN/A .desc("Number of loads that were rescheduled"); 246595SN/A 247595SN/A lsqCacheBlocked 2482623SN/A .name(name() + ".cacheBlocked") 249595SN/A .desc("Number of times an access to memory failed due to the cache being blocked"); 2502390SN/A} 2511080SN/A 2526227Snate@binkert.orgtemplate<class Impl> 2536227Snate@binkert.orgvoid 2541080SN/ALSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 2551080SN/A{ 256595SN/A dcachePort = dcache_port; 2572683Sktlim@umich.edu} 2581080SN/A 2591080SN/Atemplate<class Impl> 2601080SN/Avoid 2611121SN/ALSQUnit<Impl>::clearLQ() 2622107SN/A{ 2631089SN/A loadQueue.clear(); 2641080SN/A} 2651089SN/A 2661080SN/Atemplate<class Impl> 2671080SN/Avoid 2681080SN/ALSQUnit<Impl>::clearSQ() 269595SN/A{ 2702683Sktlim@umich.edu storeQueue.clear(); 2711080SN/A} 2722090SN/A 2731080SN/Atemplate<class Impl> 274595SN/Avoid 2752683Sktlim@umich.eduLSQUnit<Impl>::drainSanityCheck() const 2762683Sktlim@umich.edu{ 277595SN/A for (int i = 0; i < loadQueue.size(); ++i) 2782683Sktlim@umich.edu assert(!loadQueue[i]); 2791098SN/A 2801098SN/A assert(storesToWB == 0); 2811098SN/A assert(!retryPkt); 2822683Sktlim@umich.edu} 2831098SN/A 2841098SN/Atemplate<class Impl> 2851098SN/Avoid 2861098SN/ALSQUnit<Impl>::takeOverFrom() 2871098SN/A{ 288595SN/A resetState(); 2892205SN/A} 2902205SN/A 2912205SN/Atemplate<class Impl> 292595SN/Avoid 2932390SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2942420SN/A{ 2952423SN/A unsigned size_plus_sentinel = size + 1; 2962390SN/A assert(size_plus_sentinel >= LQEntries); 297595SN/A 298595SN/A if (size_plus_sentinel > LQEntries) { 2991858SN/A while (size_plus_sentinel > loadQueue.size()) { 3002SN/A DynInstPtr dummy; 3012623SN/A loadQueue.push_back(dummy); 3022SN/A LQEntries++; 3032680Sktlim@umich.edu } 3042SN/A } else { 3052SN/A LQEntries = size_plus_sentinel; 3062SN/A } 3071858SN/A 3082SN/A} 3095807Snate@binkert.org 3102SN/Atemplate<class Impl> 3115807Snate@binkert.orgvoid 3125807Snate@binkert.orgLSQUnit<Impl>::resizeSQ(unsigned size) 3132SN/A{ 3145807Snate@binkert.org unsigned size_plus_sentinel = size + 1; 3155807Snate@binkert.org if (size_plus_sentinel > SQEntries) { 3162SN/A while (size_plus_sentinel > storeQueue.size()) { 3172SN/A SQEntry dummy; 3182SN/A storeQueue.push_back(dummy); 3192SN/A SQEntries++; 3202623SN/A } 3212SN/A } else { 3221858SN/A SQEntries = size_plus_sentinel; 3235704Snate@binkert.org } 3245647Sgblack@eecs.umich.edu} 3252SN/A 3263520Sgblack@eecs.umich.edutemplate <class Impl> 3275835Sgblack@eecs.umich.eduvoid 3285647Sgblack@eecs.umich.eduLSQUnit<Impl>::insert(DynInstPtr &inst) 3293520Sgblack@eecs.umich.edu{ 3302SN/A assert(inst->isMemRef()); 3312SN/A 3322SN/A assert(inst->isLoad() || inst->isStore()); 3332623SN/A 3342SN/A if (inst->isLoad()) { 3352623SN/A insertLoad(inst); 3365894Sgblack@eecs.umich.edu } else { 3372662Sstever@eecs.umich.edu insertStore(inst); 3382623SN/A } 3394514Ssaidi@eecs.umich.edu 3404495Sacolyte@umich.edu inst->setInLSQ(); 3412623SN/A} 3423093Sksewell@umich.edu 3434495Sacolyte@umich.edutemplate <class Impl> 3443093Sksewell@umich.eduvoid 3453093Sksewell@umich.eduLSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3464564Sgblack@eecs.umich.edu{ 3472741Sksewell@umich.edu assert((loadTail + 1) % LQEntries != loadHead); 3482741Sksewell@umich.edu assert(loads < LQEntries); 3492623SN/A 3504564Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 3516105Ssteve.reinhardt@amd.com load_inst->pcState(), loadTail, load_inst->seqNum); 3522623SN/A 3532623SN/A load_inst->lqIdx = loadTail; 3542623SN/A 3552623SN/A if (stores == 0) { 3562623SN/A load_inst->sqIdx = -1; 3572623SN/A } else { 3582SN/A load_inst->sqIdx = storeTail; 3592683Sktlim@umich.edu } 3602427SN/A 3612683Sktlim@umich.edu loadQueue[loadTail] = load_inst; 3622427SN/A 3632SN/A incrLdIdx(loadTail); 3642623SN/A 3652623SN/A ++loads; 3662SN/A} 3672623SN/A 3682623SN/Atemplate <class Impl> 3694377Sgblack@eecs.umich.eduvoid 3705665Sgblack@eecs.umich.eduLSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3714377Sgblack@eecs.umich.edu{ 3725665Sgblack@eecs.umich.edu // Make sure it is not full before inserting an instruction. 3735665Sgblack@eecs.umich.edu assert((storeTail + 1) % SQEntries != storeHead); 3745665Sgblack@eecs.umich.edu assert(stores < SQEntries); 3755665Sgblack@eecs.umich.edu 3765665Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 3774181Sgblack@eecs.umich.edu store_inst->pcState(), storeTail, store_inst->seqNum); 3784181Sgblack@eecs.umich.edu 3794181Sgblack@eecs.umich.edu store_inst->sqIdx = storeTail; 3804182Sgblack@eecs.umich.edu store_inst->lqIdx = loadTail; 3814182Sgblack@eecs.umich.edu 3824182Sgblack@eecs.umich.edu storeQueue[storeTail] = SQEntry(store_inst); 3834593Sgblack@eecs.umich.edu 3844593Sgblack@eecs.umich.edu incrStIdx(storeTail); 3854593Sgblack@eecs.umich.edu 3864593Sgblack@eecs.umich.edu ++stores; 3874593Sgblack@eecs.umich.edu} 3884377Sgblack@eecs.umich.edu 3894377Sgblack@eecs.umich.edutemplate <class Impl> 3904377Sgblack@eecs.umich.edutypename Impl::DynInstPtr 3914377Sgblack@eecs.umich.eduLSQUnit<Impl>::getMemDepViolator() 3924377Sgblack@eecs.umich.edu{ 3934377Sgblack@eecs.umich.edu DynInstPtr temp = memDepViolator; 3944377Sgblack@eecs.umich.edu 3954377Sgblack@eecs.umich.edu memDepViolator = NULL; 3964572Sacolyte@umich.edu 3974572Sacolyte@umich.edu return temp; 3984377Sgblack@eecs.umich.edu} 3994377Sgblack@eecs.umich.edu 4004377Sgblack@eecs.umich.edutemplate <class Impl> 4014377Sgblack@eecs.umich.eduunsigned 4024181Sgblack@eecs.umich.eduLSQUnit<Impl>::numFreeEntries() 4034181Sgblack@eecs.umich.edu{ 4044181Sgblack@eecs.umich.edu unsigned free_lq_entries = LQEntries - loads; 4054539Sgblack@eecs.umich.edu unsigned free_sq_entries = SQEntries - stores; 4063276Sgblack@eecs.umich.edu 4075665Sgblack@eecs.umich.edu // Both the LQ and SQ entries have an extra dummy entry to differentiate 4083280Sgblack@eecs.umich.edu // empty/full conditions. Subtract 1 from the free entries. 4093280Sgblack@eecs.umich.edu if (free_lq_entries < free_sq_entries) { 4103276Sgblack@eecs.umich.edu return free_lq_entries - 1; 4113276Sgblack@eecs.umich.edu } else { 4123276Sgblack@eecs.umich.edu return free_sq_entries - 1; 4135665Sgblack@eecs.umich.edu } 4143276Sgblack@eecs.umich.edu} 4153276Sgblack@eecs.umich.edu 4164181Sgblack@eecs.umich.edutemplate <class Impl> 4174181Sgblack@eecs.umich.eduvoid 4184181Sgblack@eecs.umich.eduLSQUnit<Impl>::checkSnoop(PacketPtr pkt) 4194522Ssaidi@eecs.umich.edu{ 4205784Sgblack@eecs.umich.edu int load_idx = loadHead; 4215784Sgblack@eecs.umich.edu 4225784Sgblack@eecs.umich.edu if (!cacheBlockMask) { 4232470SN/A assert(dcachePort); 4244181Sgblack@eecs.umich.edu Addr bs = dcachePort->peerBlockSize(); 4254181Sgblack@eecs.umich.edu 4264522Ssaidi@eecs.umich.edu // Make sure we actually got a size 4272623SN/A assert(bs != 0); 4282623SN/A 4294181Sgblack@eecs.umich.edu cacheBlockMask = ~(bs - 1); 4302623SN/A } 4314181Sgblack@eecs.umich.edu 4322623SN/A // Unlock the cpu-local monitor when the CPU sees a snoop to a locked 4332623SN/A // address. The CPU can speculatively execute a LL operation after a pending 4342623SN/A // SC operation in the pipeline and that can make the cache monitor the CPU 4352623SN/A // is connected to valid while it really shouldn't be. 4362623SN/A for (int x = 0; x < cpu->numActiveThreads(); x++) { 4372623SN/A ThreadContext *tc = cpu->getContext(x); 4385086Sgblack@eecs.umich.edu bool no_squash = cpu->thread[x]->noSquashFromTC; 4393577Sgblack@eecs.umich.edu cpu->thread[x]->noSquashFromTC = true; 4402683Sktlim@umich.edu TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 4415086Sgblack@eecs.umich.edu cpu->thread[x]->noSquashFromTC = no_squash; 4422623SN/A } 4432683Sktlim@umich.edu 4442623SN/A // If this is the only load in the LSQ we don't care 4452420SN/A if (load_idx == loadTail) 4462SN/A return; 4472623SN/A incrLdIdx(load_idx); 4482623SN/A 4492SN/A DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 4502SN/A Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 4512623SN/A while (load_idx != loadTail) { 4522623SN/A DynInstPtr ld_inst = loadQueue[load_idx]; 4532623SN/A 4542623SN/A if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 4552SN/A incrLdIdx(load_idx); 4565953Ssaidi@eecs.umich.edu continue; 4575953Ssaidi@eecs.umich.edu } 4585953Ssaidi@eecs.umich.edu 4595953Ssaidi@eecs.umich.edu Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 4602683Sktlim@umich.edu DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 4612644Sstever@eecs.umich.edu ld_inst->seqNum, load_addr, invalidate_addr); 4622644Sstever@eecs.umich.edu 4634046Sbinkertn@umich.edu if (load_addr == invalidate_addr) { 4644046Sbinkertn@umich.edu if (ld_inst->possibleLoadViolation()) { 4654046Sbinkertn@umich.edu DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 4662644Sstever@eecs.umich.edu ld_inst->physEffAddr, pkt->getAddr(), ld_inst->seqNum); 4672623SN/A 4682SN/A // Mark the load for re-execution 4692SN/A ld_inst->fault = new ReExec; 4702623SN/A } else { 4712623SN/A // If a older load checks this and it's true 4722623SN/A // then we might have missed the snoop 4734377Sgblack@eecs.umich.edu // in which case we need to invalidate to be sure 4744377Sgblack@eecs.umich.edu ld_inst->hitExternalSnoop(true); 4752090SN/A } 4763905Ssaidi@eecs.umich.edu } 4775120Sgblack@eecs.umich.edu incrLdIdx(load_idx); 4785281Sgblack@eecs.umich.edu } 4794377Sgblack@eecs.umich.edu return; 4803276Sgblack@eecs.umich.edu} 4814539Sgblack@eecs.umich.edu 4825665Sgblack@eecs.umich.edutemplate <class Impl> 4835665Sgblack@eecs.umich.eduFault 4845665Sgblack@eecs.umich.eduLSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 4853276Sgblack@eecs.umich.edu{ 4863276Sgblack@eecs.umich.edu Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 4873280Sgblack@eecs.umich.edu Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 4885665Sgblack@eecs.umich.edu 4895665Sgblack@eecs.umich.edu /** @todo in theory you only need to check an instruction that has executed 4903276Sgblack@eecs.umich.edu * however, there isn't a good way in the pipeline at the moment to check 4913276Sgblack@eecs.umich.edu * all instructions that will execute before the store writes back. Thus, 4925665Sgblack@eecs.umich.edu * like the implementation that came before it, we're overly conservative. 4933276Sgblack@eecs.umich.edu */ 4943280Sgblack@eecs.umich.edu while (load_idx != loadTail) { 4953276Sgblack@eecs.umich.edu DynInstPtr ld_inst = loadQueue[load_idx]; 4963276Sgblack@eecs.umich.edu if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 4973280Sgblack@eecs.umich.edu incrLdIdx(load_idx); 4983276Sgblack@eecs.umich.edu continue; 4993276Sgblack@eecs.umich.edu } 5003276Sgblack@eecs.umich.edu 5013276Sgblack@eecs.umich.edu Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 5023276Sgblack@eecs.umich.edu Addr ld_eff_addr2 = 5033276Sgblack@eecs.umich.edu (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 5043276Sgblack@eecs.umich.edu 5052SN/A if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 5062SN/A if (inst->isLoad()) { 5072SN/A // If this load is to the same block as an external snoop 5085250Sksewell@umich.edu // invalidate that we've observed then the load needs to be 5095222Sksewell@umich.edu // squashed as it could have newer data 5105222Sksewell@umich.edu if (ld_inst->hitExternalSnoop()) { 5115222Sksewell@umich.edu if (!memDepViolator || 5125222Sksewell@umich.edu ld_inst->seqNum < memDepViolator->seqNum) { 5135222Sksewell@umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 5145222Sksewell@umich.edu "and [sn:%lli] at address %#x\n", 5155222Sksewell@umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5165222Sksewell@umich.edu memDepViolator = ld_inst; 5175222Sksewell@umich.edu 5185222Sksewell@umich.edu ++lsqMemOrderViolation; 5195222Sksewell@umich.edu 5205222Sksewell@umich.edu return new GenericISA::M5PanicFault( 5215222Sksewell@umich.edu "Detected fault with inst [sn:%lli] and " 5225222Sksewell@umich.edu "[sn:%lli] at address %#x\n", 5235222Sksewell@umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5245222Sksewell@umich.edu } 5255222Sksewell@umich.edu } 5265222Sksewell@umich.edu 5275222Sksewell@umich.edu // Otherwise, mark the load has a possible load violation 5285222Sksewell@umich.edu // and if we see a snoop before it's commited, we need to squash 5295222Sksewell@umich.edu ld_inst->possibleLoadViolation(true); 5305222Sksewell@umich.edu DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 5315222Sksewell@umich.edu " between instructions [sn:%lli] and [sn:%lli]\n", 5325222Sksewell@umich.edu inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 5335222Sksewell@umich.edu } else { 5345222Sksewell@umich.edu // A load/store incorrectly passed this store. 5355222Sksewell@umich.edu // Check if we already have a violator, or if it's newer 5365222Sksewell@umich.edu // squash and refetch. 5375222Sksewell@umich.edu if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 5385222Sksewell@umich.edu break; 5395222Sksewell@umich.edu 5405222Sksewell@umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 5415250Sksewell@umich.edu "[sn:%lli] at address %#x\n", 542 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 543 memDepViolator = ld_inst; 544 545 ++lsqMemOrderViolation; 546 547 return new GenericISA::M5PanicFault("Detected fault with " 548 "inst [sn:%lli] and [sn:%lli] at address %#x\n", 549 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 550 } 551 } 552 553 incrLdIdx(load_idx); 554 } 555 return NoFault; 556} 557 558 559 560 561template <class Impl> 562Fault 563LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 564{ 565 using namespace TheISA; 566 // Execute a specific load. 567 Fault load_fault = NoFault; 568 569 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 570 inst->pcState(), inst->seqNum); 571 572 assert(!inst->isSquashed()); 573 574 load_fault = inst->initiateAcc(); 575 576 if (inst->isTranslationDelayed() && 577 load_fault == NoFault) 578 return load_fault; 579 580 // If the instruction faulted or predicated false, then we need to send it 581 // along to commit without the instruction completing. 582 if (load_fault != NoFault || inst->readPredicate() == false) { 583 // Send this instruction to commit, also make sure iew stage 584 // realizes there is activity. 585 // Mark it as executed unless it is an uncached load that 586 // needs to hit the head of commit. 587 if (inst->readPredicate() == false) 588 inst->forwardOldRegs(); 589 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 590 inst->seqNum, 591 (load_fault != NoFault ? "fault" : "predication")); 592 if (!(inst->hasRequest() && inst->uncacheable()) || 593 inst->isAtCommit()) { 594 inst->setExecuted(); 595 } 596 iewStage->instToCommit(inst); 597 iewStage->activityThisCycle(); 598 } else if (!loadBlocked()) { 599 assert(inst->effAddrValid()); 600 int load_idx = inst->lqIdx; 601 incrLdIdx(load_idx); 602 603 if (checkLoads) 604 return checkViolations(load_idx, inst); 605 } 606 607 return load_fault; 608} 609 610template <class Impl> 611Fault 612LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 613{ 614 using namespace TheISA; 615 // Make sure that a store exists. 616 assert(stores != 0); 617 618 int store_idx = store_inst->sqIdx; 619 620 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 621 store_inst->pcState(), store_inst->seqNum); 622 623 assert(!store_inst->isSquashed()); 624 625 // Check the recently completed loads to see if any match this store's 626 // address. If so, then we have a memory ordering violation. 627 int load_idx = store_inst->lqIdx; 628 629 Fault store_fault = store_inst->initiateAcc(); 630 631 if (store_inst->isTranslationDelayed() && 632 store_fault == NoFault) 633 return store_fault; 634 635 if (store_inst->readPredicate() == false) 636 store_inst->forwardOldRegs(); 637 638 if (storeQueue[store_idx].size == 0) { 639 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 640 store_inst->pcState(), store_inst->seqNum); 641 642 return store_fault; 643 } else if (store_inst->readPredicate() == false) { 644 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 645 store_inst->seqNum); 646 return store_fault; 647 } 648 649 assert(store_fault == NoFault); 650 651 if (store_inst->isStoreConditional()) { 652 // Store conditionals need to set themselves as able to 653 // writeback if we haven't had a fault by here. 654 storeQueue[store_idx].canWB = true; 655 656 ++storesToWB; 657 } 658 659 return checkViolations(load_idx, store_inst); 660 661} 662 663template <class Impl> 664void 665LSQUnit<Impl>::commitLoad() 666{ 667 assert(loadQueue[loadHead]); 668 669 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 670 loadQueue[loadHead]->pcState()); 671 672 loadQueue[loadHead] = NULL; 673 674 incrLdIdx(loadHead); 675 676 --loads; 677} 678 679template <class Impl> 680void 681LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 682{ 683 assert(loads == 0 || loadQueue[loadHead]); 684 685 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 686 commitLoad(); 687 } 688} 689 690template <class Impl> 691void 692LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 693{ 694 assert(stores == 0 || storeQueue[storeHead].inst); 695 696 int store_idx = storeHead; 697 698 while (store_idx != storeTail) { 699 assert(storeQueue[store_idx].inst); 700 // Mark any stores that are now committed and have not yet 701 // been marked as able to write back. 702 if (!storeQueue[store_idx].canWB) { 703 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 704 break; 705 } 706 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 707 "%s [sn:%lli]\n", 708 storeQueue[store_idx].inst->pcState(), 709 storeQueue[store_idx].inst->seqNum); 710 711 storeQueue[store_idx].canWB = true; 712 713 ++storesToWB; 714 } 715 716 incrStIdx(store_idx); 717 } 718} 719 720template <class Impl> 721void 722LSQUnit<Impl>::writebackPendingStore() 723{ 724 if (hasPendingPkt) { 725 assert(pendingPkt != NULL); 726 727 // If the cache is blocked, this will store the packet for retry. 728 if (sendStore(pendingPkt)) { 729 storePostSend(pendingPkt); 730 } 731 pendingPkt = NULL; 732 hasPendingPkt = false; 733 } 734} 735 736template <class Impl> 737void 738LSQUnit<Impl>::writebackStores() 739{ 740 // First writeback the second packet from any split store that didn't 741 // complete last cycle because there weren't enough cache ports available. 742 if (TheISA::HasUnalignedMemAcc) { 743 writebackPendingStore(); 744 } 745 746 while (storesToWB > 0 && 747 storeWBIdx != storeTail && 748 storeQueue[storeWBIdx].inst && 749 storeQueue[storeWBIdx].canWB && 750 ((!needsTSO) || (!storeInFlight)) && 751 usedPorts < cachePorts) { 752 753 if (isStoreBlocked || lsq->cacheBlocked()) { 754 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 755 " is blocked!\n"); 756 break; 757 } 758 759 // Store didn't write any data so no need to write it back to 760 // memory. 761 if (storeQueue[storeWBIdx].size == 0) { 762 completeStore(storeWBIdx); 763 764 incrStIdx(storeWBIdx); 765 766 continue; 767 } 768 769 ++usedPorts; 770 771 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 772 incrStIdx(storeWBIdx); 773 774 continue; 775 } 776 777 assert(storeQueue[storeWBIdx].req); 778 assert(!storeQueue[storeWBIdx].committed); 779 780 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 781 assert(storeQueue[storeWBIdx].sreqLow); 782 assert(storeQueue[storeWBIdx].sreqHigh); 783 } 784 785 DynInstPtr inst = storeQueue[storeWBIdx].inst; 786 787 Request *req = storeQueue[storeWBIdx].req; 788 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 789 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 790 791 storeQueue[storeWBIdx].committed = true; 792 793 assert(!inst->memData); 794 inst->memData = new uint8_t[64]; 795 796 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 797 798 MemCmd command = 799 req->isSwap() ? MemCmd::SwapReq : 800 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 801 PacketPtr data_pkt; 802 PacketPtr snd_data_pkt = NULL; 803 804 LSQSenderState *state = new LSQSenderState; 805 state->isLoad = false; 806 state->idx = storeWBIdx; 807 state->inst = inst; 808 809 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 810 811 // Build a single data packet if the store isn't split. 812 data_pkt = new Packet(req, command); 813 data_pkt->dataStatic(inst->memData); 814 data_pkt->senderState = state; 815 } else { 816 // Create two packets if the store is split in two. 817 data_pkt = new Packet(sreqLow, command); 818 snd_data_pkt = new Packet(sreqHigh, command); 819 820 data_pkt->dataStatic(inst->memData); 821 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 822 823 data_pkt->senderState = state; 824 snd_data_pkt->senderState = state; 825 826 state->isSplit = true; 827 state->outstanding = 2; 828 829 // Can delete the main request now. 830 delete req; 831 req = sreqLow; 832 } 833 834 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 835 "to Addr:%#x, data:%#x [sn:%lli]\n", 836 storeWBIdx, inst->pcState(), 837 req->getPaddr(), (int)*(inst->memData), 838 inst->seqNum); 839 840 // @todo: Remove this SC hack once the memory system handles it. 841 if (inst->isStoreConditional()) { 842 assert(!storeQueue[storeWBIdx].isSplit); 843 // Disable recording the result temporarily. Writing to 844 // misc regs normally updates the result, but this is not 845 // the desired behavior when handling store conditionals. 846 inst->recordResult(false); 847 bool success = TheISA::handleLockedWrite(inst.get(), req); 848 inst->recordResult(true); 849 850 if (!success) { 851 // Instantly complete this store. 852 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 853 "Instantly completing it.\n", 854 inst->seqNum); 855 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 856 cpu->schedule(wb, curTick() + 1); 857 if (cpu->checker) { 858 // Make sure to set the LLSC data for verification 859 // if checker is loaded 860 inst->reqToVerify->setExtraData(0); 861 inst->completeAcc(data_pkt); 862 } 863 completeStore(storeWBIdx); 864 incrStIdx(storeWBIdx); 865 continue; 866 } 867 } else { 868 // Non-store conditionals do not need a writeback. 869 state->noWB = true; 870 } 871 872 bool split = 873 TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 874 875 ThreadContext *thread = cpu->tcBase(lsqID); 876 877 if (req->isMmappedIpr()) { 878 assert(!inst->isStoreConditional()); 879 TheISA::handleIprWrite(thread, data_pkt); 880 delete data_pkt; 881 if (split) { 882 assert(snd_data_pkt->req->isMmappedIpr()); 883 TheISA::handleIprWrite(thread, snd_data_pkt); 884 delete snd_data_pkt; 885 delete sreqLow; 886 delete sreqHigh; 887 } 888 delete state; 889 delete req; 890 completeStore(storeWBIdx); 891 incrStIdx(storeWBIdx); 892 } else if (!sendStore(data_pkt)) { 893 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 894 "retry later\n", 895 inst->seqNum); 896 897 // Need to store the second packet, if split. 898 if (split) { 899 state->pktToSend = true; 900 state->pendingPacket = snd_data_pkt; 901 } 902 } else { 903 904 // If split, try to send the second packet too 905 if (split) { 906 assert(snd_data_pkt); 907 908 // Ensure there are enough ports to use. 909 if (usedPorts < cachePorts) { 910 ++usedPorts; 911 if (sendStore(snd_data_pkt)) { 912 storePostSend(snd_data_pkt); 913 } else { 914 DPRINTF(IEW, "D-Cache became blocked when writing" 915 " [sn:%lli] second packet, will retry later\n", 916 inst->seqNum); 917 } 918 } else { 919 920 // Store the packet for when there's free ports. 921 assert(pendingPkt == NULL); 922 pendingPkt = snd_data_pkt; 923 hasPendingPkt = true; 924 } 925 } else { 926 927 // Not a split store. 928 storePostSend(data_pkt); 929 } 930 } 931 } 932 933 // Not sure this should set it to 0. 934 usedPorts = 0; 935 936 assert(stores >= 0 && storesToWB >= 0); 937} 938 939/*template <class Impl> 940void 941LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 942{ 943 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 944 mshrSeqNums.end(), 945 seqNum); 946 947 if (mshr_it != mshrSeqNums.end()) { 948 mshrSeqNums.erase(mshr_it); 949 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 950 } 951}*/ 952 953template <class Impl> 954void 955LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 956{ 957 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 958 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 959 960 int load_idx = loadTail; 961 decrLdIdx(load_idx); 962 963 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 964 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 965 "[sn:%lli]\n", 966 loadQueue[load_idx]->pcState(), 967 loadQueue[load_idx]->seqNum); 968 969 if (isStalled() && load_idx == stallingLoadIdx) { 970 stalled = false; 971 stallingStoreIsn = 0; 972 stallingLoadIdx = 0; 973 } 974 975 // Clear the smart pointer to make sure it is decremented. 976 loadQueue[load_idx]->setSquashed(); 977 loadQueue[load_idx] = NULL; 978 --loads; 979 980 // Inefficient! 981 loadTail = load_idx; 982 983 decrLdIdx(load_idx); 984 ++lsqSquashedLoads; 985 } 986 987 if (isLoadBlocked) { 988 if (squashed_num < blockedLoadSeqNum) { 989 isLoadBlocked = false; 990 loadBlockedHandled = false; 991 blockedLoadSeqNum = 0; 992 } 993 } 994 995 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 996 memDepViolator = NULL; 997 } 998 999 int store_idx = storeTail; 1000 decrStIdx(store_idx); 1001 1002 while (stores != 0 && 1003 storeQueue[store_idx].inst->seqNum > squashed_num) { 1004 // Instructions marked as can WB are already committed. 1005 if (storeQueue[store_idx].canWB) { 1006 break; 1007 } 1008 1009 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 1010 "idx:%i [sn:%lli]\n", 1011 storeQueue[store_idx].inst->pcState(), 1012 store_idx, storeQueue[store_idx].inst->seqNum); 1013 1014 // I don't think this can happen. It should have been cleared 1015 // by the stalling load. 1016 if (isStalled() && 1017 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1018 panic("Is stalled should have been cleared by stalling load!\n"); 1019 stalled = false; 1020 stallingStoreIsn = 0; 1021 } 1022 1023 // Clear the smart pointer to make sure it is decremented. 1024 storeQueue[store_idx].inst->setSquashed(); 1025 storeQueue[store_idx].inst = NULL; 1026 storeQueue[store_idx].canWB = 0; 1027 1028 // Must delete request now that it wasn't handed off to 1029 // memory. This is quite ugly. @todo: Figure out the proper 1030 // place to really handle request deletes. 1031 delete storeQueue[store_idx].req; 1032 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 1033 delete storeQueue[store_idx].sreqLow; 1034 delete storeQueue[store_idx].sreqHigh; 1035 1036 storeQueue[store_idx].sreqLow = NULL; 1037 storeQueue[store_idx].sreqHigh = NULL; 1038 } 1039 1040 storeQueue[store_idx].req = NULL; 1041 --stores; 1042 1043 // Inefficient! 1044 storeTail = store_idx; 1045 1046 decrStIdx(store_idx); 1047 ++lsqSquashedStores; 1048 } 1049} 1050 1051template <class Impl> 1052void 1053LSQUnit<Impl>::storePostSend(PacketPtr pkt) 1054{ 1055 if (isStalled() && 1056 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 1057 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1058 "load idx:%i\n", 1059 stallingStoreIsn, stallingLoadIdx); 1060 stalled = false; 1061 stallingStoreIsn = 0; 1062 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1063 } 1064 1065 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 1066 // The store is basically completed at this time. This 1067 // only works so long as the checker doesn't try to 1068 // verify the value in memory for stores. 1069 storeQueue[storeWBIdx].inst->setCompleted(); 1070 1071 if (cpu->checker) { 1072 cpu->checker->verify(storeQueue[storeWBIdx].inst); 1073 } 1074 } 1075 1076 if (needsTSO) { 1077 storeInFlight = true; 1078 } 1079 1080 incrStIdx(storeWBIdx); 1081} 1082 1083template <class Impl> 1084void 1085LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 1086{ 1087 iewStage->wakeCPU(); 1088 1089 // Squashed instructions do not need to complete their access. 1090 if (inst->isSquashed()) { 1091 iewStage->decrWb(inst->seqNum); 1092 assert(!inst->isStore()); 1093 ++lsqIgnoredResponses; 1094 return; 1095 } 1096 1097 if (!inst->isExecuted()) { 1098 inst->setExecuted(); 1099 1100 // Complete access to copy data to proper place. 1101 inst->completeAcc(pkt); 1102 } 1103 1104 // Need to insert instruction into queue to commit 1105 iewStage->instToCommit(inst); 1106 1107 iewStage->activityThisCycle(); 1108 1109 // see if this load changed the PC 1110 iewStage->checkMisprediction(inst); 1111} 1112 1113template <class Impl> 1114void 1115LSQUnit<Impl>::completeStore(int store_idx) 1116{ 1117 assert(storeQueue[store_idx].inst); 1118 storeQueue[store_idx].completed = true; 1119 --storesToWB; 1120 // A bit conservative because a store completion may not free up entries, 1121 // but hopefully avoids two store completions in one cycle from making 1122 // the CPU tick twice. 1123 cpu->wakeCPU(); 1124 cpu->activityThisCycle(); 1125 1126 if (store_idx == storeHead) { 1127 do { 1128 incrStIdx(storeHead); 1129 1130 --stores; 1131 } while (storeQueue[storeHead].completed && 1132 storeHead != storeTail); 1133 1134 iewStage->updateLSQNextCycle = true; 1135 } 1136 1137 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 1138 "idx:%i\n", 1139 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 1140 1141#if TRACING_ON 1142 if (DTRACE(O3PipeView)) { 1143 storeQueue[store_idx].inst->storeTick = 1144 curTick() - storeQueue[store_idx].inst->fetchTick; 1145 } 1146#endif 1147 1148 if (isStalled() && 1149 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1150 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1151 "load idx:%i\n", 1152 stallingStoreIsn, stallingLoadIdx); 1153 stalled = false; 1154 stallingStoreIsn = 0; 1155 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1156 } 1157 1158 storeQueue[store_idx].inst->setCompleted(); 1159 1160 if (needsTSO) { 1161 storeInFlight = false; 1162 } 1163 1164 // Tell the checker we've completed this instruction. Some stores 1165 // may get reported twice to the checker, but the checker can 1166 // handle that case. 1167 if (cpu->checker) { 1168 cpu->checker->verify(storeQueue[store_idx].inst); 1169 } 1170} 1171 1172template <class Impl> 1173bool 1174LSQUnit<Impl>::sendStore(PacketPtr data_pkt) 1175{ 1176 if (!dcachePort->sendTimingReq(data_pkt)) { 1177 // Need to handle becoming blocked on a store. 1178 isStoreBlocked = true; 1179 ++lsqCacheBlocked; 1180 assert(retryPkt == NULL); 1181 retryPkt = data_pkt; 1182 lsq->setRetryTid(lsqID); 1183 return false; 1184 } 1185 return true; 1186} 1187 1188template <class Impl> 1189void 1190LSQUnit<Impl>::recvRetry() 1191{ 1192 if (isStoreBlocked) { 1193 DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 1194 assert(retryPkt != NULL); 1195 1196 LSQSenderState *state = 1197 dynamic_cast<LSQSenderState *>(retryPkt->senderState); 1198 1199 if (dcachePort->sendTimingReq(retryPkt)) { 1200 // Don't finish the store unless this is the last packet. 1201 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 1202 state->pendingPacket == retryPkt) { 1203 state->pktToSend = false; 1204 storePostSend(retryPkt); 1205 } 1206 retryPkt = NULL; 1207 isStoreBlocked = false; 1208 lsq->setRetryTid(InvalidThreadID); 1209 1210 // Send any outstanding packet. 1211 if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 1212 assert(state->pendingPacket); 1213 if (sendStore(state->pendingPacket)) { 1214 storePostSend(state->pendingPacket); 1215 } 1216 } 1217 } else { 1218 // Still blocked! 1219 ++lsqCacheBlocked; 1220 lsq->setRetryTid(lsqID); 1221 } 1222 } else if (isLoadBlocked) { 1223 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 1224 "no need to resend packet.\n"); 1225 } else { 1226 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 1227 } 1228} 1229 1230template <class Impl> 1231inline void 1232LSQUnit<Impl>::incrStIdx(int &store_idx) const 1233{ 1234 if (++store_idx >= SQEntries) 1235 store_idx = 0; 1236} 1237 1238template <class Impl> 1239inline void 1240LSQUnit<Impl>::decrStIdx(int &store_idx) const 1241{ 1242 if (--store_idx < 0) 1243 store_idx += SQEntries; 1244} 1245 1246template <class Impl> 1247inline void 1248LSQUnit<Impl>::incrLdIdx(int &load_idx) const 1249{ 1250 if (++load_idx >= LQEntries) 1251 load_idx = 0; 1252} 1253 1254template <class Impl> 1255inline void 1256LSQUnit<Impl>::decrLdIdx(int &load_idx) const 1257{ 1258 if (--load_idx < 0) 1259 load_idx += LQEntries; 1260} 1261 1262template <class Impl> 1263void 1264LSQUnit<Impl>::dumpInsts() const 1265{ 1266 cprintf("Load store queue: Dumping instructions.\n"); 1267 cprintf("Load queue size: %i\n", loads); 1268 cprintf("Load queue: "); 1269 1270 int load_idx = loadHead; 1271 1272 while (load_idx != loadTail && loadQueue[load_idx]) { 1273 const DynInstPtr &inst(loadQueue[load_idx]); 1274 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 1275 1276 incrLdIdx(load_idx); 1277 } 1278 cprintf("\n"); 1279 1280 cprintf("Store queue size: %i\n", stores); 1281 cprintf("Store queue: "); 1282 1283 int store_idx = storeHead; 1284 1285 while (store_idx != storeTail && storeQueue[store_idx].inst) { 1286 const DynInstPtr &inst(storeQueue[store_idx].inst); 1287 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 1288 1289 incrStIdx(store_idx); 1290 } 1291 1292 cprintf("\n"); 1293} 1294