lsq_unit_impl.hh revision 8733:64a7bf8fa56c
1/* 2 * Copyright (c) 2010-2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include "arch/generic/debugfaults.hh" 45#include "arch/locked_mem.hh" 46#include "base/str.hh" 47#include "config/the_isa.hh" 48#include "cpu/o3/lsq.hh" 49#include "cpu/o3/lsq_unit.hh" 50#include "debug/Activity.hh" 51#include "debug/IEW.hh" 52#include "debug/LSQUnit.hh" 53#include "mem/packet.hh" 54#include "mem/request.hh" 55 56#if USE_CHECKER 57#include "cpu/checker/cpu.hh" 58#endif 59 60template<class Impl> 61LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 62 LSQUnit *lsq_ptr) 63 : Event(Default_Pri, AutoDelete), 64 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 65{ 66} 67 68template<class Impl> 69void 70LSQUnit<Impl>::WritebackEvent::process() 71{ 72 if (!lsqPtr->isSwitchedOut()) { 73 lsqPtr->writeback(inst, pkt); 74 } 75 76 if (pkt->senderState) 77 delete pkt->senderState; 78 79 delete pkt->req; 80 delete pkt; 81} 82 83template<class Impl> 84const char * 85LSQUnit<Impl>::WritebackEvent::description() const 86{ 87 return "Store writeback"; 88} 89 90template<class Impl> 91void 92LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 93{ 94 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 95 DynInstPtr inst = state->inst; 96 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 97 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 98 99 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 100 101 assert(!pkt->wasNacked()); 102 103 // If this is a split access, wait until all packets are received. 104 if (TheISA::HasUnalignedMemAcc && !state->complete()) { 105 delete pkt->req; 106 delete pkt; 107 return; 108 } 109 110 if (isSwitchedOut() || inst->isSquashed()) { 111 iewStage->decrWb(inst->seqNum); 112 } else { 113 if (!state->noWB) { 114 if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 115 !state->isLoad) { 116 writeback(inst, pkt); 117 } else { 118 writeback(inst, state->mainPkt); 119 } 120 } 121 122 if (inst->isStore()) { 123 completeStore(state->idx); 124 } 125 } 126 127 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 128 delete state->mainPkt->req; 129 delete state->mainPkt; 130 } 131 delete state; 132 delete pkt->req; 133 delete pkt; 134} 135 136template <class Impl> 137LSQUnit<Impl>::LSQUnit() 138 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 139 isStoreBlocked(false), isLoadBlocked(false), 140 loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false) 141{ 142} 143 144template<class Impl> 145void 146LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 147 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 148 unsigned id) 149{ 150 cpu = cpu_ptr; 151 iewStage = iew_ptr; 152 153 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 154 155 switchedOut = false; 156 157 cacheBlockMask = 0; 158 159 lsq = lsq_ptr; 160 161 lsqID = id; 162 163 // Add 1 for the sentinel entry (they are circular queues). 164 LQEntries = maxLQEntries + 1; 165 SQEntries = maxSQEntries + 1; 166 167 loadQueue.resize(LQEntries); 168 storeQueue.resize(SQEntries); 169 170 depCheckShift = params->LSQDepCheckShift; 171 checkLoads = params->LSQCheckLoads; 172 173 loadHead = loadTail = 0; 174 175 storeHead = storeWBIdx = storeTail = 0; 176 177 usedPorts = 0; 178 cachePorts = params->cachePorts; 179 180 retryPkt = NULL; 181 memDepViolator = NULL; 182 183 blockedLoadSeqNum = 0; 184 needsTSO = params->needsTSO; 185} 186 187template<class Impl> 188std::string 189LSQUnit<Impl>::name() const 190{ 191 if (Impl::MaxThreads == 1) { 192 return iewStage->name() + ".lsq"; 193 } else { 194 return iewStage->name() + ".lsq.thread" + to_string(lsqID); 195 } 196} 197 198template<class Impl> 199void 200LSQUnit<Impl>::regStats() 201{ 202 lsqForwLoads 203 .name(name() + ".forwLoads") 204 .desc("Number of loads that had data forwarded from stores"); 205 206 invAddrLoads 207 .name(name() + ".invAddrLoads") 208 .desc("Number of loads ignored due to an invalid address"); 209 210 lsqSquashedLoads 211 .name(name() + ".squashedLoads") 212 .desc("Number of loads squashed"); 213 214 lsqIgnoredResponses 215 .name(name() + ".ignoredResponses") 216 .desc("Number of memory responses ignored because the instruction is squashed"); 217 218 lsqMemOrderViolation 219 .name(name() + ".memOrderViolation") 220 .desc("Number of memory ordering violations"); 221 222 lsqSquashedStores 223 .name(name() + ".squashedStores") 224 .desc("Number of stores squashed"); 225 226 invAddrSwpfs 227 .name(name() + ".invAddrSwpfs") 228 .desc("Number of software prefetches ignored due to an invalid address"); 229 230 lsqBlockedLoads 231 .name(name() + ".blockedLoads") 232 .desc("Number of blocked loads due to partial load-store forwarding"); 233 234 lsqRescheduledLoads 235 .name(name() + ".rescheduledLoads") 236 .desc("Number of loads that were rescheduled"); 237 238 lsqCacheBlocked 239 .name(name() + ".cacheBlocked") 240 .desc("Number of times an access to memory failed due to the cache being blocked"); 241} 242 243template<class Impl> 244void 245LSQUnit<Impl>::setDcachePort(Port *dcache_port) 246{ 247 dcachePort = dcache_port; 248} 249 250template<class Impl> 251void 252LSQUnit<Impl>::clearLQ() 253{ 254 loadQueue.clear(); 255} 256 257template<class Impl> 258void 259LSQUnit<Impl>::clearSQ() 260{ 261 storeQueue.clear(); 262} 263 264template<class Impl> 265void 266LSQUnit<Impl>::switchOut() 267{ 268 switchedOut = true; 269 for (int i = 0; i < loadQueue.size(); ++i) { 270 assert(!loadQueue[i]); 271 loadQueue[i] = NULL; 272 } 273 274 assert(storesToWB == 0); 275} 276 277template<class Impl> 278void 279LSQUnit<Impl>::takeOverFrom() 280{ 281 switchedOut = false; 282 loads = stores = storesToWB = 0; 283 284 loadHead = loadTail = 0; 285 286 storeHead = storeWBIdx = storeTail = 0; 287 288 usedPorts = 0; 289 290 memDepViolator = NULL; 291 292 blockedLoadSeqNum = 0; 293 294 stalled = false; 295 isLoadBlocked = false; 296 loadBlockedHandled = false; 297 298 // Just incase the memory system changed out from under us 299 cacheBlockMask = 0; 300} 301 302template<class Impl> 303void 304LSQUnit<Impl>::resizeLQ(unsigned size) 305{ 306 unsigned size_plus_sentinel = size + 1; 307 assert(size_plus_sentinel >= LQEntries); 308 309 if (size_plus_sentinel > LQEntries) { 310 while (size_plus_sentinel > loadQueue.size()) { 311 DynInstPtr dummy; 312 loadQueue.push_back(dummy); 313 LQEntries++; 314 } 315 } else { 316 LQEntries = size_plus_sentinel; 317 } 318 319} 320 321template<class Impl> 322void 323LSQUnit<Impl>::resizeSQ(unsigned size) 324{ 325 unsigned size_plus_sentinel = size + 1; 326 if (size_plus_sentinel > SQEntries) { 327 while (size_plus_sentinel > storeQueue.size()) { 328 SQEntry dummy; 329 storeQueue.push_back(dummy); 330 SQEntries++; 331 } 332 } else { 333 SQEntries = size_plus_sentinel; 334 } 335} 336 337template <class Impl> 338void 339LSQUnit<Impl>::insert(DynInstPtr &inst) 340{ 341 assert(inst->isMemRef()); 342 343 assert(inst->isLoad() || inst->isStore()); 344 345 if (inst->isLoad()) { 346 insertLoad(inst); 347 } else { 348 insertStore(inst); 349 } 350 351 inst->setInLSQ(); 352} 353 354template <class Impl> 355void 356LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 357{ 358 assert((loadTail + 1) % LQEntries != loadHead); 359 assert(loads < LQEntries); 360 361 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 362 load_inst->pcState(), loadTail, load_inst->seqNum); 363 364 load_inst->lqIdx = loadTail; 365 366 if (stores == 0) { 367 load_inst->sqIdx = -1; 368 } else { 369 load_inst->sqIdx = storeTail; 370 } 371 372 loadQueue[loadTail] = load_inst; 373 374 incrLdIdx(loadTail); 375 376 ++loads; 377} 378 379template <class Impl> 380void 381LSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 382{ 383 // Make sure it is not full before inserting an instruction. 384 assert((storeTail + 1) % SQEntries != storeHead); 385 assert(stores < SQEntries); 386 387 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 388 store_inst->pcState(), storeTail, store_inst->seqNum); 389 390 store_inst->sqIdx = storeTail; 391 store_inst->lqIdx = loadTail; 392 393 storeQueue[storeTail] = SQEntry(store_inst); 394 395 incrStIdx(storeTail); 396 397 ++stores; 398} 399 400template <class Impl> 401typename Impl::DynInstPtr 402LSQUnit<Impl>::getMemDepViolator() 403{ 404 DynInstPtr temp = memDepViolator; 405 406 memDepViolator = NULL; 407 408 return temp; 409} 410 411template <class Impl> 412unsigned 413LSQUnit<Impl>::numFreeEntries() 414{ 415 unsigned free_lq_entries = LQEntries - loads; 416 unsigned free_sq_entries = SQEntries - stores; 417 418 // Both the LQ and SQ entries have an extra dummy entry to differentiate 419 // empty/full conditions. Subtract 1 from the free entries. 420 if (free_lq_entries < free_sq_entries) { 421 return free_lq_entries - 1; 422 } else { 423 return free_sq_entries - 1; 424 } 425} 426 427template <class Impl> 428int 429LSQUnit<Impl>::numLoadsReady() 430{ 431 int load_idx = loadHead; 432 int retval = 0; 433 434 while (load_idx != loadTail) { 435 assert(loadQueue[load_idx]); 436 437 if (loadQueue[load_idx]->readyToIssue()) { 438 ++retval; 439 } 440 } 441 442 return retval; 443} 444 445template <class Impl> 446void 447LSQUnit<Impl>::checkSnoop(PacketPtr pkt) 448{ 449 int load_idx = loadHead; 450 451 if (!cacheBlockMask) { 452 assert(dcachePort); 453 Addr bs = dcachePort->peerBlockSize(); 454 455 // Make sure we actually got a size 456 assert(bs != 0); 457 458 cacheBlockMask = ~(bs - 1); 459 } 460 461 // If this is the only load in the LSQ we don't care 462 if (load_idx == loadTail) 463 return; 464 incrLdIdx(load_idx); 465 466 DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 467 Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 468 while (load_idx != loadTail) { 469 DynInstPtr ld_inst = loadQueue[load_idx]; 470 471 if (!ld_inst->effAddrValid || ld_inst->uncacheable()) { 472 incrLdIdx(load_idx); 473 continue; 474 } 475 476 Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 477 DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 478 ld_inst->seqNum, load_addr, invalidate_addr); 479 480 if (load_addr == invalidate_addr) { 481 if (ld_inst->possibleLoadViolation) { 482 DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 483 ld_inst->physEffAddr, pkt->getAddr(), ld_inst->seqNum); 484 485 // Mark the load for re-execution 486 ld_inst->fault = new ReExec; 487 } else { 488 // If a older load checks this and it's true 489 // then we might have missed the snoop 490 // in which case we need to invalidate to be sure 491 ld_inst->hitExternalSnoop = true; 492 } 493 } 494 incrLdIdx(load_idx); 495 } 496 return; 497} 498 499template <class Impl> 500Fault 501LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 502{ 503 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 504 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 505 506 /** @todo in theory you only need to check an instruction that has executed 507 * however, there isn't a good way in the pipeline at the moment to check 508 * all instructions that will execute before the store writes back. Thus, 509 * like the implementation that came before it, we're overly conservative. 510 */ 511 while (load_idx != loadTail) { 512 DynInstPtr ld_inst = loadQueue[load_idx]; 513 if (!ld_inst->effAddrValid || ld_inst->uncacheable()) { 514 incrLdIdx(load_idx); 515 continue; 516 } 517 518 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 519 Addr ld_eff_addr2 = 520 (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 521 522 if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 523 if (inst->isLoad()) { 524 // If this load is to the same block as an external snoop 525 // invalidate that we've observed then the load needs to be 526 // squashed as it could have newer data 527 if (ld_inst->hitExternalSnoop) { 528 if (!memDepViolator || 529 ld_inst->seqNum < memDepViolator->seqNum) { 530 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 531 "and [sn:%lli] at address %#x\n", 532 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 533 memDepViolator = ld_inst; 534 535 ++lsqMemOrderViolation; 536 537 return new GenericISA::M5PanicFault( 538 "Detected fault with inst [sn:%lli] and " 539 "[sn:%lli] at address %#x\n", 540 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 541 } 542 } 543 544 // Otherwise, mark the load has a possible load violation 545 // and if we see a snoop before it's commited, we need to squash 546 ld_inst->possibleLoadViolation = true; 547 DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 548 " between instructions [sn:%lli] and [sn:%lli]\n", 549 inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 550 } else { 551 // A load/store incorrectly passed this store. 552 // Check if we already have a violator, or if it's newer 553 // squash and refetch. 554 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 555 break; 556 557 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 558 "[sn:%lli] at address %#x\n", 559 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 560 memDepViolator = ld_inst; 561 562 ++lsqMemOrderViolation; 563 564 return new GenericISA::M5PanicFault("Detected fault with " 565 "inst [sn:%lli] and [sn:%lli] at address %#x\n", 566 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 567 } 568 } 569 570 incrLdIdx(load_idx); 571 } 572 return NoFault; 573} 574 575 576 577 578template <class Impl> 579Fault 580LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 581{ 582 using namespace TheISA; 583 // Execute a specific load. 584 Fault load_fault = NoFault; 585 586 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 587 inst->pcState(), inst->seqNum); 588 589 assert(!inst->isSquashed()); 590 591 load_fault = inst->initiateAcc(); 592 593 if (inst->isTranslationDelayed() && 594 load_fault == NoFault) 595 return load_fault; 596 597 // If the instruction faulted or predicated false, then we need to send it 598 // along to commit without the instruction completing. 599 if (load_fault != NoFault || inst->readPredicate() == false) { 600 // Send this instruction to commit, also make sure iew stage 601 // realizes there is activity. 602 // Mark it as executed unless it is an uncached load that 603 // needs to hit the head of commit. 604 if (inst->readPredicate() == false) 605 inst->forwardOldRegs(); 606 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 607 inst->seqNum, 608 (load_fault != NoFault ? "fault" : "predication")); 609 if (!(inst->hasRequest() && inst->uncacheable()) || 610 inst->isAtCommit()) { 611 inst->setExecuted(); 612 } 613 iewStage->instToCommit(inst); 614 iewStage->activityThisCycle(); 615 } else if (!loadBlocked()) { 616 assert(inst->effAddrValid); 617 int load_idx = inst->lqIdx; 618 incrLdIdx(load_idx); 619 620 if (checkLoads) 621 return checkViolations(load_idx, inst); 622 } 623 624 return load_fault; 625} 626 627template <class Impl> 628Fault 629LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 630{ 631 using namespace TheISA; 632 // Make sure that a store exists. 633 assert(stores != 0); 634 635 int store_idx = store_inst->sqIdx; 636 637 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 638 store_inst->pcState(), store_inst->seqNum); 639 640 assert(!store_inst->isSquashed()); 641 642 // Check the recently completed loads to see if any match this store's 643 // address. If so, then we have a memory ordering violation. 644 int load_idx = store_inst->lqIdx; 645 646 Fault store_fault = store_inst->initiateAcc(); 647 648 if (store_inst->isTranslationDelayed() && 649 store_fault == NoFault) 650 return store_fault; 651 652 if (store_inst->readPredicate() == false) 653 store_inst->forwardOldRegs(); 654 655 if (storeQueue[store_idx].size == 0) { 656 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 657 store_inst->pcState(), store_inst->seqNum); 658 659 return store_fault; 660 } else if (store_inst->readPredicate() == false) { 661 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 662 store_inst->seqNum); 663 return store_fault; 664 } 665 666 assert(store_fault == NoFault); 667 668 if (store_inst->isStoreConditional()) { 669 // Store conditionals need to set themselves as able to 670 // writeback if we haven't had a fault by here. 671 storeQueue[store_idx].canWB = true; 672 673 ++storesToWB; 674 } 675 676 return checkViolations(load_idx, store_inst); 677 678} 679 680template <class Impl> 681void 682LSQUnit<Impl>::commitLoad() 683{ 684 assert(loadQueue[loadHead]); 685 686 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 687 loadQueue[loadHead]->pcState()); 688 689 loadQueue[loadHead] = NULL; 690 691 incrLdIdx(loadHead); 692 693 --loads; 694} 695 696template <class Impl> 697void 698LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 699{ 700 assert(loads == 0 || loadQueue[loadHead]); 701 702 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 703 commitLoad(); 704 } 705} 706 707template <class Impl> 708void 709LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 710{ 711 assert(stores == 0 || storeQueue[storeHead].inst); 712 713 int store_idx = storeHead; 714 715 while (store_idx != storeTail) { 716 assert(storeQueue[store_idx].inst); 717 // Mark any stores that are now committed and have not yet 718 // been marked as able to write back. 719 if (!storeQueue[store_idx].canWB) { 720 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 721 break; 722 } 723 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 724 "%s [sn:%lli]\n", 725 storeQueue[store_idx].inst->pcState(), 726 storeQueue[store_idx].inst->seqNum); 727 728 storeQueue[store_idx].canWB = true; 729 730 ++storesToWB; 731 } 732 733 incrStIdx(store_idx); 734 } 735} 736 737template <class Impl> 738void 739LSQUnit<Impl>::writebackPendingStore() 740{ 741 if (hasPendingPkt) { 742 assert(pendingPkt != NULL); 743 744 // If the cache is blocked, this will store the packet for retry. 745 if (sendStore(pendingPkt)) { 746 storePostSend(pendingPkt); 747 } 748 pendingPkt = NULL; 749 hasPendingPkt = false; 750 } 751} 752 753template <class Impl> 754void 755LSQUnit<Impl>::writebackStores() 756{ 757 // First writeback the second packet from any split store that didn't 758 // complete last cycle because there weren't enough cache ports available. 759 if (TheISA::HasUnalignedMemAcc) { 760 writebackPendingStore(); 761 } 762 763 while (storesToWB > 0 && 764 storeWBIdx != storeTail && 765 storeQueue[storeWBIdx].inst && 766 storeQueue[storeWBIdx].canWB && 767 ((!needsTSO) || (!storeInFlight)) && 768 usedPorts < cachePorts) { 769 770 if (isStoreBlocked || lsq->cacheBlocked()) { 771 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 772 " is blocked!\n"); 773 break; 774 } 775 776 // Store didn't write any data so no need to write it back to 777 // memory. 778 if (storeQueue[storeWBIdx].size == 0) { 779 completeStore(storeWBIdx); 780 781 incrStIdx(storeWBIdx); 782 783 continue; 784 } 785 786 ++usedPorts; 787 788 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 789 incrStIdx(storeWBIdx); 790 791 continue; 792 } 793 794 assert(storeQueue[storeWBIdx].req); 795 assert(!storeQueue[storeWBIdx].committed); 796 797 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 798 assert(storeQueue[storeWBIdx].sreqLow); 799 assert(storeQueue[storeWBIdx].sreqHigh); 800 } 801 802 DynInstPtr inst = storeQueue[storeWBIdx].inst; 803 804 Request *req = storeQueue[storeWBIdx].req; 805 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 806 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 807 808 storeQueue[storeWBIdx].committed = true; 809 810 assert(!inst->memData); 811 inst->memData = new uint8_t[64]; 812 813 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 814 815 MemCmd command = 816 req->isSwap() ? MemCmd::SwapReq : 817 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 818 PacketPtr data_pkt; 819 PacketPtr snd_data_pkt = NULL; 820 821 LSQSenderState *state = new LSQSenderState; 822 state->isLoad = false; 823 state->idx = storeWBIdx; 824 state->inst = inst; 825 826 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 827 828 // Build a single data packet if the store isn't split. 829 data_pkt = new Packet(req, command, Packet::Broadcast); 830 data_pkt->dataStatic(inst->memData); 831 data_pkt->senderState = state; 832 } else { 833 // Create two packets if the store is split in two. 834 data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 835 snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 836 837 data_pkt->dataStatic(inst->memData); 838 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 839 840 data_pkt->senderState = state; 841 snd_data_pkt->senderState = state; 842 843 state->isSplit = true; 844 state->outstanding = 2; 845 846 // Can delete the main request now. 847 delete req; 848 req = sreqLow; 849 } 850 851 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 852 "to Addr:%#x, data:%#x [sn:%lli]\n", 853 storeWBIdx, inst->pcState(), 854 req->getPaddr(), (int)*(inst->memData), 855 inst->seqNum); 856 857 // @todo: Remove this SC hack once the memory system handles it. 858 if (inst->isStoreConditional()) { 859 assert(!storeQueue[storeWBIdx].isSplit); 860 // Disable recording the result temporarily. Writing to 861 // misc regs normally updates the result, but this is not 862 // the desired behavior when handling store conditionals. 863 inst->recordResult = false; 864 bool success = TheISA::handleLockedWrite(inst.get(), req); 865 inst->recordResult = true; 866 867 if (!success) { 868 // Instantly complete this store. 869 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 870 "Instantly completing it.\n", 871 inst->seqNum); 872 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 873 cpu->schedule(wb, curTick() + 1); 874#if USE_CHECKER 875 // Make sure to set the LLSC data for verification 876 inst->reqToVerify->setExtraData(0); 877 inst->completeAcc(data_pkt); 878#endif 879 completeStore(storeWBIdx); 880 incrStIdx(storeWBIdx); 881 continue; 882 } 883 } else { 884 // Non-store conditionals do not need a writeback. 885 state->noWB = true; 886 } 887 888 bool split = 889 TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 890 891 ThreadContext *thread = cpu->tcBase(lsqID); 892 893 if (req->isMmappedIpr()) { 894 assert(!inst->isStoreConditional()); 895 TheISA::handleIprWrite(thread, data_pkt); 896 delete data_pkt; 897 if (split) { 898 assert(snd_data_pkt->req->isMmappedIpr()); 899 TheISA::handleIprWrite(thread, snd_data_pkt); 900 delete snd_data_pkt; 901 delete sreqLow; 902 delete sreqHigh; 903 } 904 delete state; 905 delete req; 906 completeStore(storeWBIdx); 907 incrStIdx(storeWBIdx); 908 } else if (!sendStore(data_pkt)) { 909 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 910 "retry later\n", 911 inst->seqNum); 912 913 // Need to store the second packet, if split. 914 if (split) { 915 state->pktToSend = true; 916 state->pendingPacket = snd_data_pkt; 917 } 918 } else { 919 920 // If split, try to send the second packet too 921 if (split) { 922 assert(snd_data_pkt); 923 924 // Ensure there are enough ports to use. 925 if (usedPorts < cachePorts) { 926 ++usedPorts; 927 if (sendStore(snd_data_pkt)) { 928 storePostSend(snd_data_pkt); 929 } else { 930 DPRINTF(IEW, "D-Cache became blocked when writing" 931 " [sn:%lli] second packet, will retry later\n", 932 inst->seqNum); 933 } 934 } else { 935 936 // Store the packet for when there's free ports. 937 assert(pendingPkt == NULL); 938 pendingPkt = snd_data_pkt; 939 hasPendingPkt = true; 940 } 941 } else { 942 943 // Not a split store. 944 storePostSend(data_pkt); 945 } 946 } 947 } 948 949 // Not sure this should set it to 0. 950 usedPorts = 0; 951 952 assert(stores >= 0 && storesToWB >= 0); 953} 954 955/*template <class Impl> 956void 957LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 958{ 959 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 960 mshrSeqNums.end(), 961 seqNum); 962 963 if (mshr_it != mshrSeqNums.end()) { 964 mshrSeqNums.erase(mshr_it); 965 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 966 } 967}*/ 968 969template <class Impl> 970void 971LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 972{ 973 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 974 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 975 976 int load_idx = loadTail; 977 decrLdIdx(load_idx); 978 979 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 980 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 981 "[sn:%lli]\n", 982 loadQueue[load_idx]->pcState(), 983 loadQueue[load_idx]->seqNum); 984 985 if (isStalled() && load_idx == stallingLoadIdx) { 986 stalled = false; 987 stallingStoreIsn = 0; 988 stallingLoadIdx = 0; 989 } 990 991 // Clear the smart pointer to make sure it is decremented. 992 loadQueue[load_idx]->setSquashed(); 993 loadQueue[load_idx] = NULL; 994 --loads; 995 996 // Inefficient! 997 loadTail = load_idx; 998 999 decrLdIdx(load_idx); 1000 ++lsqSquashedLoads; 1001 } 1002 1003 if (isLoadBlocked) { 1004 if (squashed_num < blockedLoadSeqNum) { 1005 isLoadBlocked = false; 1006 loadBlockedHandled = false; 1007 blockedLoadSeqNum = 0; 1008 } 1009 } 1010 1011 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 1012 memDepViolator = NULL; 1013 } 1014 1015 int store_idx = storeTail; 1016 decrStIdx(store_idx); 1017 1018 while (stores != 0 && 1019 storeQueue[store_idx].inst->seqNum > squashed_num) { 1020 // Instructions marked as can WB are already committed. 1021 if (storeQueue[store_idx].canWB) { 1022 break; 1023 } 1024 1025 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 1026 "idx:%i [sn:%lli]\n", 1027 storeQueue[store_idx].inst->pcState(), 1028 store_idx, storeQueue[store_idx].inst->seqNum); 1029 1030 // I don't think this can happen. It should have been cleared 1031 // by the stalling load. 1032 if (isStalled() && 1033 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1034 panic("Is stalled should have been cleared by stalling load!\n"); 1035 stalled = false; 1036 stallingStoreIsn = 0; 1037 } 1038 1039 // Clear the smart pointer to make sure it is decremented. 1040 storeQueue[store_idx].inst->setSquashed(); 1041 storeQueue[store_idx].inst = NULL; 1042 storeQueue[store_idx].canWB = 0; 1043 1044 // Must delete request now that it wasn't handed off to 1045 // memory. This is quite ugly. @todo: Figure out the proper 1046 // place to really handle request deletes. 1047 delete storeQueue[store_idx].req; 1048 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 1049 delete storeQueue[store_idx].sreqLow; 1050 delete storeQueue[store_idx].sreqHigh; 1051 1052 storeQueue[store_idx].sreqLow = NULL; 1053 storeQueue[store_idx].sreqHigh = NULL; 1054 } 1055 1056 storeQueue[store_idx].req = NULL; 1057 --stores; 1058 1059 // Inefficient! 1060 storeTail = store_idx; 1061 1062 decrStIdx(store_idx); 1063 ++lsqSquashedStores; 1064 } 1065} 1066 1067template <class Impl> 1068void 1069LSQUnit<Impl>::storePostSend(PacketPtr pkt) 1070{ 1071 if (isStalled() && 1072 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 1073 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1074 "load idx:%i\n", 1075 stallingStoreIsn, stallingLoadIdx); 1076 stalled = false; 1077 stallingStoreIsn = 0; 1078 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1079 } 1080 1081 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 1082 // The store is basically completed at this time. This 1083 // only works so long as the checker doesn't try to 1084 // verify the value in memory for stores. 1085 storeQueue[storeWBIdx].inst->setCompleted(); 1086#if USE_CHECKER 1087 if (cpu->checker) { 1088 cpu->checker->verify(storeQueue[storeWBIdx].inst); 1089 } 1090#endif 1091 } 1092 1093 if (needsTSO) { 1094 storeInFlight = true; 1095 } 1096 1097 incrStIdx(storeWBIdx); 1098} 1099 1100template <class Impl> 1101void 1102LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 1103{ 1104 iewStage->wakeCPU(); 1105 1106 // Squashed instructions do not need to complete their access. 1107 if (inst->isSquashed()) { 1108 iewStage->decrWb(inst->seqNum); 1109 assert(!inst->isStore()); 1110 ++lsqIgnoredResponses; 1111 return; 1112 } 1113 1114 if (!inst->isExecuted()) { 1115 inst->setExecuted(); 1116 1117 // Complete access to copy data to proper place. 1118 inst->completeAcc(pkt); 1119 } 1120 1121 // Need to insert instruction into queue to commit 1122 iewStage->instToCommit(inst); 1123 1124 iewStage->activityThisCycle(); 1125 1126 // see if this load changed the PC 1127 iewStage->checkMisprediction(inst); 1128} 1129 1130template <class Impl> 1131void 1132LSQUnit<Impl>::completeStore(int store_idx) 1133{ 1134 assert(storeQueue[store_idx].inst); 1135 storeQueue[store_idx].completed = true; 1136 --storesToWB; 1137 // A bit conservative because a store completion may not free up entries, 1138 // but hopefully avoids two store completions in one cycle from making 1139 // the CPU tick twice. 1140 cpu->wakeCPU(); 1141 cpu->activityThisCycle(); 1142 1143 if (store_idx == storeHead) { 1144 do { 1145 incrStIdx(storeHead); 1146 1147 --stores; 1148 } while (storeQueue[storeHead].completed && 1149 storeHead != storeTail); 1150 1151 iewStage->updateLSQNextCycle = true; 1152 } 1153 1154 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 1155 "idx:%i\n", 1156 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 1157 1158 if (isStalled() && 1159 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1160 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1161 "load idx:%i\n", 1162 stallingStoreIsn, stallingLoadIdx); 1163 stalled = false; 1164 stallingStoreIsn = 0; 1165 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1166 } 1167 1168 storeQueue[store_idx].inst->setCompleted(); 1169 1170 if (needsTSO) { 1171 storeInFlight = false; 1172 } 1173 1174 // Tell the checker we've completed this instruction. Some stores 1175 // may get reported twice to the checker, but the checker can 1176 // handle that case. 1177#if USE_CHECKER 1178 if (cpu->checker) { 1179 cpu->checker->verify(storeQueue[store_idx].inst); 1180 } 1181#endif 1182} 1183 1184template <class Impl> 1185bool 1186LSQUnit<Impl>::sendStore(PacketPtr data_pkt) 1187{ 1188 if (!dcachePort->sendTiming(data_pkt)) { 1189 // Need to handle becoming blocked on a store. 1190 isStoreBlocked = true; 1191 ++lsqCacheBlocked; 1192 assert(retryPkt == NULL); 1193 retryPkt = data_pkt; 1194 lsq->setRetryTid(lsqID); 1195 return false; 1196 } 1197 return true; 1198} 1199 1200template <class Impl> 1201void 1202LSQUnit<Impl>::recvRetry() 1203{ 1204 if (isStoreBlocked) { 1205 DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 1206 assert(retryPkt != NULL); 1207 1208 LSQSenderState *state = 1209 dynamic_cast<LSQSenderState *>(retryPkt->senderState); 1210 1211 if (dcachePort->sendTiming(retryPkt)) { 1212 // Don't finish the store unless this is the last packet. 1213 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 1214 state->pendingPacket == retryPkt) { 1215 state->pktToSend = false; 1216 storePostSend(retryPkt); 1217 } 1218 retryPkt = NULL; 1219 isStoreBlocked = false; 1220 lsq->setRetryTid(InvalidThreadID); 1221 1222 // Send any outstanding packet. 1223 if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 1224 assert(state->pendingPacket); 1225 if (sendStore(state->pendingPacket)) { 1226 storePostSend(state->pendingPacket); 1227 } 1228 } 1229 } else { 1230 // Still blocked! 1231 ++lsqCacheBlocked; 1232 lsq->setRetryTid(lsqID); 1233 } 1234 } else if (isLoadBlocked) { 1235 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 1236 "no need to resend packet.\n"); 1237 } else { 1238 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 1239 } 1240} 1241 1242template <class Impl> 1243inline void 1244LSQUnit<Impl>::incrStIdx(int &store_idx) 1245{ 1246 if (++store_idx >= SQEntries) 1247 store_idx = 0; 1248} 1249 1250template <class Impl> 1251inline void 1252LSQUnit<Impl>::decrStIdx(int &store_idx) 1253{ 1254 if (--store_idx < 0) 1255 store_idx += SQEntries; 1256} 1257 1258template <class Impl> 1259inline void 1260LSQUnit<Impl>::incrLdIdx(int &load_idx) 1261{ 1262 if (++load_idx >= LQEntries) 1263 load_idx = 0; 1264} 1265 1266template <class Impl> 1267inline void 1268LSQUnit<Impl>::decrLdIdx(int &load_idx) 1269{ 1270 if (--load_idx < 0) 1271 load_idx += LQEntries; 1272} 1273 1274template <class Impl> 1275void 1276LSQUnit<Impl>::dumpInsts() 1277{ 1278 cprintf("Load store queue: Dumping instructions.\n"); 1279 cprintf("Load queue size: %i\n", loads); 1280 cprintf("Load queue: "); 1281 1282 int load_idx = loadHead; 1283 1284 while (load_idx != loadTail && loadQueue[load_idx]) { 1285 cprintf("%s ", loadQueue[load_idx]->pcState()); 1286 1287 incrLdIdx(load_idx); 1288 } 1289 1290 cprintf("Store queue size: %i\n", stores); 1291 cprintf("Store queue: "); 1292 1293 int store_idx = storeHead; 1294 1295 while (store_idx != storeTail && storeQueue[store_idx].inst) { 1296 cprintf("%s ", storeQueue[store_idx].inst->pcState()); 1297 1298 incrStIdx(store_idx); 1299 } 1300 1301 cprintf("\n"); 1302} 1303