lsq_unit_impl.hh revision 8229
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include "arch/locked_mem.hh" 45#include "base/str.hh" 46#include "config/the_isa.hh" 47#include "config/use_checker.hh" 48#include "cpu/o3/lsq.hh" 49#include "cpu/o3/lsq_unit.hh" 50#include "mem/packet.hh" 51#include "mem/request.hh" 52 53#if USE_CHECKER 54#include "cpu/checker/cpu.hh" 55#endif 56 57template<class Impl> 58LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 59 LSQUnit *lsq_ptr) 60 : inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 61{ 62 this->setFlags(Event::AutoDelete); 63} 64 65template<class Impl> 66void 67LSQUnit<Impl>::WritebackEvent::process() 68{ 69 if (!lsqPtr->isSwitchedOut()) { 70 lsqPtr->writeback(inst, pkt); 71 } 72 73 if (pkt->senderState) 74 delete pkt->senderState; 75 76 delete pkt->req; 77 delete pkt; 78} 79 80template<class Impl> 81const char * 82LSQUnit<Impl>::WritebackEvent::description() const 83{ 84 return "Store writeback"; 85} 86 87template<class Impl> 88void 89LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 90{ 91 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 92 DynInstPtr inst = state->inst; 93 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 94 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 95 96 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 97 98 assert(!pkt->wasNacked()); 99 100 // If this is a split access, wait until all packets are received. 101 if (TheISA::HasUnalignedMemAcc && !state->complete()) { 102 delete pkt->req; 103 delete pkt; 104 return; 105 } 106 107 if (isSwitchedOut() || inst->isSquashed()) { 108 iewStage->decrWb(inst->seqNum); 109 } else { 110 if (!state->noWB) { 111 if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 112 !state->isLoad) { 113 writeback(inst, pkt); 114 } else { 115 writeback(inst, state->mainPkt); 116 } 117 } 118 119 if (inst->isStore()) { 120 completeStore(state->idx); 121 } 122 } 123 124 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 125 delete state->mainPkt->req; 126 delete state->mainPkt; 127 } 128 delete state; 129 delete pkt->req; 130 delete pkt; 131} 132 133template <class Impl> 134LSQUnit<Impl>::LSQUnit() 135 : loads(0), stores(0), storesToWB(0), stalled(false), 136 isStoreBlocked(false), isLoadBlocked(false), 137 loadBlockedHandled(false), hasPendingPkt(false) 138{ 139} 140 141template<class Impl> 142void 143LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 144 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 145 unsigned id) 146{ 147 cpu = cpu_ptr; 148 iewStage = iew_ptr; 149 150 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 151 152 switchedOut = false; 153 154 lsq = lsq_ptr; 155 156 lsqID = id; 157 158 // Add 1 for the sentinel entry (they are circular queues). 159 LQEntries = maxLQEntries + 1; 160 SQEntries = maxSQEntries + 1; 161 162 loadQueue.resize(LQEntries); 163 storeQueue.resize(SQEntries); 164 165 depCheckShift = params->LSQDepCheckShift; 166 checkLoads = params->LSQCheckLoads; 167 168 loadHead = loadTail = 0; 169 170 storeHead = storeWBIdx = storeTail = 0; 171 172 usedPorts = 0; 173 cachePorts = params->cachePorts; 174 175 retryPkt = NULL; 176 memDepViolator = NULL; 177 178 blockedLoadSeqNum = 0; 179} 180 181template<class Impl> 182std::string 183LSQUnit<Impl>::name() const 184{ 185 if (Impl::MaxThreads == 1) { 186 return iewStage->name() + ".lsq"; 187 } else { 188 return iewStage->name() + ".lsq.thread." + to_string(lsqID); 189 } 190} 191 192template<class Impl> 193void 194LSQUnit<Impl>::regStats() 195{ 196 lsqForwLoads 197 .name(name() + ".forwLoads") 198 .desc("Number of loads that had data forwarded from stores"); 199 200 invAddrLoads 201 .name(name() + ".invAddrLoads") 202 .desc("Number of loads ignored due to an invalid address"); 203 204 lsqSquashedLoads 205 .name(name() + ".squashedLoads") 206 .desc("Number of loads squashed"); 207 208 lsqIgnoredResponses 209 .name(name() + ".ignoredResponses") 210 .desc("Number of memory responses ignored because the instruction is squashed"); 211 212 lsqMemOrderViolation 213 .name(name() + ".memOrderViolation") 214 .desc("Number of memory ordering violations"); 215 216 lsqSquashedStores 217 .name(name() + ".squashedStores") 218 .desc("Number of stores squashed"); 219 220 invAddrSwpfs 221 .name(name() + ".invAddrSwpfs") 222 .desc("Number of software prefetches ignored due to an invalid address"); 223 224 lsqBlockedLoads 225 .name(name() + ".blockedLoads") 226 .desc("Number of blocked loads due to partial load-store forwarding"); 227 228 lsqRescheduledLoads 229 .name(name() + ".rescheduledLoads") 230 .desc("Number of loads that were rescheduled"); 231 232 lsqCacheBlocked 233 .name(name() + ".cacheBlocked") 234 .desc("Number of times an access to memory failed due to the cache being blocked"); 235} 236 237template<class Impl> 238void 239LSQUnit<Impl>::setDcachePort(Port *dcache_port) 240{ 241 dcachePort = dcache_port; 242 243#if USE_CHECKER 244 if (cpu->checker) { 245 cpu->checker->setDcachePort(dcachePort); 246 } 247#endif 248} 249 250template<class Impl> 251void 252LSQUnit<Impl>::clearLQ() 253{ 254 loadQueue.clear(); 255} 256 257template<class Impl> 258void 259LSQUnit<Impl>::clearSQ() 260{ 261 storeQueue.clear(); 262} 263 264template<class Impl> 265void 266LSQUnit<Impl>::switchOut() 267{ 268 switchedOut = true; 269 for (int i = 0; i < loadQueue.size(); ++i) { 270 assert(!loadQueue[i]); 271 loadQueue[i] = NULL; 272 } 273 274 assert(storesToWB == 0); 275} 276 277template<class Impl> 278void 279LSQUnit<Impl>::takeOverFrom() 280{ 281 switchedOut = false; 282 loads = stores = storesToWB = 0; 283 284 loadHead = loadTail = 0; 285 286 storeHead = storeWBIdx = storeTail = 0; 287 288 usedPorts = 0; 289 290 memDepViolator = NULL; 291 292 blockedLoadSeqNum = 0; 293 294 stalled = false; 295 isLoadBlocked = false; 296 loadBlockedHandled = false; 297} 298 299template<class Impl> 300void 301LSQUnit<Impl>::resizeLQ(unsigned size) 302{ 303 unsigned size_plus_sentinel = size + 1; 304 assert(size_plus_sentinel >= LQEntries); 305 306 if (size_plus_sentinel > LQEntries) { 307 while (size_plus_sentinel > loadQueue.size()) { 308 DynInstPtr dummy; 309 loadQueue.push_back(dummy); 310 LQEntries++; 311 } 312 } else { 313 LQEntries = size_plus_sentinel; 314 } 315 316} 317 318template<class Impl> 319void 320LSQUnit<Impl>::resizeSQ(unsigned size) 321{ 322 unsigned size_plus_sentinel = size + 1; 323 if (size_plus_sentinel > SQEntries) { 324 while (size_plus_sentinel > storeQueue.size()) { 325 SQEntry dummy; 326 storeQueue.push_back(dummy); 327 SQEntries++; 328 } 329 } else { 330 SQEntries = size_plus_sentinel; 331 } 332} 333 334template <class Impl> 335void 336LSQUnit<Impl>::insert(DynInstPtr &inst) 337{ 338 assert(inst->isMemRef()); 339 340 assert(inst->isLoad() || inst->isStore()); 341 342 if (inst->isLoad()) { 343 insertLoad(inst); 344 } else { 345 insertStore(inst); 346 } 347 348 inst->setInLSQ(); 349} 350 351template <class Impl> 352void 353LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 354{ 355 assert((loadTail + 1) % LQEntries != loadHead); 356 assert(loads < LQEntries); 357 358 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 359 load_inst->pcState(), loadTail, load_inst->seqNum); 360 361 load_inst->lqIdx = loadTail; 362 363 if (stores == 0) { 364 load_inst->sqIdx = -1; 365 } else { 366 load_inst->sqIdx = storeTail; 367 } 368 369 loadQueue[loadTail] = load_inst; 370 371 incrLdIdx(loadTail); 372 373 ++loads; 374} 375 376template <class Impl> 377void 378LSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 379{ 380 // Make sure it is not full before inserting an instruction. 381 assert((storeTail + 1) % SQEntries != storeHead); 382 assert(stores < SQEntries); 383 384 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 385 store_inst->pcState(), storeTail, store_inst->seqNum); 386 387 store_inst->sqIdx = storeTail; 388 store_inst->lqIdx = loadTail; 389 390 storeQueue[storeTail] = SQEntry(store_inst); 391 392 incrStIdx(storeTail); 393 394 ++stores; 395} 396 397template <class Impl> 398typename Impl::DynInstPtr 399LSQUnit<Impl>::getMemDepViolator() 400{ 401 DynInstPtr temp = memDepViolator; 402 403 memDepViolator = NULL; 404 405 return temp; 406} 407 408template <class Impl> 409unsigned 410LSQUnit<Impl>::numFreeEntries() 411{ 412 unsigned free_lq_entries = LQEntries - loads; 413 unsigned free_sq_entries = SQEntries - stores; 414 415 // Both the LQ and SQ entries have an extra dummy entry to differentiate 416 // empty/full conditions. Subtract 1 from the free entries. 417 if (free_lq_entries < free_sq_entries) { 418 return free_lq_entries - 1; 419 } else { 420 return free_sq_entries - 1; 421 } 422} 423 424template <class Impl> 425int 426LSQUnit<Impl>::numLoadsReady() 427{ 428 int load_idx = loadHead; 429 int retval = 0; 430 431 while (load_idx != loadTail) { 432 assert(loadQueue[load_idx]); 433 434 if (loadQueue[load_idx]->readyToIssue()) { 435 ++retval; 436 } 437 } 438 439 return retval; 440} 441 442template <class Impl> 443Fault 444LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 445{ 446 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 447 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 448 449 /** @todo in theory you only need to check an instruction that has executed 450 * however, there isn't a good way in the pipeline at the moment to check 451 * all instructions that will execute before the store writes back. Thus, 452 * like the implementation that came before it, we're overly conservative. 453 */ 454 while (load_idx != loadTail) { 455 DynInstPtr ld_inst = loadQueue[load_idx]; 456 if (!ld_inst->effAddrValid || ld_inst->uncacheable()) { 457 incrLdIdx(load_idx); 458 continue; 459 } 460 461 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 462 Addr ld_eff_addr2 = 463 (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 464 465 if ((inst_eff_addr2 > ld_eff_addr1 && inst_eff_addr1 < ld_eff_addr2) || 466 inst_eff_addr1 == ld_eff_addr1) { 467 // A load/store incorrectly passed this load/store. 468 // Check if we already have a violator, or if it's newer 469 // squash and refetch. 470 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 471 break; 472 473 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and [sn:%lli]" 474 " at address %#x\n", inst->seqNum, ld_inst->seqNum, 475 ld_eff_addr1); 476 memDepViolator = ld_inst; 477 478 ++lsqMemOrderViolation; 479 480 return TheISA::genMachineCheckFault(); 481 } 482 483 incrLdIdx(load_idx); 484 } 485 return NoFault; 486} 487 488 489 490 491template <class Impl> 492Fault 493LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 494{ 495 using namespace TheISA; 496 // Execute a specific load. 497 Fault load_fault = NoFault; 498 499 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 500 inst->pcState(), inst->seqNum); 501 502 assert(!inst->isSquashed()); 503 504 load_fault = inst->initiateAcc(); 505 506 if (inst->isTranslationDelayed() && 507 load_fault == NoFault) 508 return load_fault; 509 510 // If the instruction faulted or predicated false, then we need to send it 511 // along to commit without the instruction completing. 512 if (load_fault != NoFault || inst->readPredicate() == false) { 513 // Send this instruction to commit, also make sure iew stage 514 // realizes there is activity. 515 // Mark it as executed unless it is an uncached load that 516 // needs to hit the head of commit. 517 if (inst->readPredicate() == false) 518 inst->forwardOldRegs(); 519 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 520 inst->seqNum, 521 (load_fault != NoFault ? "fault" : "predication")); 522 if (!(inst->hasRequest() && inst->uncacheable()) || 523 inst->isAtCommit()) { 524 inst->setExecuted(); 525 } 526 iewStage->instToCommit(inst); 527 iewStage->activityThisCycle(); 528 } else if (!loadBlocked()) { 529 assert(inst->effAddrValid); 530 int load_idx = inst->lqIdx; 531 incrLdIdx(load_idx); 532 533 if (checkLoads) 534 return checkViolations(load_idx, inst); 535 } 536 537 return load_fault; 538} 539 540template <class Impl> 541Fault 542LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 543{ 544 using namespace TheISA; 545 // Make sure that a store exists. 546 assert(stores != 0); 547 548 int store_idx = store_inst->sqIdx; 549 550 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 551 store_inst->pcState(), store_inst->seqNum); 552 553 assert(!store_inst->isSquashed()); 554 555 // Check the recently completed loads to see if any match this store's 556 // address. If so, then we have a memory ordering violation. 557 int load_idx = store_inst->lqIdx; 558 559 Fault store_fault = store_inst->initiateAcc(); 560 561 if (store_inst->isTranslationDelayed() && 562 store_fault == NoFault) 563 return store_fault; 564 565 if (store_inst->readPredicate() == false) 566 store_inst->forwardOldRegs(); 567 568 if (storeQueue[store_idx].size == 0) { 569 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 570 store_inst->pcState(), store_inst->seqNum); 571 572 return store_fault; 573 } else if (store_inst->readPredicate() == false) { 574 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 575 store_inst->seqNum); 576 return store_fault; 577 } 578 579 assert(store_fault == NoFault); 580 581 if (store_inst->isStoreConditional()) { 582 // Store conditionals need to set themselves as able to 583 // writeback if we haven't had a fault by here. 584 storeQueue[store_idx].canWB = true; 585 586 ++storesToWB; 587 } 588 589 return checkViolations(load_idx, store_inst); 590 591} 592 593template <class Impl> 594void 595LSQUnit<Impl>::commitLoad() 596{ 597 assert(loadQueue[loadHead]); 598 599 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 600 loadQueue[loadHead]->pcState()); 601 602 loadQueue[loadHead] = NULL; 603 604 incrLdIdx(loadHead); 605 606 --loads; 607} 608 609template <class Impl> 610void 611LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 612{ 613 assert(loads == 0 || loadQueue[loadHead]); 614 615 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 616 commitLoad(); 617 } 618} 619 620template <class Impl> 621void 622LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 623{ 624 assert(stores == 0 || storeQueue[storeHead].inst); 625 626 int store_idx = storeHead; 627 628 while (store_idx != storeTail) { 629 assert(storeQueue[store_idx].inst); 630 // Mark any stores that are now committed and have not yet 631 // been marked as able to write back. 632 if (!storeQueue[store_idx].canWB) { 633 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 634 break; 635 } 636 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 637 "%s [sn:%lli]\n", 638 storeQueue[store_idx].inst->pcState(), 639 storeQueue[store_idx].inst->seqNum); 640 641 storeQueue[store_idx].canWB = true; 642 643 ++storesToWB; 644 } 645 646 incrStIdx(store_idx); 647 } 648} 649 650template <class Impl> 651void 652LSQUnit<Impl>::writebackPendingStore() 653{ 654 if (hasPendingPkt) { 655 assert(pendingPkt != NULL); 656 657 // If the cache is blocked, this will store the packet for retry. 658 if (sendStore(pendingPkt)) { 659 storePostSend(pendingPkt); 660 } 661 pendingPkt = NULL; 662 hasPendingPkt = false; 663 } 664} 665 666template <class Impl> 667void 668LSQUnit<Impl>::writebackStores() 669{ 670 // First writeback the second packet from any split store that didn't 671 // complete last cycle because there weren't enough cache ports available. 672 if (TheISA::HasUnalignedMemAcc) { 673 writebackPendingStore(); 674 } 675 676 while (storesToWB > 0 && 677 storeWBIdx != storeTail && 678 storeQueue[storeWBIdx].inst && 679 storeQueue[storeWBIdx].canWB && 680 usedPorts < cachePorts) { 681 682 if (isStoreBlocked || lsq->cacheBlocked()) { 683 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 684 " is blocked!\n"); 685 break; 686 } 687 688 // Store didn't write any data so no need to write it back to 689 // memory. 690 if (storeQueue[storeWBIdx].size == 0) { 691 completeStore(storeWBIdx); 692 693 incrStIdx(storeWBIdx); 694 695 continue; 696 } 697 698 ++usedPorts; 699 700 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 701 incrStIdx(storeWBIdx); 702 703 continue; 704 } 705 706 assert(storeQueue[storeWBIdx].req); 707 assert(!storeQueue[storeWBIdx].committed); 708 709 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 710 assert(storeQueue[storeWBIdx].sreqLow); 711 assert(storeQueue[storeWBIdx].sreqHigh); 712 } 713 714 DynInstPtr inst = storeQueue[storeWBIdx].inst; 715 716 Request *req = storeQueue[storeWBIdx].req; 717 storeQueue[storeWBIdx].committed = true; 718 719 assert(!inst->memData); 720 inst->memData = new uint8_t[64]; 721 722 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 723 724 MemCmd command = 725 req->isSwap() ? MemCmd::SwapReq : 726 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 727 PacketPtr data_pkt; 728 PacketPtr snd_data_pkt = NULL; 729 730 LSQSenderState *state = new LSQSenderState; 731 state->isLoad = false; 732 state->idx = storeWBIdx; 733 state->inst = inst; 734 735 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 736 737 // Build a single data packet if the store isn't split. 738 data_pkt = new Packet(req, command, Packet::Broadcast); 739 data_pkt->dataStatic(inst->memData); 740 data_pkt->senderState = state; 741 } else { 742 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 743 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 744 745 // Create two packets if the store is split in two. 746 data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 747 snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 748 749 data_pkt->dataStatic(inst->memData); 750 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 751 752 data_pkt->senderState = state; 753 snd_data_pkt->senderState = state; 754 755 state->isSplit = true; 756 state->outstanding = 2; 757 758 // Can delete the main request now. 759 delete req; 760 req = sreqLow; 761 } 762 763 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 764 "to Addr:%#x, data:%#x [sn:%lli]\n", 765 storeWBIdx, inst->pcState(), 766 req->getPaddr(), (int)*(inst->memData), 767 inst->seqNum); 768 769 // @todo: Remove this SC hack once the memory system handles it. 770 if (inst->isStoreConditional()) { 771 assert(!storeQueue[storeWBIdx].isSplit); 772 // Disable recording the result temporarily. Writing to 773 // misc regs normally updates the result, but this is not 774 // the desired behavior when handling store conditionals. 775 inst->recordResult = false; 776 bool success = TheISA::handleLockedWrite(inst.get(), req); 777 inst->recordResult = true; 778 779 if (!success) { 780 // Instantly complete this store. 781 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 782 "Instantly completing it.\n", 783 inst->seqNum); 784 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 785 cpu->schedule(wb, curTick() + 1); 786 completeStore(storeWBIdx); 787 incrStIdx(storeWBIdx); 788 continue; 789 } 790 } else { 791 // Non-store conditionals do not need a writeback. 792 state->noWB = true; 793 } 794 795 if (!sendStore(data_pkt)) { 796 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 797 "retry later\n", 798 inst->seqNum); 799 800 // Need to store the second packet, if split. 801 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 802 state->pktToSend = true; 803 state->pendingPacket = snd_data_pkt; 804 } 805 } else { 806 807 // If split, try to send the second packet too 808 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 809 assert(snd_data_pkt); 810 811 // Ensure there are enough ports to use. 812 if (usedPorts < cachePorts) { 813 ++usedPorts; 814 if (sendStore(snd_data_pkt)) { 815 storePostSend(snd_data_pkt); 816 } else { 817 DPRINTF(IEW, "D-Cache became blocked when writing" 818 " [sn:%lli] second packet, will retry later\n", 819 inst->seqNum); 820 } 821 } else { 822 823 // Store the packet for when there's free ports. 824 assert(pendingPkt == NULL); 825 pendingPkt = snd_data_pkt; 826 hasPendingPkt = true; 827 } 828 } else { 829 830 // Not a split store. 831 storePostSend(data_pkt); 832 } 833 } 834 } 835 836 // Not sure this should set it to 0. 837 usedPorts = 0; 838 839 assert(stores >= 0 && storesToWB >= 0); 840} 841 842/*template <class Impl> 843void 844LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 845{ 846 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 847 mshrSeqNums.end(), 848 seqNum); 849 850 if (mshr_it != mshrSeqNums.end()) { 851 mshrSeqNums.erase(mshr_it); 852 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 853 } 854}*/ 855 856template <class Impl> 857void 858LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 859{ 860 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 861 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 862 863 int load_idx = loadTail; 864 decrLdIdx(load_idx); 865 866 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 867 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 868 "[sn:%lli]\n", 869 loadQueue[load_idx]->pcState(), 870 loadQueue[load_idx]->seqNum); 871 872 if (isStalled() && load_idx == stallingLoadIdx) { 873 stalled = false; 874 stallingStoreIsn = 0; 875 stallingLoadIdx = 0; 876 } 877 878 // Clear the smart pointer to make sure it is decremented. 879 loadQueue[load_idx]->setSquashed(); 880 loadQueue[load_idx] = NULL; 881 --loads; 882 883 // Inefficient! 884 loadTail = load_idx; 885 886 decrLdIdx(load_idx); 887 ++lsqSquashedLoads; 888 } 889 890 if (isLoadBlocked) { 891 if (squashed_num < blockedLoadSeqNum) { 892 isLoadBlocked = false; 893 loadBlockedHandled = false; 894 blockedLoadSeqNum = 0; 895 } 896 } 897 898 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 899 memDepViolator = NULL; 900 } 901 902 int store_idx = storeTail; 903 decrStIdx(store_idx); 904 905 while (stores != 0 && 906 storeQueue[store_idx].inst->seqNum > squashed_num) { 907 // Instructions marked as can WB are already committed. 908 if (storeQueue[store_idx].canWB) { 909 break; 910 } 911 912 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 913 "idx:%i [sn:%lli]\n", 914 storeQueue[store_idx].inst->pcState(), 915 store_idx, storeQueue[store_idx].inst->seqNum); 916 917 // I don't think this can happen. It should have been cleared 918 // by the stalling load. 919 if (isStalled() && 920 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 921 panic("Is stalled should have been cleared by stalling load!\n"); 922 stalled = false; 923 stallingStoreIsn = 0; 924 } 925 926 // Clear the smart pointer to make sure it is decremented. 927 storeQueue[store_idx].inst->setSquashed(); 928 storeQueue[store_idx].inst = NULL; 929 storeQueue[store_idx].canWB = 0; 930 931 // Must delete request now that it wasn't handed off to 932 // memory. This is quite ugly. @todo: Figure out the proper 933 // place to really handle request deletes. 934 delete storeQueue[store_idx].req; 935 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 936 delete storeQueue[store_idx].sreqLow; 937 delete storeQueue[store_idx].sreqHigh; 938 939 storeQueue[store_idx].sreqLow = NULL; 940 storeQueue[store_idx].sreqHigh = NULL; 941 } 942 943 storeQueue[store_idx].req = NULL; 944 --stores; 945 946 // Inefficient! 947 storeTail = store_idx; 948 949 decrStIdx(store_idx); 950 ++lsqSquashedStores; 951 } 952} 953 954template <class Impl> 955void 956LSQUnit<Impl>::storePostSend(PacketPtr pkt) 957{ 958 if (isStalled() && 959 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 960 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 961 "load idx:%i\n", 962 stallingStoreIsn, stallingLoadIdx); 963 stalled = false; 964 stallingStoreIsn = 0; 965 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 966 } 967 968 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 969 // The store is basically completed at this time. This 970 // only works so long as the checker doesn't try to 971 // verify the value in memory for stores. 972 storeQueue[storeWBIdx].inst->setCompleted(); 973#if USE_CHECKER 974 if (cpu->checker) { 975 cpu->checker->verify(storeQueue[storeWBIdx].inst); 976 } 977#endif 978 } 979 980 incrStIdx(storeWBIdx); 981} 982 983template <class Impl> 984void 985LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 986{ 987 iewStage->wakeCPU(); 988 989 // Squashed instructions do not need to complete their access. 990 if (inst->isSquashed()) { 991 iewStage->decrWb(inst->seqNum); 992 assert(!inst->isStore()); 993 ++lsqIgnoredResponses; 994 return; 995 } 996 997 if (!inst->isExecuted()) { 998 inst->setExecuted(); 999 1000 // Complete access to copy data to proper place. 1001 inst->completeAcc(pkt); 1002 } 1003 1004 // Need to insert instruction into queue to commit 1005 iewStage->instToCommit(inst); 1006 1007 iewStage->activityThisCycle(); 1008 1009 // see if this load changed the PC 1010 iewStage->checkMisprediction(inst); 1011} 1012 1013template <class Impl> 1014void 1015LSQUnit<Impl>::completeStore(int store_idx) 1016{ 1017 assert(storeQueue[store_idx].inst); 1018 storeQueue[store_idx].completed = true; 1019 --storesToWB; 1020 // A bit conservative because a store completion may not free up entries, 1021 // but hopefully avoids two store completions in one cycle from making 1022 // the CPU tick twice. 1023 cpu->wakeCPU(); 1024 cpu->activityThisCycle(); 1025 1026 if (store_idx == storeHead) { 1027 do { 1028 incrStIdx(storeHead); 1029 1030 --stores; 1031 } while (storeQueue[storeHead].completed && 1032 storeHead != storeTail); 1033 1034 iewStage->updateLSQNextCycle = true; 1035 } 1036 1037 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 1038 "idx:%i\n", 1039 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 1040 1041 if (isStalled() && 1042 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1043 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1044 "load idx:%i\n", 1045 stallingStoreIsn, stallingLoadIdx); 1046 stalled = false; 1047 stallingStoreIsn = 0; 1048 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1049 } 1050 1051 storeQueue[store_idx].inst->setCompleted(); 1052 1053 // Tell the checker we've completed this instruction. Some stores 1054 // may get reported twice to the checker, but the checker can 1055 // handle that case. 1056#if USE_CHECKER 1057 if (cpu->checker) { 1058 cpu->checker->verify(storeQueue[store_idx].inst); 1059 } 1060#endif 1061} 1062 1063template <class Impl> 1064bool 1065LSQUnit<Impl>::sendStore(PacketPtr data_pkt) 1066{ 1067 if (!dcachePort->sendTiming(data_pkt)) { 1068 // Need to handle becoming blocked on a store. 1069 isStoreBlocked = true; 1070 ++lsqCacheBlocked; 1071 assert(retryPkt == NULL); 1072 retryPkt = data_pkt; 1073 lsq->setRetryTid(lsqID); 1074 return false; 1075 } 1076 return true; 1077} 1078 1079template <class Impl> 1080void 1081LSQUnit<Impl>::recvRetry() 1082{ 1083 if (isStoreBlocked) { 1084 DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 1085 assert(retryPkt != NULL); 1086 1087 if (dcachePort->sendTiming(retryPkt)) { 1088 LSQSenderState *state = 1089 dynamic_cast<LSQSenderState *>(retryPkt->senderState); 1090 1091 // Don't finish the store unless this is the last packet. 1092 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 1093 state->pendingPacket == retryPkt) { 1094 state->pktToSend = false; 1095 storePostSend(retryPkt); 1096 } 1097 retryPkt = NULL; 1098 isStoreBlocked = false; 1099 lsq->setRetryTid(InvalidThreadID); 1100 1101 // Send any outstanding packet. 1102 if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 1103 assert(state->pendingPacket); 1104 if (sendStore(state->pendingPacket)) { 1105 storePostSend(state->pendingPacket); 1106 } 1107 } 1108 } else { 1109 // Still blocked! 1110 ++lsqCacheBlocked; 1111 lsq->setRetryTid(lsqID); 1112 } 1113 } else if (isLoadBlocked) { 1114 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 1115 "no need to resend packet.\n"); 1116 } else { 1117 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 1118 } 1119} 1120 1121template <class Impl> 1122inline void 1123LSQUnit<Impl>::incrStIdx(int &store_idx) 1124{ 1125 if (++store_idx >= SQEntries) 1126 store_idx = 0; 1127} 1128 1129template <class Impl> 1130inline void 1131LSQUnit<Impl>::decrStIdx(int &store_idx) 1132{ 1133 if (--store_idx < 0) 1134 store_idx += SQEntries; 1135} 1136 1137template <class Impl> 1138inline void 1139LSQUnit<Impl>::incrLdIdx(int &load_idx) 1140{ 1141 if (++load_idx >= LQEntries) 1142 load_idx = 0; 1143} 1144 1145template <class Impl> 1146inline void 1147LSQUnit<Impl>::decrLdIdx(int &load_idx) 1148{ 1149 if (--load_idx < 0) 1150 load_idx += LQEntries; 1151} 1152 1153template <class Impl> 1154void 1155LSQUnit<Impl>::dumpInsts() 1156{ 1157 cprintf("Load store queue: Dumping instructions.\n"); 1158 cprintf("Load queue size: %i\n", loads); 1159 cprintf("Load queue: "); 1160 1161 int load_idx = loadHead; 1162 1163 while (load_idx != loadTail && loadQueue[load_idx]) { 1164 cprintf("%s ", loadQueue[load_idx]->pcState()); 1165 1166 incrLdIdx(load_idx); 1167 } 1168 1169 cprintf("Store queue size: %i\n", stores); 1170 cprintf("Store queue: "); 1171 1172 int store_idx = storeHead; 1173 1174 while (store_idx != storeTail && storeQueue[store_idx].inst) { 1175 cprintf("%s ", storeQueue[store_idx].inst->pcState()); 1176 1177 incrStIdx(store_idx); 1178 } 1179 1180 cprintf("\n"); 1181} 1182