lsq_unit_impl.hh revision 6658:f4de76601762
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 310259SAndrew.Bardsley@arm.com * All rights reserved. 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 610259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 710259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 810259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 910259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 1110259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 1210259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 1310259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 1410259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 1510259SAndrew.Bardsley@arm.com * 1610259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710259SAndrew.Bardsley@arm.com * 2810259SAndrew.Bardsley@arm.com * Authors: Kevin Lim 2910259SAndrew.Bardsley@arm.com * Korey Sewell 3010259SAndrew.Bardsley@arm.com */ 3110259SAndrew.Bardsley@arm.com 3210259SAndrew.Bardsley@arm.com#include "arch/locked_mem.hh" 3310259SAndrew.Bardsley@arm.com#include "config/the_isa.hh" 3410259SAndrew.Bardsley@arm.com#include "config/use_checker.hh" 3510259SAndrew.Bardsley@arm.com#include "cpu/o3/lsq.hh" 3610259SAndrew.Bardsley@arm.com#include "cpu/o3/lsq_unit.hh" 3710259SAndrew.Bardsley@arm.com#include "base/str.hh" 3810259SAndrew.Bardsley@arm.com#include "mem/packet.hh" 3910259SAndrew.Bardsley@arm.com#include "mem/request.hh" 4010259SAndrew.Bardsley@arm.com 4110259SAndrew.Bardsley@arm.com#if USE_CHECKER 4210259SAndrew.Bardsley@arm.com#include "cpu/checker/cpu.hh" 4310259SAndrew.Bardsley@arm.com#endif 4410259SAndrew.Bardsley@arm.com 4510259SAndrew.Bardsley@arm.comtemplate<class Impl> 4610259SAndrew.Bardsley@arm.comLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 4710259SAndrew.Bardsley@arm.com LSQUnit *lsq_ptr) 4810259SAndrew.Bardsley@arm.com : inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 4910259SAndrew.Bardsley@arm.com{ 5010259SAndrew.Bardsley@arm.com this->setFlags(Event::AutoDelete); 5110259SAndrew.Bardsley@arm.com} 5210259SAndrew.Bardsley@arm.com 5310259SAndrew.Bardsley@arm.comtemplate<class Impl> 5410259SAndrew.Bardsley@arm.comvoid 5510259SAndrew.Bardsley@arm.comLSQUnit<Impl>::WritebackEvent::process() 5610259SAndrew.Bardsley@arm.com{ 5710259SAndrew.Bardsley@arm.com if (!lsqPtr->isSwitchedOut()) { 5810259SAndrew.Bardsley@arm.com lsqPtr->writeback(inst, pkt); 5910259SAndrew.Bardsley@arm.com } 6010259SAndrew.Bardsley@arm.com 6110259SAndrew.Bardsley@arm.com if (pkt->senderState) 6210259SAndrew.Bardsley@arm.com delete pkt->senderState; 6310259SAndrew.Bardsley@arm.com 6410259SAndrew.Bardsley@arm.com delete pkt->req; 6510259SAndrew.Bardsley@arm.com delete pkt; 6610259SAndrew.Bardsley@arm.com} 6710259SAndrew.Bardsley@arm.com 6810259SAndrew.Bardsley@arm.comtemplate<class Impl> 6910259SAndrew.Bardsley@arm.comconst char * 7010259SAndrew.Bardsley@arm.comLSQUnit<Impl>::WritebackEvent::description() const 7110259SAndrew.Bardsley@arm.com{ 7210259SAndrew.Bardsley@arm.com return "Store writeback"; 7310259SAndrew.Bardsley@arm.com} 7410259SAndrew.Bardsley@arm.com 7510259SAndrew.Bardsley@arm.comtemplate<class Impl> 7610259SAndrew.Bardsley@arm.comvoid 7710259SAndrew.Bardsley@arm.comLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 7810259SAndrew.Bardsley@arm.com{ 7910259SAndrew.Bardsley@arm.com LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 8010259SAndrew.Bardsley@arm.com DynInstPtr inst = state->inst; 8110259SAndrew.Bardsley@arm.com DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 8210259SAndrew.Bardsley@arm.com DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); 8310259SAndrew.Bardsley@arm.com 8410259SAndrew.Bardsley@arm.com //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 8510259SAndrew.Bardsley@arm.com 8610259SAndrew.Bardsley@arm.com assert(!pkt->wasNacked()); 8710259SAndrew.Bardsley@arm.com 8810259SAndrew.Bardsley@arm.com if (isSwitchedOut() || inst->isSquashed()) { 8910259SAndrew.Bardsley@arm.com iewStage->decrWb(inst->seqNum); 9010259SAndrew.Bardsley@arm.com } else { 9110259SAndrew.Bardsley@arm.com if (!state->noWB) { 9210259SAndrew.Bardsley@arm.com writeback(inst, pkt); 9310259SAndrew.Bardsley@arm.com } 9410259SAndrew.Bardsley@arm.com 9510259SAndrew.Bardsley@arm.com if (inst->isStore()) { 9610259SAndrew.Bardsley@arm.com completeStore(state->idx); 9710259SAndrew.Bardsley@arm.com } 9810259SAndrew.Bardsley@arm.com } 9910259SAndrew.Bardsley@arm.com 10010259SAndrew.Bardsley@arm.com delete state; 10111341Sandreas.hansson@arm.com delete pkt->req; 10210259SAndrew.Bardsley@arm.com delete pkt; 10310259SAndrew.Bardsley@arm.com} 10411341Sandreas.hansson@arm.com 10510259SAndrew.Bardsley@arm.comtemplate <class Impl> 10611331Sandreas.hansson@arm.comLSQUnit<Impl>::LSQUnit() 10711331Sandreas.hansson@arm.com : loads(0), stores(0), storesToWB(0), stalled(false), 10811341Sandreas.hansson@arm.com isStoreBlocked(false), isLoadBlocked(false), 10910259SAndrew.Bardsley@arm.com loadBlockedHandled(false) 11011331Sandreas.hansson@arm.com{ 11111341Sandreas.hansson@arm.com} 11210259SAndrew.Bardsley@arm.com 11310259SAndrew.Bardsley@arm.comtemplate<class Impl> 11410259SAndrew.Bardsley@arm.comvoid 11510259SAndrew.Bardsley@arm.comLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 11610259SAndrew.Bardsley@arm.com LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 11710259SAndrew.Bardsley@arm.com unsigned id) 11810259SAndrew.Bardsley@arm.com{ 11910259SAndrew.Bardsley@arm.com cpu = cpu_ptr; 12010259SAndrew.Bardsley@arm.com iewStage = iew_ptr; 12110259SAndrew.Bardsley@arm.com 12210259SAndrew.Bardsley@arm.com DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 12310259SAndrew.Bardsley@arm.com 12410259SAndrew.Bardsley@arm.com switchedOut = false; 12510259SAndrew.Bardsley@arm.com 12610259SAndrew.Bardsley@arm.com lsq = lsq_ptr; 12710259SAndrew.Bardsley@arm.com 12810259SAndrew.Bardsley@arm.com lsqID = id; 12910259SAndrew.Bardsley@arm.com 13010259SAndrew.Bardsley@arm.com // Add 1 for the sentinel entry (they are circular queues). 13110259SAndrew.Bardsley@arm.com LQEntries = maxLQEntries + 1; 13210259SAndrew.Bardsley@arm.com SQEntries = maxSQEntries + 1; 13310259SAndrew.Bardsley@arm.com 13410259SAndrew.Bardsley@arm.com loadQueue.resize(LQEntries); 13510259SAndrew.Bardsley@arm.com storeQueue.resize(SQEntries); 13610259SAndrew.Bardsley@arm.com 13710259SAndrew.Bardsley@arm.com loadHead = loadTail = 0; 13810259SAndrew.Bardsley@arm.com 13910259SAndrew.Bardsley@arm.com storeHead = storeWBIdx = storeTail = 0; 14010259SAndrew.Bardsley@arm.com 14110259SAndrew.Bardsley@arm.com usedPorts = 0; 14210259SAndrew.Bardsley@arm.com cachePorts = params->cachePorts; 14310259SAndrew.Bardsley@arm.com 14410259SAndrew.Bardsley@arm.com retryPkt = NULL; 14510259SAndrew.Bardsley@arm.com memDepViolator = NULL; 14610259SAndrew.Bardsley@arm.com 14710259SAndrew.Bardsley@arm.com blockedLoadSeqNum = 0; 14810259SAndrew.Bardsley@arm.com} 14910259SAndrew.Bardsley@arm.com 15010259SAndrew.Bardsley@arm.comtemplate<class Impl> 15110259SAndrew.Bardsley@arm.comstd::string 15210259SAndrew.Bardsley@arm.comLSQUnit<Impl>::name() const 15310259SAndrew.Bardsley@arm.com{ 15410259SAndrew.Bardsley@arm.com if (Impl::MaxThreads == 1) { 15510259SAndrew.Bardsley@arm.com return iewStage->name() + ".lsq"; 15610259SAndrew.Bardsley@arm.com } else { 15710259SAndrew.Bardsley@arm.com return iewStage->name() + ".lsq.thread." + to_string(lsqID); 15810259SAndrew.Bardsley@arm.com } 15910259SAndrew.Bardsley@arm.com} 16010259SAndrew.Bardsley@arm.com 16110259SAndrew.Bardsley@arm.comtemplate<class Impl> 16210259SAndrew.Bardsley@arm.comvoid 16310259SAndrew.Bardsley@arm.comLSQUnit<Impl>::regStats() 16410259SAndrew.Bardsley@arm.com{ 16510259SAndrew.Bardsley@arm.com lsqForwLoads 16610259SAndrew.Bardsley@arm.com .name(name() + ".forwLoads") 16710259SAndrew.Bardsley@arm.com .desc("Number of loads that had data forwarded from stores"); 16810259SAndrew.Bardsley@arm.com 16910259SAndrew.Bardsley@arm.com invAddrLoads 17010259SAndrew.Bardsley@arm.com .name(name() + ".invAddrLoads") 17110259SAndrew.Bardsley@arm.com .desc("Number of loads ignored due to an invalid address"); 17210259SAndrew.Bardsley@arm.com 17310259SAndrew.Bardsley@arm.com lsqSquashedLoads 17410259SAndrew.Bardsley@arm.com .name(name() + ".squashedLoads") 17510259SAndrew.Bardsley@arm.com .desc("Number of loads squashed"); 17610259SAndrew.Bardsley@arm.com 17710259SAndrew.Bardsley@arm.com lsqIgnoredResponses 17810259SAndrew.Bardsley@arm.com .name(name() + ".ignoredResponses") 17910259SAndrew.Bardsley@arm.com .desc("Number of memory responses ignored because the instruction is squashed"); 18010259SAndrew.Bardsley@arm.com 18110259SAndrew.Bardsley@arm.com lsqMemOrderViolation 18210259SAndrew.Bardsley@arm.com .name(name() + ".memOrderViolation") 18310259SAndrew.Bardsley@arm.com .desc("Number of memory ordering violations"); 18410259SAndrew.Bardsley@arm.com 18510259SAndrew.Bardsley@arm.com lsqSquashedStores 18610259SAndrew.Bardsley@arm.com .name(name() + ".squashedStores") 18710259SAndrew.Bardsley@arm.com .desc("Number of stores squashed"); 18810259SAndrew.Bardsley@arm.com 18910259SAndrew.Bardsley@arm.com invAddrSwpfs 19010259SAndrew.Bardsley@arm.com .name(name() + ".invAddrSwpfs") 19110259SAndrew.Bardsley@arm.com .desc("Number of software prefetches ignored due to an invalid address"); 19210259SAndrew.Bardsley@arm.com 19310259SAndrew.Bardsley@arm.com lsqBlockedLoads 19410259SAndrew.Bardsley@arm.com .name(name() + ".blockedLoads") 19510259SAndrew.Bardsley@arm.com .desc("Number of blocked loads due to partial load-store forwarding"); 19610259SAndrew.Bardsley@arm.com 19710259SAndrew.Bardsley@arm.com lsqRescheduledLoads 19810259SAndrew.Bardsley@arm.com .name(name() + ".rescheduledLoads") 19910259SAndrew.Bardsley@arm.com .desc("Number of loads that were rescheduled"); 20010259SAndrew.Bardsley@arm.com 20110259SAndrew.Bardsley@arm.com lsqCacheBlocked 20210259SAndrew.Bardsley@arm.com .name(name() + ".cacheBlocked") 20310259SAndrew.Bardsley@arm.com .desc("Number of times an access to memory failed due to the cache being blocked"); 20410259SAndrew.Bardsley@arm.com} 20510259SAndrew.Bardsley@arm.com 20610259SAndrew.Bardsley@arm.comtemplate<class Impl> 20710259SAndrew.Bardsley@arm.comvoid 20810259SAndrew.Bardsley@arm.comLSQUnit<Impl>::setDcachePort(Port *dcache_port) 20910259SAndrew.Bardsley@arm.com{ 21010259SAndrew.Bardsley@arm.com dcachePort = dcache_port; 21110259SAndrew.Bardsley@arm.com 21210259SAndrew.Bardsley@arm.com#if USE_CHECKER 21310259SAndrew.Bardsley@arm.com if (cpu->checker) { 21410259SAndrew.Bardsley@arm.com cpu->checker->setDcachePort(dcachePort); 21510259SAndrew.Bardsley@arm.com } 21610259SAndrew.Bardsley@arm.com#endif 21710259SAndrew.Bardsley@arm.com} 21810259SAndrew.Bardsley@arm.com 21910259SAndrew.Bardsley@arm.comtemplate<class Impl> 22010259SAndrew.Bardsley@arm.comvoid 22110259SAndrew.Bardsley@arm.comLSQUnit<Impl>::clearLQ() 22210259SAndrew.Bardsley@arm.com{ 22310259SAndrew.Bardsley@arm.com loadQueue.clear(); 22410259SAndrew.Bardsley@arm.com} 22510259SAndrew.Bardsley@arm.com 22610259SAndrew.Bardsley@arm.comtemplate<class Impl> 22710259SAndrew.Bardsley@arm.comvoid 22810259SAndrew.Bardsley@arm.comLSQUnit<Impl>::clearSQ() 22910259SAndrew.Bardsley@arm.com{ 23010259SAndrew.Bardsley@arm.com storeQueue.clear(); 23110259SAndrew.Bardsley@arm.com} 23210259SAndrew.Bardsley@arm.com 23310259SAndrew.Bardsley@arm.comtemplate<class Impl> 23410259SAndrew.Bardsley@arm.comvoid 23510259SAndrew.Bardsley@arm.comLSQUnit<Impl>::switchOut() 23610259SAndrew.Bardsley@arm.com{ 23710259SAndrew.Bardsley@arm.com switchedOut = true; 23810259SAndrew.Bardsley@arm.com for (int i = 0; i < loadQueue.size(); ++i) { 23910259SAndrew.Bardsley@arm.com assert(!loadQueue[i]); 24010259SAndrew.Bardsley@arm.com loadQueue[i] = NULL; 24110259SAndrew.Bardsley@arm.com } 24210259SAndrew.Bardsley@arm.com 24310259SAndrew.Bardsley@arm.com assert(storesToWB == 0); 24410259SAndrew.Bardsley@arm.com} 24510259SAndrew.Bardsley@arm.com 24610259SAndrew.Bardsley@arm.comtemplate<class Impl> 24710259SAndrew.Bardsley@arm.comvoid 24810259SAndrew.Bardsley@arm.comLSQUnit<Impl>::takeOverFrom() 24910259SAndrew.Bardsley@arm.com{ 25010259SAndrew.Bardsley@arm.com switchedOut = false; 25110259SAndrew.Bardsley@arm.com loads = stores = storesToWB = 0; 25210259SAndrew.Bardsley@arm.com 25310259SAndrew.Bardsley@arm.com loadHead = loadTail = 0; 25410259SAndrew.Bardsley@arm.com 25510259SAndrew.Bardsley@arm.com storeHead = storeWBIdx = storeTail = 0; 25610259SAndrew.Bardsley@arm.com 25710259SAndrew.Bardsley@arm.com usedPorts = 0; 25810259SAndrew.Bardsley@arm.com 25910259SAndrew.Bardsley@arm.com memDepViolator = NULL; 26010259SAndrew.Bardsley@arm.com 26110259SAndrew.Bardsley@arm.com blockedLoadSeqNum = 0; 26210259SAndrew.Bardsley@arm.com 26310259SAndrew.Bardsley@arm.com stalled = false; 26410259SAndrew.Bardsley@arm.com isLoadBlocked = false; 26510259SAndrew.Bardsley@arm.com loadBlockedHandled = false; 26610259SAndrew.Bardsley@arm.com} 26710259SAndrew.Bardsley@arm.com 26810259SAndrew.Bardsley@arm.comtemplate<class Impl> 26910259SAndrew.Bardsley@arm.comvoid 27010259SAndrew.Bardsley@arm.comLSQUnit<Impl>::resizeLQ(unsigned size) 27110259SAndrew.Bardsley@arm.com{ 27210259SAndrew.Bardsley@arm.com unsigned size_plus_sentinel = size + 1; 27310259SAndrew.Bardsley@arm.com assert(size_plus_sentinel >= LQEntries); 27410259SAndrew.Bardsley@arm.com 27510379Sandreas.hansson@arm.com if (size_plus_sentinel > LQEntries) { 27610379Sandreas.hansson@arm.com while (size_plus_sentinel > loadQueue.size()) { 27710259SAndrew.Bardsley@arm.com DynInstPtr dummy; 27810259SAndrew.Bardsley@arm.com loadQueue.push_back(dummy); 27910259SAndrew.Bardsley@arm.com LQEntries++; 28010259SAndrew.Bardsley@arm.com } 28110259SAndrew.Bardsley@arm.com } else { 28210259SAndrew.Bardsley@arm.com LQEntries = size_plus_sentinel; 28310259SAndrew.Bardsley@arm.com } 28410259SAndrew.Bardsley@arm.com 28510259SAndrew.Bardsley@arm.com} 28610259SAndrew.Bardsley@arm.com 28710259SAndrew.Bardsley@arm.comtemplate<class Impl> 28810259SAndrew.Bardsley@arm.comvoid 28910259SAndrew.Bardsley@arm.comLSQUnit<Impl>::resizeSQ(unsigned size) 29010259SAndrew.Bardsley@arm.com{ 29110259SAndrew.Bardsley@arm.com unsigned size_plus_sentinel = size + 1; 29210259SAndrew.Bardsley@arm.com if (size_plus_sentinel > SQEntries) { 29310259SAndrew.Bardsley@arm.com while (size_plus_sentinel > storeQueue.size()) { 29410259SAndrew.Bardsley@arm.com SQEntry dummy; 29510259SAndrew.Bardsley@arm.com storeQueue.push_back(dummy); 29610259SAndrew.Bardsley@arm.com SQEntries++; 29710259SAndrew.Bardsley@arm.com } 29810259SAndrew.Bardsley@arm.com } else { 29910259SAndrew.Bardsley@arm.com SQEntries = size_plus_sentinel; 30010259SAndrew.Bardsley@arm.com } 30110259SAndrew.Bardsley@arm.com} 30210259SAndrew.Bardsley@arm.com 30310259SAndrew.Bardsley@arm.comtemplate <class Impl> 30410259SAndrew.Bardsley@arm.comvoid 30510259SAndrew.Bardsley@arm.comLSQUnit<Impl>::insert(DynInstPtr &inst) 30610259SAndrew.Bardsley@arm.com{ 30710259SAndrew.Bardsley@arm.com assert(inst->isMemRef()); 30810259SAndrew.Bardsley@arm.com 30910259SAndrew.Bardsley@arm.com assert(inst->isLoad() || inst->isStore()); 31010259SAndrew.Bardsley@arm.com 31110259SAndrew.Bardsley@arm.com if (inst->isLoad()) { 31210259SAndrew.Bardsley@arm.com insertLoad(inst); 31310259SAndrew.Bardsley@arm.com } else { 31410259SAndrew.Bardsley@arm.com insertStore(inst); 31510259SAndrew.Bardsley@arm.com } 31610259SAndrew.Bardsley@arm.com 31710259SAndrew.Bardsley@arm.com inst->setInLSQ(); 31810259SAndrew.Bardsley@arm.com} 31910259SAndrew.Bardsley@arm.com 32010259SAndrew.Bardsley@arm.comtemplate <class Impl> 32110259SAndrew.Bardsley@arm.comvoid 32210259SAndrew.Bardsley@arm.comLSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 32310259SAndrew.Bardsley@arm.com{ 32410259SAndrew.Bardsley@arm.com assert((loadTail + 1) % LQEntries != loadHead); 32510259SAndrew.Bardsley@arm.com assert(loads < LQEntries); 32610259SAndrew.Bardsley@arm.com 32710259SAndrew.Bardsley@arm.com DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 32810259SAndrew.Bardsley@arm.com load_inst->readPC(), loadTail, load_inst->seqNum); 32910259SAndrew.Bardsley@arm.com 33010259SAndrew.Bardsley@arm.com load_inst->lqIdx = loadTail; 33110259SAndrew.Bardsley@arm.com 33210259SAndrew.Bardsley@arm.com if (stores == 0) { 33310259SAndrew.Bardsley@arm.com load_inst->sqIdx = -1; 33410259SAndrew.Bardsley@arm.com } else { 33510259SAndrew.Bardsley@arm.com load_inst->sqIdx = storeTail; 33610379Sandreas.hansson@arm.com } 33710379Sandreas.hansson@arm.com 33810259SAndrew.Bardsley@arm.com loadQueue[loadTail] = load_inst; 33910259SAndrew.Bardsley@arm.com 34010259SAndrew.Bardsley@arm.com incrLdIdx(loadTail); 34110259SAndrew.Bardsley@arm.com 34210259SAndrew.Bardsley@arm.com ++loads; 34310259SAndrew.Bardsley@arm.com} 34410259SAndrew.Bardsley@arm.com 34510259SAndrew.Bardsley@arm.comtemplate <class Impl> 34610259SAndrew.Bardsley@arm.comvoid 34710259SAndrew.Bardsley@arm.comLSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 34810259SAndrew.Bardsley@arm.com{ 34910259SAndrew.Bardsley@arm.com // Make sure it is not full before inserting an instruction. 35010259SAndrew.Bardsley@arm.com assert((storeTail + 1) % SQEntries != storeHead); 35110259SAndrew.Bardsley@arm.com assert(stores < SQEntries); 35210259SAndrew.Bardsley@arm.com 35310259SAndrew.Bardsley@arm.com DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 35410259SAndrew.Bardsley@arm.com store_inst->readPC(), storeTail, store_inst->seqNum); 35510259SAndrew.Bardsley@arm.com 35610259SAndrew.Bardsley@arm.com store_inst->sqIdx = storeTail; 35710259SAndrew.Bardsley@arm.com store_inst->lqIdx = loadTail; 35810259SAndrew.Bardsley@arm.com 35910259SAndrew.Bardsley@arm.com storeQueue[storeTail] = SQEntry(store_inst); 36010259SAndrew.Bardsley@arm.com 36110259SAndrew.Bardsley@arm.com incrStIdx(storeTail); 36210259SAndrew.Bardsley@arm.com 36310259SAndrew.Bardsley@arm.com ++stores; 36410259SAndrew.Bardsley@arm.com} 36510259SAndrew.Bardsley@arm.com 36610259SAndrew.Bardsley@arm.comtemplate <class Impl> 36710259SAndrew.Bardsley@arm.comtypename Impl::DynInstPtr 36810259SAndrew.Bardsley@arm.comLSQUnit<Impl>::getMemDepViolator() 36910259SAndrew.Bardsley@arm.com{ 37010259SAndrew.Bardsley@arm.com DynInstPtr temp = memDepViolator; 37110259SAndrew.Bardsley@arm.com 37210259SAndrew.Bardsley@arm.com memDepViolator = NULL; 37310259SAndrew.Bardsley@arm.com 37410259SAndrew.Bardsley@arm.com return temp; 37510259SAndrew.Bardsley@arm.com} 37610259SAndrew.Bardsley@arm.com 37710259SAndrew.Bardsley@arm.comtemplate <class Impl> 37810259SAndrew.Bardsley@arm.comunsigned 37910259SAndrew.Bardsley@arm.comLSQUnit<Impl>::numFreeEntries() 38010259SAndrew.Bardsley@arm.com{ 38110259SAndrew.Bardsley@arm.com unsigned free_lq_entries = LQEntries - loads; 38210259SAndrew.Bardsley@arm.com unsigned free_sq_entries = SQEntries - stores; 38310259SAndrew.Bardsley@arm.com 38410259SAndrew.Bardsley@arm.com // Both the LQ and SQ entries have an extra dummy entry to differentiate 38510259SAndrew.Bardsley@arm.com // empty/full conditions. Subtract 1 from the free entries. 38610259SAndrew.Bardsley@arm.com if (free_lq_entries < free_sq_entries) { 38710259SAndrew.Bardsley@arm.com return free_lq_entries - 1; 38810259SAndrew.Bardsley@arm.com } else { 38910259SAndrew.Bardsley@arm.com return free_sq_entries - 1; 39010259SAndrew.Bardsley@arm.com } 39110259SAndrew.Bardsley@arm.com} 39210259SAndrew.Bardsley@arm.com 39310259SAndrew.Bardsley@arm.comtemplate <class Impl> 39410259SAndrew.Bardsley@arm.comint 39510259SAndrew.Bardsley@arm.comLSQUnit<Impl>::numLoadsReady() 39610259SAndrew.Bardsley@arm.com{ 39710259SAndrew.Bardsley@arm.com int load_idx = loadHead; 39810259SAndrew.Bardsley@arm.com int retval = 0; 39910259SAndrew.Bardsley@arm.com 40010259SAndrew.Bardsley@arm.com while (load_idx != loadTail) { 40110259SAndrew.Bardsley@arm.com assert(loadQueue[load_idx]); 40210259SAndrew.Bardsley@arm.com 40310259SAndrew.Bardsley@arm.com if (loadQueue[load_idx]->readyToIssue()) { 40410259SAndrew.Bardsley@arm.com ++retval; 40510259SAndrew.Bardsley@arm.com } 40610259SAndrew.Bardsley@arm.com } 40710259SAndrew.Bardsley@arm.com 40810259SAndrew.Bardsley@arm.com return retval; 40910259SAndrew.Bardsley@arm.com} 41010259SAndrew.Bardsley@arm.com 41110259SAndrew.Bardsley@arm.comtemplate <class Impl> 41210259SAndrew.Bardsley@arm.comFault 41310259SAndrew.Bardsley@arm.comLSQUnit<Impl>::executeLoad(DynInstPtr &inst) 41410259SAndrew.Bardsley@arm.com{ 41510259SAndrew.Bardsley@arm.com using namespace TheISA; 41610259SAndrew.Bardsley@arm.com // Execute a specific load. 41710259SAndrew.Bardsley@arm.com Fault load_fault = NoFault; 41810259SAndrew.Bardsley@arm.com 41910259SAndrew.Bardsley@arm.com DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 42010259SAndrew.Bardsley@arm.com inst->readPC(),inst->seqNum); 42110259SAndrew.Bardsley@arm.com 42210379Sandreas.hansson@arm.com assert(!inst->isSquashed()); 42310379Sandreas.hansson@arm.com 42410259SAndrew.Bardsley@arm.com load_fault = inst->initiateAcc(); 42510259SAndrew.Bardsley@arm.com 42610259SAndrew.Bardsley@arm.com // If the instruction faulted, then we need to send it along to commit 42710259SAndrew.Bardsley@arm.com // without the instruction completing. 42810259SAndrew.Bardsley@arm.com if (load_fault != NoFault) { 42910259SAndrew.Bardsley@arm.com // Send this instruction to commit, also make sure iew stage 43010259SAndrew.Bardsley@arm.com // realizes there is activity. 43110259SAndrew.Bardsley@arm.com // Mark it as executed unless it is an uncached load that 43210259SAndrew.Bardsley@arm.com // needs to hit the head of commit. 43310259SAndrew.Bardsley@arm.com if (!(inst->hasRequest() && inst->uncacheable()) || 43410259SAndrew.Bardsley@arm.com inst->isAtCommit()) { 43510259SAndrew.Bardsley@arm.com inst->setExecuted(); 43610259SAndrew.Bardsley@arm.com } 43710259SAndrew.Bardsley@arm.com iewStage->instToCommit(inst); 43810259SAndrew.Bardsley@arm.com iewStage->activityThisCycle(); 43910259SAndrew.Bardsley@arm.com } else if (!loadBlocked()) { 44010259SAndrew.Bardsley@arm.com assert(inst->effAddrValid); 44110259SAndrew.Bardsley@arm.com int load_idx = inst->lqIdx; 44210259SAndrew.Bardsley@arm.com incrLdIdx(load_idx); 44310259SAndrew.Bardsley@arm.com while (load_idx != loadTail) { 44410259SAndrew.Bardsley@arm.com // Really only need to check loads that have actually executed 44510259SAndrew.Bardsley@arm.com 44610259SAndrew.Bardsley@arm.com // @todo: For now this is extra conservative, detecting a 44710259SAndrew.Bardsley@arm.com // violation if the addresses match assuming all accesses 44810259SAndrew.Bardsley@arm.com // are quad word accesses. 44910259SAndrew.Bardsley@arm.com 45010259SAndrew.Bardsley@arm.com // @todo: Fix this, magic number being used here 45110259SAndrew.Bardsley@arm.com if (loadQueue[load_idx]->effAddrValid && 45210259SAndrew.Bardsley@arm.com (loadQueue[load_idx]->effAddr >> 8) == 45310259SAndrew.Bardsley@arm.com (inst->effAddr >> 8)) { 45410259SAndrew.Bardsley@arm.com // A load incorrectly passed this load. Squash and refetch. 45510259SAndrew.Bardsley@arm.com // For now return a fault to show that it was unsuccessful. 45610259SAndrew.Bardsley@arm.com DynInstPtr violator = loadQueue[load_idx]; 45710259SAndrew.Bardsley@arm.com if (!memDepViolator || 45810259SAndrew.Bardsley@arm.com (violator->seqNum < memDepViolator->seqNum)) { 45910259SAndrew.Bardsley@arm.com memDepViolator = violator; 46010259SAndrew.Bardsley@arm.com } else { 46110259SAndrew.Bardsley@arm.com break; 46210259SAndrew.Bardsley@arm.com } 46310259SAndrew.Bardsley@arm.com 46410259SAndrew.Bardsley@arm.com ++lsqMemOrderViolation; 46510259SAndrew.Bardsley@arm.com 46610259SAndrew.Bardsley@arm.com return genMachineCheckFault(); 46710259SAndrew.Bardsley@arm.com } 46810259SAndrew.Bardsley@arm.com 46910259SAndrew.Bardsley@arm.com incrLdIdx(load_idx); 47010259SAndrew.Bardsley@arm.com } 47110259SAndrew.Bardsley@arm.com } 47210259SAndrew.Bardsley@arm.com 47310259SAndrew.Bardsley@arm.com return load_fault; 47410259SAndrew.Bardsley@arm.com} 47510259SAndrew.Bardsley@arm.com 47610259SAndrew.Bardsley@arm.comtemplate <class Impl> 47710259SAndrew.Bardsley@arm.comFault 47810259SAndrew.Bardsley@arm.comLSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 47910259SAndrew.Bardsley@arm.com{ 48010259SAndrew.Bardsley@arm.com using namespace TheISA; 48110259SAndrew.Bardsley@arm.com // Make sure that a store exists. 48210259SAndrew.Bardsley@arm.com assert(stores != 0); 48310259SAndrew.Bardsley@arm.com 48410259SAndrew.Bardsley@arm.com int store_idx = store_inst->sqIdx; 48510259SAndrew.Bardsley@arm.com 48610259SAndrew.Bardsley@arm.com DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 48710259SAndrew.Bardsley@arm.com store_inst->readPC(), store_inst->seqNum); 48810259SAndrew.Bardsley@arm.com 48910259SAndrew.Bardsley@arm.com assert(!store_inst->isSquashed()); 49010259SAndrew.Bardsley@arm.com 49110259SAndrew.Bardsley@arm.com // Check the recently completed loads to see if any match this store's 49210259SAndrew.Bardsley@arm.com // address. If so, then we have a memory ordering violation. 49310259SAndrew.Bardsley@arm.com int load_idx = store_inst->lqIdx; 49410259SAndrew.Bardsley@arm.com 49510259SAndrew.Bardsley@arm.com Fault store_fault = store_inst->initiateAcc(); 49610259SAndrew.Bardsley@arm.com 49710259SAndrew.Bardsley@arm.com if (storeQueue[store_idx].size == 0) { 49810259SAndrew.Bardsley@arm.com DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 49910259SAndrew.Bardsley@arm.com store_inst->readPC(),store_inst->seqNum); 50010259SAndrew.Bardsley@arm.com 50110259SAndrew.Bardsley@arm.com return store_fault; 50210259SAndrew.Bardsley@arm.com } 50310259SAndrew.Bardsley@arm.com 50410259SAndrew.Bardsley@arm.com assert(store_fault == NoFault); 50510259SAndrew.Bardsley@arm.com 50610259SAndrew.Bardsley@arm.com if (store_inst->isStoreConditional()) { 50710259SAndrew.Bardsley@arm.com // Store conditionals need to set themselves as able to 50810259SAndrew.Bardsley@arm.com // writeback if we haven't had a fault by here. 50910259SAndrew.Bardsley@arm.com storeQueue[store_idx].canWB = true; 51010259SAndrew.Bardsley@arm.com 51110259SAndrew.Bardsley@arm.com ++storesToWB; 51210259SAndrew.Bardsley@arm.com } 51310259SAndrew.Bardsley@arm.com 51410259SAndrew.Bardsley@arm.com assert(store_inst->effAddrValid); 51510259SAndrew.Bardsley@arm.com while (load_idx != loadTail) { 51610259SAndrew.Bardsley@arm.com // Really only need to check loads that have actually executed 51710259SAndrew.Bardsley@arm.com // It's safe to check all loads because effAddr is set to 51810259SAndrew.Bardsley@arm.com // InvalAddr when the dyn inst is created. 51910259SAndrew.Bardsley@arm.com 52010259SAndrew.Bardsley@arm.com // @todo: For now this is extra conservative, detecting a 52110581SAndrew.Bardsley@arm.com // violation if the addresses match assuming all accesses 52210581SAndrew.Bardsley@arm.com // are quad word accesses. 52310581SAndrew.Bardsley@arm.com 52410581SAndrew.Bardsley@arm.com // @todo: Fix this, magic number being used here 52510581SAndrew.Bardsley@arm.com if (loadQueue[load_idx]->effAddrValid && 52610259SAndrew.Bardsley@arm.com (loadQueue[load_idx]->effAddr >> 8) == 52710259SAndrew.Bardsley@arm.com (store_inst->effAddr >> 8)) { 52810259SAndrew.Bardsley@arm.com // A load incorrectly passed this store. Squash and refetch. 52910259SAndrew.Bardsley@arm.com // For now return a fault to show that it was unsuccessful. 53010259SAndrew.Bardsley@arm.com DynInstPtr violator = loadQueue[load_idx]; 53110259SAndrew.Bardsley@arm.com if (!memDepViolator || 53210259SAndrew.Bardsley@arm.com (violator->seqNum < memDepViolator->seqNum)) { 53310259SAndrew.Bardsley@arm.com memDepViolator = violator; 53410259SAndrew.Bardsley@arm.com } else { 53510259SAndrew.Bardsley@arm.com break; 53610259SAndrew.Bardsley@arm.com } 53710259SAndrew.Bardsley@arm.com 53810259SAndrew.Bardsley@arm.com ++lsqMemOrderViolation; 53910259SAndrew.Bardsley@arm.com 54010259SAndrew.Bardsley@arm.com return genMachineCheckFault(); 54110259SAndrew.Bardsley@arm.com } 54210259SAndrew.Bardsley@arm.com 54310259SAndrew.Bardsley@arm.com incrLdIdx(load_idx); 54410259SAndrew.Bardsley@arm.com } 54510259SAndrew.Bardsley@arm.com 54610259SAndrew.Bardsley@arm.com return store_fault; 54710259SAndrew.Bardsley@arm.com} 54810259SAndrew.Bardsley@arm.com 54910259SAndrew.Bardsley@arm.comtemplate <class Impl> 55010259SAndrew.Bardsley@arm.comvoid 55110259SAndrew.Bardsley@arm.comLSQUnit<Impl>::commitLoad() 55210259SAndrew.Bardsley@arm.com{ 55310259SAndrew.Bardsley@arm.com assert(loadQueue[loadHead]); 55410259SAndrew.Bardsley@arm.com 55510259SAndrew.Bardsley@arm.com DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 55610259SAndrew.Bardsley@arm.com loadQueue[loadHead]->readPC()); 55710259SAndrew.Bardsley@arm.com 55810259SAndrew.Bardsley@arm.com loadQueue[loadHead] = NULL; 55910259SAndrew.Bardsley@arm.com 56010259SAndrew.Bardsley@arm.com incrLdIdx(loadHead); 56110259SAndrew.Bardsley@arm.com 56210259SAndrew.Bardsley@arm.com --loads; 56310259SAndrew.Bardsley@arm.com} 56410259SAndrew.Bardsley@arm.com 56510259SAndrew.Bardsley@arm.comtemplate <class Impl> 56610259SAndrew.Bardsley@arm.comvoid 56710259SAndrew.Bardsley@arm.comLSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 56810259SAndrew.Bardsley@arm.com{ 56910259SAndrew.Bardsley@arm.com assert(loads == 0 || loadQueue[loadHead]); 57010259SAndrew.Bardsley@arm.com 57110259SAndrew.Bardsley@arm.com while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 57210259SAndrew.Bardsley@arm.com commitLoad(); 57310259SAndrew.Bardsley@arm.com } 57410259SAndrew.Bardsley@arm.com} 57510259SAndrew.Bardsley@arm.com 57610259SAndrew.Bardsley@arm.comtemplate <class Impl> 57710259SAndrew.Bardsley@arm.comvoid 57810259SAndrew.Bardsley@arm.comLSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 57910259SAndrew.Bardsley@arm.com{ 58010259SAndrew.Bardsley@arm.com assert(stores == 0 || storeQueue[storeHead].inst); 58110259SAndrew.Bardsley@arm.com 58210259SAndrew.Bardsley@arm.com int store_idx = storeHead; 58310259SAndrew.Bardsley@arm.com 58410259SAndrew.Bardsley@arm.com while (store_idx != storeTail) { 58510259SAndrew.Bardsley@arm.com assert(storeQueue[store_idx].inst); 58610259SAndrew.Bardsley@arm.com // Mark any stores that are now committed and have not yet 58710259SAndrew.Bardsley@arm.com // been marked as able to write back. 58810259SAndrew.Bardsley@arm.com if (!storeQueue[store_idx].canWB) { 58910259SAndrew.Bardsley@arm.com if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 59010259SAndrew.Bardsley@arm.com break; 59110259SAndrew.Bardsley@arm.com } 59210259SAndrew.Bardsley@arm.com DPRINTF(LSQUnit, "Marking store as able to write back, PC " 59310259SAndrew.Bardsley@arm.com "%#x [sn:%lli]\n", 59410259SAndrew.Bardsley@arm.com storeQueue[store_idx].inst->readPC(), 59510259SAndrew.Bardsley@arm.com storeQueue[store_idx].inst->seqNum); 59610259SAndrew.Bardsley@arm.com 59710368SAndrew.Bardsley@arm.com storeQueue[store_idx].canWB = true; 59810368SAndrew.Bardsley@arm.com 59910368SAndrew.Bardsley@arm.com ++storesToWB; 60010368SAndrew.Bardsley@arm.com } 60110368SAndrew.Bardsley@arm.com 60210259SAndrew.Bardsley@arm.com incrStIdx(store_idx); 60310259SAndrew.Bardsley@arm.com } 60410259SAndrew.Bardsley@arm.com} 60510259SAndrew.Bardsley@arm.com 60610259SAndrew.Bardsley@arm.comtemplate <class Impl> 60710259SAndrew.Bardsley@arm.comvoid 60810259SAndrew.Bardsley@arm.comLSQUnit<Impl>::writebackStores() 60910259SAndrew.Bardsley@arm.com{ 61010259SAndrew.Bardsley@arm.com while (storesToWB > 0 && 61110259SAndrew.Bardsley@arm.com storeWBIdx != storeTail && 61210259SAndrew.Bardsley@arm.com storeQueue[storeWBIdx].inst && 61310259SAndrew.Bardsley@arm.com storeQueue[storeWBIdx].canWB && 61410259SAndrew.Bardsley@arm.com usedPorts < cachePorts) { 61510259SAndrew.Bardsley@arm.com 61610259SAndrew.Bardsley@arm.com if (isStoreBlocked || lsq->cacheBlocked()) { 61710259SAndrew.Bardsley@arm.com DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 61810259SAndrew.Bardsley@arm.com " is blocked!\n"); 61910259SAndrew.Bardsley@arm.com break; 62010259SAndrew.Bardsley@arm.com } 62110259SAndrew.Bardsley@arm.com 62210259SAndrew.Bardsley@arm.com // Store didn't write any data so no need to write it back to 62310259SAndrew.Bardsley@arm.com // memory. 62410259SAndrew.Bardsley@arm.com if (storeQueue[storeWBIdx].size == 0) { 62510259SAndrew.Bardsley@arm.com completeStore(storeWBIdx); 62610259SAndrew.Bardsley@arm.com 62710259SAndrew.Bardsley@arm.com incrStIdx(storeWBIdx); 62810259SAndrew.Bardsley@arm.com 62910259SAndrew.Bardsley@arm.com continue; 63010259SAndrew.Bardsley@arm.com } 63110259SAndrew.Bardsley@arm.com 63210259SAndrew.Bardsley@arm.com ++usedPorts; 63310259SAndrew.Bardsley@arm.com 63410259SAndrew.Bardsley@arm.com if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 63510259SAndrew.Bardsley@arm.com incrStIdx(storeWBIdx); 63610259SAndrew.Bardsley@arm.com 63710259SAndrew.Bardsley@arm.com continue; 63810259SAndrew.Bardsley@arm.com } 63910259SAndrew.Bardsley@arm.com 64010259SAndrew.Bardsley@arm.com assert(storeQueue[storeWBIdx].req); 64110259SAndrew.Bardsley@arm.com assert(!storeQueue[storeWBIdx].committed); 64210259SAndrew.Bardsley@arm.com 64310259SAndrew.Bardsley@arm.com DynInstPtr inst = storeQueue[storeWBIdx].inst; 64410259SAndrew.Bardsley@arm.com 64510259SAndrew.Bardsley@arm.com Request *req = storeQueue[storeWBIdx].req; 64610259SAndrew.Bardsley@arm.com storeQueue[storeWBIdx].committed = true; 64710259SAndrew.Bardsley@arm.com 64810259SAndrew.Bardsley@arm.com assert(!inst->memData); 64910259SAndrew.Bardsley@arm.com inst->memData = new uint8_t[64]; 65010259SAndrew.Bardsley@arm.com 65110259SAndrew.Bardsley@arm.com memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 65210259SAndrew.Bardsley@arm.com 65310259SAndrew.Bardsley@arm.com MemCmd command = 65410259SAndrew.Bardsley@arm.com req->isSwap() ? MemCmd::SwapReq : 65510259SAndrew.Bardsley@arm.com (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 65610259SAndrew.Bardsley@arm.com PacketPtr data_pkt = new Packet(req, command, 65710259SAndrew.Bardsley@arm.com Packet::Broadcast); 65810259SAndrew.Bardsley@arm.com data_pkt->dataStatic(inst->memData); 65910259SAndrew.Bardsley@arm.com 66010259SAndrew.Bardsley@arm.com LSQSenderState *state = new LSQSenderState; 66110259SAndrew.Bardsley@arm.com state->isLoad = false; 66210259SAndrew.Bardsley@arm.com state->idx = storeWBIdx; 66310259SAndrew.Bardsley@arm.com state->inst = inst; 66410259SAndrew.Bardsley@arm.com data_pkt->senderState = state; 66510259SAndrew.Bardsley@arm.com 66610259SAndrew.Bardsley@arm.com DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 66710259SAndrew.Bardsley@arm.com "to Addr:%#x, data:%#x [sn:%lli]\n", 66810259SAndrew.Bardsley@arm.com storeWBIdx, inst->readPC(), 66910259SAndrew.Bardsley@arm.com req->getPaddr(), (int)*(inst->memData), 67010259SAndrew.Bardsley@arm.com inst->seqNum); 67110259SAndrew.Bardsley@arm.com 67210259SAndrew.Bardsley@arm.com // @todo: Remove this SC hack once the memory system handles it. 67310259SAndrew.Bardsley@arm.com if (inst->isStoreConditional()) { 67410259SAndrew.Bardsley@arm.com // Disable recording the result temporarily. Writing to 67510259SAndrew.Bardsley@arm.com // misc regs normally updates the result, but this is not 67610259SAndrew.Bardsley@arm.com // the desired behavior when handling store conditionals. 67710259SAndrew.Bardsley@arm.com inst->recordResult = false; 67810259SAndrew.Bardsley@arm.com bool success = TheISA::handleLockedWrite(inst.get(), req); 67910259SAndrew.Bardsley@arm.com inst->recordResult = true; 68010259SAndrew.Bardsley@arm.com 68110259SAndrew.Bardsley@arm.com if (!success) { 68210259SAndrew.Bardsley@arm.com // Instantly complete this store. 68310259SAndrew.Bardsley@arm.com DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 68410259SAndrew.Bardsley@arm.com "Instantly completing it.\n", 68510259SAndrew.Bardsley@arm.com inst->seqNum); 68610259SAndrew.Bardsley@arm.com WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 68710259SAndrew.Bardsley@arm.com cpu->schedule(wb, curTick + 1); 68810259SAndrew.Bardsley@arm.com completeStore(storeWBIdx); 68910259SAndrew.Bardsley@arm.com incrStIdx(storeWBIdx); 69010259SAndrew.Bardsley@arm.com continue; 69110259SAndrew.Bardsley@arm.com } 69210259SAndrew.Bardsley@arm.com } else { 69310259SAndrew.Bardsley@arm.com // Non-store conditionals do not need a writeback. 69410259SAndrew.Bardsley@arm.com state->noWB = true; 69510259SAndrew.Bardsley@arm.com } 69610259SAndrew.Bardsley@arm.com 69710259SAndrew.Bardsley@arm.com if (!dcachePort->sendTiming(data_pkt)) { 69810259SAndrew.Bardsley@arm.com // Need to handle becoming blocked on a store. 69910259SAndrew.Bardsley@arm.com DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 70010259SAndrew.Bardsley@arm.com "retry later\n", 70110259SAndrew.Bardsley@arm.com inst->seqNum); 70210259SAndrew.Bardsley@arm.com isStoreBlocked = true; 70310259SAndrew.Bardsley@arm.com ++lsqCacheBlocked; 70410259SAndrew.Bardsley@arm.com assert(retryPkt == NULL); 70510259SAndrew.Bardsley@arm.com retryPkt = data_pkt; 70610259SAndrew.Bardsley@arm.com lsq->setRetryTid(lsqID); 70710259SAndrew.Bardsley@arm.com } else { 70810259SAndrew.Bardsley@arm.com storePostSend(data_pkt); 70910259SAndrew.Bardsley@arm.com } 71010259SAndrew.Bardsley@arm.com } 71110259SAndrew.Bardsley@arm.com 71210259SAndrew.Bardsley@arm.com // Not sure this should set it to 0. 71310259SAndrew.Bardsley@arm.com usedPorts = 0; 71410259SAndrew.Bardsley@arm.com 71510259SAndrew.Bardsley@arm.com assert(stores >= 0 && storesToWB >= 0); 71610259SAndrew.Bardsley@arm.com} 71710259SAndrew.Bardsley@arm.com 71810259SAndrew.Bardsley@arm.com/*template <class Impl> 71910713Sandreas.hansson@arm.comvoid 72010259SAndrew.Bardsley@arm.comLSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 72110259SAndrew.Bardsley@arm.com{ 72210259SAndrew.Bardsley@arm.com list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 72310259SAndrew.Bardsley@arm.com mshrSeqNums.end(), 72410259SAndrew.Bardsley@arm.com seqNum); 72510259SAndrew.Bardsley@arm.com 72610259SAndrew.Bardsley@arm.com if (mshr_it != mshrSeqNums.end()) { 72710259SAndrew.Bardsley@arm.com mshrSeqNums.erase(mshr_it); 72810259SAndrew.Bardsley@arm.com DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 72910259SAndrew.Bardsley@arm.com } 73010259SAndrew.Bardsley@arm.com}*/ 73110259SAndrew.Bardsley@arm.com 73210259SAndrew.Bardsley@arm.comtemplate <class Impl> 73310259SAndrew.Bardsley@arm.comvoid 73410259SAndrew.Bardsley@arm.comLSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 73510259SAndrew.Bardsley@arm.com{ 736 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 737 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 738 739 int load_idx = loadTail; 740 decrLdIdx(load_idx); 741 742 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 743 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 744 "[sn:%lli]\n", 745 loadQueue[load_idx]->readPC(), 746 loadQueue[load_idx]->seqNum); 747 748 if (isStalled() && load_idx == stallingLoadIdx) { 749 stalled = false; 750 stallingStoreIsn = 0; 751 stallingLoadIdx = 0; 752 } 753 754 // Clear the smart pointer to make sure it is decremented. 755 loadQueue[load_idx]->setSquashed(); 756 loadQueue[load_idx] = NULL; 757 --loads; 758 759 // Inefficient! 760 loadTail = load_idx; 761 762 decrLdIdx(load_idx); 763 ++lsqSquashedLoads; 764 } 765 766 if (isLoadBlocked) { 767 if (squashed_num < blockedLoadSeqNum) { 768 isLoadBlocked = false; 769 loadBlockedHandled = false; 770 blockedLoadSeqNum = 0; 771 } 772 } 773 774 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 775 memDepViolator = NULL; 776 } 777 778 int store_idx = storeTail; 779 decrStIdx(store_idx); 780 781 while (stores != 0 && 782 storeQueue[store_idx].inst->seqNum > squashed_num) { 783 // Instructions marked as can WB are already committed. 784 if (storeQueue[store_idx].canWB) { 785 break; 786 } 787 788 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 789 "idx:%i [sn:%lli]\n", 790 storeQueue[store_idx].inst->readPC(), 791 store_idx, storeQueue[store_idx].inst->seqNum); 792 793 // I don't think this can happen. It should have been cleared 794 // by the stalling load. 795 if (isStalled() && 796 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 797 panic("Is stalled should have been cleared by stalling load!\n"); 798 stalled = false; 799 stallingStoreIsn = 0; 800 } 801 802 // Clear the smart pointer to make sure it is decremented. 803 storeQueue[store_idx].inst->setSquashed(); 804 storeQueue[store_idx].inst = NULL; 805 storeQueue[store_idx].canWB = 0; 806 807 // Must delete request now that it wasn't handed off to 808 // memory. This is quite ugly. @todo: Figure out the proper 809 // place to really handle request deletes. 810 delete storeQueue[store_idx].req; 811 812 storeQueue[store_idx].req = NULL; 813 --stores; 814 815 // Inefficient! 816 storeTail = store_idx; 817 818 decrStIdx(store_idx); 819 ++lsqSquashedStores; 820 } 821} 822 823template <class Impl> 824void 825LSQUnit<Impl>::storePostSend(PacketPtr pkt) 826{ 827 if (isStalled() && 828 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 829 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 830 "load idx:%i\n", 831 stallingStoreIsn, stallingLoadIdx); 832 stalled = false; 833 stallingStoreIsn = 0; 834 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 835 } 836 837 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 838 // The store is basically completed at this time. This 839 // only works so long as the checker doesn't try to 840 // verify the value in memory for stores. 841 storeQueue[storeWBIdx].inst->setCompleted(); 842#if USE_CHECKER 843 if (cpu->checker) { 844 cpu->checker->verify(storeQueue[storeWBIdx].inst); 845 } 846#endif 847 } 848 849 incrStIdx(storeWBIdx); 850} 851 852template <class Impl> 853void 854LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 855{ 856 iewStage->wakeCPU(); 857 858 // Squashed instructions do not need to complete their access. 859 if (inst->isSquashed()) { 860 iewStage->decrWb(inst->seqNum); 861 assert(!inst->isStore()); 862 ++lsqIgnoredResponses; 863 return; 864 } 865 866 if (!inst->isExecuted()) { 867 inst->setExecuted(); 868 869 // Complete access to copy data to proper place. 870 inst->completeAcc(pkt); 871 } 872 873 // Need to insert instruction into queue to commit 874 iewStage->instToCommit(inst); 875 876 iewStage->activityThisCycle(); 877} 878 879template <class Impl> 880void 881LSQUnit<Impl>::completeStore(int store_idx) 882{ 883 assert(storeQueue[store_idx].inst); 884 storeQueue[store_idx].completed = true; 885 --storesToWB; 886 // A bit conservative because a store completion may not free up entries, 887 // but hopefully avoids two store completions in one cycle from making 888 // the CPU tick twice. 889 cpu->wakeCPU(); 890 cpu->activityThisCycle(); 891 892 if (store_idx == storeHead) { 893 do { 894 incrStIdx(storeHead); 895 896 --stores; 897 } while (storeQueue[storeHead].completed && 898 storeHead != storeTail); 899 900 iewStage->updateLSQNextCycle = true; 901 } 902 903 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 904 "idx:%i\n", 905 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 906 907 if (isStalled() && 908 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 909 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 910 "load idx:%i\n", 911 stallingStoreIsn, stallingLoadIdx); 912 stalled = false; 913 stallingStoreIsn = 0; 914 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 915 } 916 917 storeQueue[store_idx].inst->setCompleted(); 918 919 // Tell the checker we've completed this instruction. Some stores 920 // may get reported twice to the checker, but the checker can 921 // handle that case. 922#if USE_CHECKER 923 if (cpu->checker) { 924 cpu->checker->verify(storeQueue[store_idx].inst); 925 } 926#endif 927} 928 929template <class Impl> 930void 931LSQUnit<Impl>::recvRetry() 932{ 933 if (isStoreBlocked) { 934 DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 935 assert(retryPkt != NULL); 936 937 if (dcachePort->sendTiming(retryPkt)) { 938 storePostSend(retryPkt); 939 retryPkt = NULL; 940 isStoreBlocked = false; 941 lsq->setRetryTid(InvalidThreadID); 942 } else { 943 // Still blocked! 944 ++lsqCacheBlocked; 945 lsq->setRetryTid(lsqID); 946 } 947 } else if (isLoadBlocked) { 948 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 949 "no need to resend packet.\n"); 950 } else { 951 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 952 } 953} 954 955template <class Impl> 956inline void 957LSQUnit<Impl>::incrStIdx(int &store_idx) 958{ 959 if (++store_idx >= SQEntries) 960 store_idx = 0; 961} 962 963template <class Impl> 964inline void 965LSQUnit<Impl>::decrStIdx(int &store_idx) 966{ 967 if (--store_idx < 0) 968 store_idx += SQEntries; 969} 970 971template <class Impl> 972inline void 973LSQUnit<Impl>::incrLdIdx(int &load_idx) 974{ 975 if (++load_idx >= LQEntries) 976 load_idx = 0; 977} 978 979template <class Impl> 980inline void 981LSQUnit<Impl>::decrLdIdx(int &load_idx) 982{ 983 if (--load_idx < 0) 984 load_idx += LQEntries; 985} 986 987template <class Impl> 988void 989LSQUnit<Impl>::dumpInsts() 990{ 991 cprintf("Load store queue: Dumping instructions.\n"); 992 cprintf("Load queue size: %i\n", loads); 993 cprintf("Load queue: "); 994 995 int load_idx = loadHead; 996 997 while (load_idx != loadTail && loadQueue[load_idx]) { 998 cprintf("%#x ", loadQueue[load_idx]->readPC()); 999 1000 incrLdIdx(load_idx); 1001 } 1002 1003 cprintf("Store queue size: %i\n", stores); 1004 cprintf("Store queue: "); 1005 1006 int store_idx = storeHead; 1007 1008 while (store_idx != storeTail && storeQueue[store_idx].inst) { 1009 cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 1010 1011 incrStIdx(store_idx); 1012 } 1013 1014 cprintf("\n"); 1015} 1016