lsq_unit_impl.hh revision 2871:7ed5c9ef3eb6
12889Sbinkertn@umich.edu/* 22889Sbinkertn@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 32889Sbinkertn@umich.edu * All rights reserved. 42889Sbinkertn@umich.edu * 52889Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 62889Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 72889Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 82889Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 92889Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 102889Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 112889Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 122889Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 132889Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 142889Sbinkertn@umich.edu * this software without specific prior written permission. 152889Sbinkertn@umich.edu * 162889Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172889Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182889Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192889Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202889Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212889Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222889Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232889Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242889Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252889Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262889Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272889Sbinkertn@umich.edu * 282889Sbinkertn@umich.edu * Authors: Kevin Lim 292889Sbinkertn@umich.edu * Korey Sewell 302889Sbinkertn@umich.edu */ 312889Sbinkertn@umich.edu 324053Sbinkertn@umich.edu#include "config/use_checker.hh" 332889Sbinkertn@umich.edu 342889Sbinkertn@umich.edu#include "cpu/o3/lsq_unit.hh" 352889Sbinkertn@umich.edu#include "base/str.hh" 362889Sbinkertn@umich.edu#include "mem/packet.hh" 372889Sbinkertn@umich.edu#include "mem/request.hh" 382889Sbinkertn@umich.edu 392889Sbinkertn@umich.edu#if USE_CHECKER 402889Sbinkertn@umich.edu#include "cpu/checker/cpu.hh" 412889Sbinkertn@umich.edu#endif 422889Sbinkertn@umich.edu 432889Sbinkertn@umich.edutemplate<class Impl> 444053Sbinkertn@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 454053Sbinkertn@umich.edu LSQUnit *lsq_ptr) 464053Sbinkertn@umich.edu : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 474053Sbinkertn@umich.edu{ 484053Sbinkertn@umich.edu this->setFlags(Event::AutoDelete); 494053Sbinkertn@umich.edu} 504053Sbinkertn@umich.edu 514053Sbinkertn@umich.edutemplate<class Impl> 524053Sbinkertn@umich.eduvoid 534053Sbinkertn@umich.eduLSQUnit<Impl>::WritebackEvent::process() 544053Sbinkertn@umich.edu{ 554053Sbinkertn@umich.edu if (!lsqPtr->isSwitchedOut()) { 564053Sbinkertn@umich.edu lsqPtr->writeback(inst, pkt); 572889Sbinkertn@umich.edu } 582889Sbinkertn@umich.edu delete pkt; 592889Sbinkertn@umich.edu} 602889Sbinkertn@umich.edu 612889Sbinkertn@umich.edutemplate<class Impl> 622890Sbinkertn@umich.educonst char * 632889Sbinkertn@umich.eduLSQUnit<Impl>::WritebackEvent::description() 642889Sbinkertn@umich.edu{ 652889Sbinkertn@umich.edu return "Store writeback event"; 662889Sbinkertn@umich.edu} 672889Sbinkertn@umich.edu 682889Sbinkertn@umich.edutemplate<class Impl> 692889Sbinkertn@umich.eduvoid 702889Sbinkertn@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 712889Sbinkertn@umich.edu{ 722889Sbinkertn@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 732889Sbinkertn@umich.edu DynInstPtr inst = state->inst; 742889Sbinkertn@umich.edu DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 752889Sbinkertn@umich.edu DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); 762889Sbinkertn@umich.edu 772889Sbinkertn@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 782889Sbinkertn@umich.edu 792889Sbinkertn@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 802889Sbinkertn@umich.edu iewStage->decrWb(inst->seqNum); 812889Sbinkertn@umich.edu delete state; 822889Sbinkertn@umich.edu delete pkt; 832889Sbinkertn@umich.edu return; 842889Sbinkertn@umich.edu } else { 852889Sbinkertn@umich.edu if (!state->noWB) { 862889Sbinkertn@umich.edu writeback(inst, pkt); 872889Sbinkertn@umich.edu } 882889Sbinkertn@umich.edu 892889Sbinkertn@umich.edu if (inst->isStore()) { 902889Sbinkertn@umich.edu completeStore(state->idx); 912889Sbinkertn@umich.edu } 922889Sbinkertn@umich.edu } 932889Sbinkertn@umich.edu 942889Sbinkertn@umich.edu delete state; 952889Sbinkertn@umich.edu delete pkt; 962889Sbinkertn@umich.edu} 972889Sbinkertn@umich.edu 982889Sbinkertn@umich.edutemplate <class Impl> 992889Sbinkertn@umich.eduTick 1002889Sbinkertn@umich.eduLSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt) 1012889Sbinkertn@umich.edu{ 1022889Sbinkertn@umich.edu panic("O3CPU model does not work with atomic mode!"); 1032889Sbinkertn@umich.edu return curTick; 1042889Sbinkertn@umich.edu} 1052889Sbinkertn@umich.edu 1062889Sbinkertn@umich.edutemplate <class Impl> 1072889Sbinkertn@umich.eduvoid 1082889Sbinkertn@umich.eduLSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt) 1092889Sbinkertn@umich.edu{ 1102889Sbinkertn@umich.edu panic("O3CPU doesn't expect recvFunctional callback!"); 1112889Sbinkertn@umich.edu} 1122889Sbinkertn@umich.edu 1132889Sbinkertn@umich.edutemplate <class Impl> 1142889Sbinkertn@umich.eduvoid 1152889Sbinkertn@umich.eduLSQUnit<Impl>::DcachePort::recvStatusChange(Status status) 1162889Sbinkertn@umich.edu{ 1172889Sbinkertn@umich.edu if (status == RangeChange) 1182889Sbinkertn@umich.edu return; 1192889Sbinkertn@umich.edu 1202889Sbinkertn@umich.edu panic("O3CPU doesn't expect recvStatusChange callback!"); 1212889Sbinkertn@umich.edu} 1222889Sbinkertn@umich.edu 1232889Sbinkertn@umich.edutemplate <class Impl> 1242889Sbinkertn@umich.edubool 1252889Sbinkertn@umich.eduLSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt) 1262889Sbinkertn@umich.edu{ 1272889Sbinkertn@umich.edu lsq->completeDataAccess(pkt); 1282889Sbinkertn@umich.edu return true; 1292889Sbinkertn@umich.edu} 1302889Sbinkertn@umich.edu 1312899Sbinkertn@umich.edutemplate <class Impl> 1322899Sbinkertn@umich.eduvoid 1332889Sbinkertn@umich.eduLSQUnit<Impl>::DcachePort::recvRetry() 1342889Sbinkertn@umich.edu{ 1352889Sbinkertn@umich.edu lsq->recvRetry(); 1362889Sbinkertn@umich.edu} 1372889Sbinkertn@umich.edu 1382889Sbinkertn@umich.edutemplate <class Impl> 1392889Sbinkertn@umich.eduLSQUnit<Impl>::LSQUnit() 1402889Sbinkertn@umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1412889Sbinkertn@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1422889Sbinkertn@umich.edu loadBlockedHandled(false) 1432889Sbinkertn@umich.edu{ 1442889Sbinkertn@umich.edu} 1452889Sbinkertn@umich.edu 1462889Sbinkertn@umich.edutemplate<class Impl> 1472889Sbinkertn@umich.eduvoid 1482889Sbinkertn@umich.eduLSQUnit<Impl>::init(Params *params, unsigned maxLQEntries, 1492889Sbinkertn@umich.edu unsigned maxSQEntries, unsigned id) 1502889Sbinkertn@umich.edu{ 1512889Sbinkertn@umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1524053Sbinkertn@umich.edu 1534053Sbinkertn@umich.edu switchedOut = false; 1542889Sbinkertn@umich.edu 1554053Sbinkertn@umich.edu lsqID = id; 1564044Sbinkertn@umich.edu 1574044Sbinkertn@umich.edu // Add 1 for the sentinel entry (they are circular queues). 1582889Sbinkertn@umich.edu LQEntries = maxLQEntries + 1; 1592889Sbinkertn@umich.edu SQEntries = maxSQEntries + 1; 1602889Sbinkertn@umich.edu 1612889Sbinkertn@umich.edu loadQueue.resize(LQEntries); 1622889Sbinkertn@umich.edu storeQueue.resize(SQEntries); 1632889Sbinkertn@umich.edu 1642889Sbinkertn@umich.edu loadHead = loadTail = 0; 1652889Sbinkertn@umich.edu 1662889Sbinkertn@umich.edu storeHead = storeWBIdx = storeTail = 0; 1672903Ssaidi@eecs.umich.edu 1682889Sbinkertn@umich.edu usedPorts = 0; 1692889Sbinkertn@umich.edu cachePorts = params->cachePorts; 1702889Sbinkertn@umich.edu 1712889Sbinkertn@umich.edu mem = params->mem; 1722889Sbinkertn@umich.edu 1732889Sbinkertn@umich.edu memDepViolator = NULL; 1742889Sbinkertn@umich.edu 1752889Sbinkertn@umich.edu blockedLoadSeqNum = 0; 1762889Sbinkertn@umich.edu} 1772889Sbinkertn@umich.edu 1782889Sbinkertn@umich.edutemplate<class Impl> 1792889Sbinkertn@umich.eduvoid 1802889Sbinkertn@umich.eduLSQUnit<Impl>::setCPU(O3CPU *cpu_ptr) 1812889Sbinkertn@umich.edu{ 1822889Sbinkertn@umich.edu cpu = cpu_ptr; 1832889Sbinkertn@umich.edu dcachePort = new DcachePort(cpu, this); 1842889Sbinkertn@umich.edu 1852889Sbinkertn@umich.edu#if USE_CHECKER 1862889Sbinkertn@umich.edu if (cpu->checker) { 1872889Sbinkertn@umich.edu cpu->checker->setDcachePort(dcachePort); 1882889Sbinkertn@umich.edu } 1892889Sbinkertn@umich.edu#endif 1904042Sbinkertn@umich.edu} 1914042Sbinkertn@umich.edu 1923624Sbinkertn@umich.edutemplate<class Impl> 1932889Sbinkertn@umich.edustd::string 1942889Sbinkertn@umich.eduLSQUnit<Impl>::name() const 1952889Sbinkertn@umich.edu{ 1962889Sbinkertn@umich.edu if (Impl::MaxThreads == 1) { 1972889Sbinkertn@umich.edu return iewStage->name() + ".lsq"; 1982889Sbinkertn@umich.edu } else { 1992889Sbinkertn@umich.edu return iewStage->name() + ".lsq.thread." + to_string(lsqID); 2002889Sbinkertn@umich.edu } 2012889Sbinkertn@umich.edu} 2022889Sbinkertn@umich.edu 2032889Sbinkertn@umich.edutemplate<class Impl> 2042889Sbinkertn@umich.eduvoid 2052889Sbinkertn@umich.eduLSQUnit<Impl>::regStats() 2062889Sbinkertn@umich.edu{ 2072889Sbinkertn@umich.edu lsqForwLoads 2082889Sbinkertn@umich.edu .name(name() + ".forwLoads") 2092889Sbinkertn@umich.edu .desc("Number of loads that had data forwarded from stores"); 2102889Sbinkertn@umich.edu 2112889Sbinkertn@umich.edu invAddrLoads 2122889Sbinkertn@umich.edu .name(name() + ".invAddrLoads") 2132889Sbinkertn@umich.edu .desc("Number of loads ignored due to an invalid address"); 2142889Sbinkertn@umich.edu 2152889Sbinkertn@umich.edu lsqSquashedLoads 2162889Sbinkertn@umich.edu .name(name() + ".squashedLoads") 2172889Sbinkertn@umich.edu .desc("Number of loads squashed"); 2182889Sbinkertn@umich.edu 2192889Sbinkertn@umich.edu lsqIgnoredResponses 2202889Sbinkertn@umich.edu .name(name() + ".ignoredResponses") 2212889Sbinkertn@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2222889Sbinkertn@umich.edu 2234053Sbinkertn@umich.edu lsqSquashedStores 2244053Sbinkertn@umich.edu .name(name() + ".squashedStores") 2254053Sbinkertn@umich.edu .desc("Number of stores squashed"); 2264053Sbinkertn@umich.edu 2274053Sbinkertn@umich.edu invAddrSwpfs 2284053Sbinkertn@umich.edu .name(name() + ".invAddrSwpfs") 2294053Sbinkertn@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2304053Sbinkertn@umich.edu 2314053Sbinkertn@umich.edu lsqBlockedLoads 2324053Sbinkertn@umich.edu .name(name() + ".blockedLoads") 2334053Sbinkertn@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2344053Sbinkertn@umich.edu 2354053Sbinkertn@umich.edu lsqRescheduledLoads 2362889Sbinkertn@umich.edu .name(name() + ".rescheduledLoads") 2372889Sbinkertn@umich.edu .desc("Number of loads that were rescheduled"); 2382889Sbinkertn@umich.edu 2392889Sbinkertn@umich.edu lsqCacheBlocked 2402889Sbinkertn@umich.edu .name(name() + ".cacheBlocked") 2412889Sbinkertn@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2422889Sbinkertn@umich.edu} 2433624Sbinkertn@umich.edu 2442889Sbinkertn@umich.edutemplate<class Impl> 2452889Sbinkertn@umich.eduvoid 2462967Sktlim@umich.eduLSQUnit<Impl>::clearLQ() 2472967Sktlim@umich.edu{ 2482967Sktlim@umich.edu loadQueue.clear(); 2492967Sktlim@umich.edu} 2502889Sbinkertn@umich.edu 2512889Sbinkertn@umich.edutemplate<class Impl> 2522889Sbinkertn@umich.eduvoid 2532922Sktlim@umich.eduLSQUnit<Impl>::clearSQ() 2542922Sktlim@umich.edu{ 2554053Sbinkertn@umich.edu storeQueue.clear(); 2562889Sbinkertn@umich.edu} 2572889Sbinkertn@umich.edu 2582889Sbinkertn@umich.edutemplate<class Impl> 2593624Sbinkertn@umich.eduvoid 2602889Sbinkertn@umich.eduLSQUnit<Impl>::switchOut() 2612889Sbinkertn@umich.edu{ 2622889Sbinkertn@umich.edu switchedOut = true; 2632889Sbinkertn@umich.edu for (int i = 0; i < loadQueue.size(); ++i) 2642889Sbinkertn@umich.edu loadQueue[i] = NULL; 2652889Sbinkertn@umich.edu 2662889Sbinkertn@umich.edu assert(storesToWB == 0); 2674078Sbinkertn@umich.edu} 2682889Sbinkertn@umich.edu 2692889Sbinkertn@umich.edutemplate<class Impl> 2703645Sbinkertn@umich.eduvoid 2713645Sbinkertn@umich.eduLSQUnit<Impl>::takeOverFrom() 2722889Sbinkertn@umich.edu{ 2734053Sbinkertn@umich.edu switchedOut = false; 2744053Sbinkertn@umich.edu loads = stores = storesToWB = 0; 2754042Sbinkertn@umich.edu 2764053Sbinkertn@umich.edu loadHead = loadTail = 0; 2774053Sbinkertn@umich.edu 2784053Sbinkertn@umich.edu storeHead = storeWBIdx = storeTail = 0; 2794053Sbinkertn@umich.edu 2804053Sbinkertn@umich.edu usedPorts = 0; 2814053Sbinkertn@umich.edu 2824053Sbinkertn@umich.edu memDepViolator = NULL; 2834053Sbinkertn@umich.edu 2844053Sbinkertn@umich.edu blockedLoadSeqNum = 0; 2854053Sbinkertn@umich.edu 2864053Sbinkertn@umich.edu stalled = false; 2874053Sbinkertn@umich.edu isLoadBlocked = false; 2884053Sbinkertn@umich.edu loadBlockedHandled = false; 2894053Sbinkertn@umich.edu} 2904046Sbinkertn@umich.edu 2914042Sbinkertn@umich.edutemplate<class Impl> 2924053Sbinkertn@umich.eduvoid 2934053Sbinkertn@umich.eduLSQUnit<Impl>::resizeLQ(unsigned size) 2944053Sbinkertn@umich.edu{ 2954074Sbinkertn@umich.edu unsigned size_plus_sentinel = size + 1; 2964042Sbinkertn@umich.edu assert(size_plus_sentinel >= LQEntries); 2974074Sbinkertn@umich.edu 2984074Sbinkertn@umich.edu if (size_plus_sentinel > LQEntries) { 2994074Sbinkertn@umich.edu while (size_plus_sentinel > loadQueue.size()) { 3004074Sbinkertn@umich.edu DynInstPtr dummy; 3014042Sbinkertn@umich.edu loadQueue.push_back(dummy); 3024046Sbinkertn@umich.edu LQEntries++; 3034042Sbinkertn@umich.edu } 3044042Sbinkertn@umich.edu } else { 3054042Sbinkertn@umich.edu LQEntries = size_plus_sentinel; 3062889Sbinkertn@umich.edu } 3072889Sbinkertn@umich.edu 3082889Sbinkertn@umich.edu} 3092891Sbinkertn@umich.edu 3103887Sbinkertn@umich.edutemplate<class Impl> 3113887Sbinkertn@umich.eduvoid 3122899Sbinkertn@umich.eduLSQUnit<Impl>::resizeSQ(unsigned size) 3132899Sbinkertn@umich.edu{ 3142899Sbinkertn@umich.edu unsigned size_plus_sentinel = size + 1; 3154042Sbinkertn@umich.edu if (size_plus_sentinel > SQEntries) { 3162899Sbinkertn@umich.edu while (size_plus_sentinel > storeQueue.size()) { 3172899Sbinkertn@umich.edu SQEntry dummy; 3182899Sbinkertn@umich.edu storeQueue.push_back(dummy); 3192899Sbinkertn@umich.edu SQEntries++; 3202899Sbinkertn@umich.edu } 3212899Sbinkertn@umich.edu } else { 3222899Sbinkertn@umich.edu SQEntries = size_plus_sentinel; 3232899Sbinkertn@umich.edu } 3242899Sbinkertn@umich.edu} 3252889Sbinkertn@umich.edu 3262889Sbinkertn@umich.edutemplate <class Impl> 3272889Sbinkertn@umich.eduvoid 3282889Sbinkertn@umich.eduLSQUnit<Impl>::insert(DynInstPtr &inst) 3292889Sbinkertn@umich.edu{ 3302889Sbinkertn@umich.edu assert(inst->isMemRef()); 3312889Sbinkertn@umich.edu 3322889Sbinkertn@umich.edu assert(inst->isLoad() || inst->isStore()); 3332889Sbinkertn@umich.edu 3342889Sbinkertn@umich.edu if (inst->isLoad()) { 3352889Sbinkertn@umich.edu insertLoad(inst); 3362889Sbinkertn@umich.edu } else { 3372889Sbinkertn@umich.edu insertStore(inst); 3382889Sbinkertn@umich.edu } 3392889Sbinkertn@umich.edu 3402889Sbinkertn@umich.edu inst->setInLSQ(); 3412889Sbinkertn@umich.edu} 342 343template <class Impl> 344void 345LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 346{ 347 assert((loadTail + 1) % LQEntries != loadHead); 348 assert(loads < LQEntries); 349 350 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 351 load_inst->readPC(), loadTail, load_inst->seqNum); 352 353 load_inst->lqIdx = loadTail; 354 355 if (stores == 0) { 356 load_inst->sqIdx = -1; 357 } else { 358 load_inst->sqIdx = storeTail; 359 } 360 361 loadQueue[loadTail] = load_inst; 362 363 incrLdIdx(loadTail); 364 365 ++loads; 366} 367 368template <class Impl> 369void 370LSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 371{ 372 // Make sure it is not full before inserting an instruction. 373 assert((storeTail + 1) % SQEntries != storeHead); 374 assert(stores < SQEntries); 375 376 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 377 store_inst->readPC(), storeTail, store_inst->seqNum); 378 379 store_inst->sqIdx = storeTail; 380 store_inst->lqIdx = loadTail; 381 382 storeQueue[storeTail] = SQEntry(store_inst); 383 384 incrStIdx(storeTail); 385 386 ++stores; 387} 388 389template <class Impl> 390typename Impl::DynInstPtr 391LSQUnit<Impl>::getMemDepViolator() 392{ 393 DynInstPtr temp = memDepViolator; 394 395 memDepViolator = NULL; 396 397 return temp; 398} 399 400template <class Impl> 401unsigned 402LSQUnit<Impl>::numFreeEntries() 403{ 404 unsigned free_lq_entries = LQEntries - loads; 405 unsigned free_sq_entries = SQEntries - stores; 406 407 // Both the LQ and SQ entries have an extra dummy entry to differentiate 408 // empty/full conditions. Subtract 1 from the free entries. 409 if (free_lq_entries < free_sq_entries) { 410 return free_lq_entries - 1; 411 } else { 412 return free_sq_entries - 1; 413 } 414} 415 416template <class Impl> 417int 418LSQUnit<Impl>::numLoadsReady() 419{ 420 int load_idx = loadHead; 421 int retval = 0; 422 423 while (load_idx != loadTail) { 424 assert(loadQueue[load_idx]); 425 426 if (loadQueue[load_idx]->readyToIssue()) { 427 ++retval; 428 } 429 } 430 431 return retval; 432} 433 434template <class Impl> 435Fault 436LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 437{ 438 // Execute a specific load. 439 Fault load_fault = NoFault; 440 441 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 442 inst->readPC(),inst->seqNum); 443 444 load_fault = inst->initiateAcc(); 445 446 // If the instruction faulted, then we need to send it along to commit 447 // without the instruction completing. 448 if (load_fault != NoFault) { 449 // Send this instruction to commit, also make sure iew stage 450 // realizes there is activity. 451 iewStage->instToCommit(inst); 452 iewStage->activityThisCycle(); 453 } 454 455 return load_fault; 456} 457 458template <class Impl> 459Fault 460LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 461{ 462 using namespace TheISA; 463 // Make sure that a store exists. 464 assert(stores != 0); 465 466 int store_idx = store_inst->sqIdx; 467 468 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 469 store_inst->readPC(), store_inst->seqNum); 470 471 // Check the recently completed loads to see if any match this store's 472 // address. If so, then we have a memory ordering violation. 473 int load_idx = store_inst->lqIdx; 474 475 Fault store_fault = store_inst->initiateAcc(); 476 477 if (storeQueue[store_idx].size == 0) { 478 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 479 store_inst->readPC(),store_inst->seqNum); 480 481 return store_fault; 482 } 483 484 assert(store_fault == NoFault); 485 486 if (store_inst->isStoreConditional()) { 487 // Store conditionals need to set themselves as able to 488 // writeback if we haven't had a fault by here. 489 storeQueue[store_idx].canWB = true; 490 491 ++storesToWB; 492 } 493 494 if (!memDepViolator) { 495 while (load_idx != loadTail) { 496 // Really only need to check loads that have actually executed 497 // It's safe to check all loads because effAddr is set to 498 // InvalAddr when the dyn inst is created. 499 500 // @todo: For now this is extra conservative, detecting a 501 // violation if the addresses match assuming all accesses 502 // are quad word accesses. 503 504 // @todo: Fix this, magic number being used here 505 if ((loadQueue[load_idx]->effAddr >> 8) == 506 (store_inst->effAddr >> 8)) { 507 // A load incorrectly passed this store. Squash and refetch. 508 // For now return a fault to show that it was unsuccessful. 509 memDepViolator = loadQueue[load_idx]; 510 511 return genMachineCheckFault(); 512 } 513 514 incrLdIdx(load_idx); 515 } 516 517 // If we've reached this point, there was no violation. 518 memDepViolator = NULL; 519 } 520 521 return store_fault; 522} 523 524template <class Impl> 525void 526LSQUnit<Impl>::commitLoad() 527{ 528 assert(loadQueue[loadHead]); 529 530 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 531 loadQueue[loadHead]->readPC()); 532 533 loadQueue[loadHead] = NULL; 534 535 incrLdIdx(loadHead); 536 537 --loads; 538} 539 540template <class Impl> 541void 542LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 543{ 544 assert(loads == 0 || loadQueue[loadHead]); 545 546 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 547 commitLoad(); 548 } 549} 550 551template <class Impl> 552void 553LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 554{ 555 assert(stores == 0 || storeQueue[storeHead].inst); 556 557 int store_idx = storeHead; 558 559 while (store_idx != storeTail) { 560 assert(storeQueue[store_idx].inst); 561 // Mark any stores that are now committed and have not yet 562 // been marked as able to write back. 563 if (!storeQueue[store_idx].canWB) { 564 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 565 break; 566 } 567 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 568 "%#x [sn:%lli]\n", 569 storeQueue[store_idx].inst->readPC(), 570 storeQueue[store_idx].inst->seqNum); 571 572 storeQueue[store_idx].canWB = true; 573 574 ++storesToWB; 575 } 576 577 incrStIdx(store_idx); 578 } 579} 580 581template <class Impl> 582void 583LSQUnit<Impl>::writebackStores() 584{ 585 while (storesToWB > 0 && 586 storeWBIdx != storeTail && 587 storeQueue[storeWBIdx].inst && 588 storeQueue[storeWBIdx].canWB && 589 usedPorts < cachePorts) { 590 591 if (isStoreBlocked) { 592 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 593 " is blocked!\n"); 594 break; 595 } 596 597 // Store didn't write any data so no need to write it back to 598 // memory. 599 if (storeQueue[storeWBIdx].size == 0) { 600 completeStore(storeWBIdx); 601 602 incrStIdx(storeWBIdx); 603 604 continue; 605 } 606 607 ++usedPorts; 608 609 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 610 incrStIdx(storeWBIdx); 611 612 continue; 613 } 614 615 assert(storeQueue[storeWBIdx].req); 616 assert(!storeQueue[storeWBIdx].committed); 617 618 DynInstPtr inst = storeQueue[storeWBIdx].inst; 619 620 Request *req = storeQueue[storeWBIdx].req; 621 storeQueue[storeWBIdx].committed = true; 622 623 assert(!inst->memData); 624 inst->memData = new uint8_t[64]; 625 memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, 626 req->getSize()); 627 628 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 629 data_pkt->dataStatic(inst->memData); 630 631 LSQSenderState *state = new LSQSenderState; 632 state->isLoad = false; 633 state->idx = storeWBIdx; 634 state->inst = inst; 635 data_pkt->senderState = state; 636 637 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 638 "to Addr:%#x, data:%#x [sn:%lli]\n", 639 storeWBIdx, storeQueue[storeWBIdx].inst->readPC(), 640 req->getPaddr(), *(inst->memData), 641 storeQueue[storeWBIdx].inst->seqNum); 642 643 // @todo: Remove this SC hack once the memory system handles it. 644 if (req->getFlags() & LOCKED) { 645 if (req->getFlags() & UNCACHEABLE) { 646 req->setScResult(2); 647 } else { 648 if (cpu->lockFlag) { 649 req->setScResult(1); 650 } else { 651 req->setScResult(0); 652 // Hack: Instantly complete this store. 653 completeDataAccess(data_pkt); 654 incrStIdx(storeWBIdx); 655 continue; 656 } 657 } 658 } else { 659 // Non-store conditionals do not need a writeback. 660 state->noWB = true; 661 } 662 663 if (!dcachePort->sendTiming(data_pkt)) { 664 // Need to handle becoming blocked on a store. 665 isStoreBlocked = true; 666 ++lsqCacheBlocked; 667 assert(retryPkt == NULL); 668 retryPkt = data_pkt; 669 } else { 670 storePostSend(data_pkt); 671 } 672 } 673 674 // Not sure this should set it to 0. 675 usedPorts = 0; 676 677 assert(stores >= 0 && storesToWB >= 0); 678} 679 680/*template <class Impl> 681void 682LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 683{ 684 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 685 mshrSeqNums.end(), 686 seqNum); 687 688 if (mshr_it != mshrSeqNums.end()) { 689 mshrSeqNums.erase(mshr_it); 690 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 691 } 692}*/ 693 694template <class Impl> 695void 696LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 697{ 698 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 699 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 700 701 int load_idx = loadTail; 702 decrLdIdx(load_idx); 703 704 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 705 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 706 "[sn:%lli]\n", 707 loadQueue[load_idx]->readPC(), 708 loadQueue[load_idx]->seqNum); 709 710 if (isStalled() && load_idx == stallingLoadIdx) { 711 stalled = false; 712 stallingStoreIsn = 0; 713 stallingLoadIdx = 0; 714 } 715 716 // Clear the smart pointer to make sure it is decremented. 717 loadQueue[load_idx]->setSquashed(); 718 loadQueue[load_idx] = NULL; 719 --loads; 720 721 // Inefficient! 722 loadTail = load_idx; 723 724 decrLdIdx(load_idx); 725 ++lsqSquashedLoads; 726 } 727 728 if (isLoadBlocked) { 729 if (squashed_num < blockedLoadSeqNum) { 730 isLoadBlocked = false; 731 loadBlockedHandled = false; 732 blockedLoadSeqNum = 0; 733 } 734 } 735 736 int store_idx = storeTail; 737 decrStIdx(store_idx); 738 739 while (stores != 0 && 740 storeQueue[store_idx].inst->seqNum > squashed_num) { 741 // Instructions marked as can WB are already committed. 742 if (storeQueue[store_idx].canWB) { 743 break; 744 } 745 746 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 747 "idx:%i [sn:%lli]\n", 748 storeQueue[store_idx].inst->readPC(), 749 store_idx, storeQueue[store_idx].inst->seqNum); 750 751 // I don't think this can happen. It should have been cleared 752 // by the stalling load. 753 if (isStalled() && 754 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 755 panic("Is stalled should have been cleared by stalling load!\n"); 756 stalled = false; 757 stallingStoreIsn = 0; 758 } 759 760 // Clear the smart pointer to make sure it is decremented. 761 storeQueue[store_idx].inst->setSquashed(); 762 storeQueue[store_idx].inst = NULL; 763 storeQueue[store_idx].canWB = 0; 764 765 storeQueue[store_idx].req = NULL; 766 --stores; 767 768 // Inefficient! 769 storeTail = store_idx; 770 771 decrStIdx(store_idx); 772 ++lsqSquashedStores; 773 } 774} 775 776template <class Impl> 777void 778LSQUnit<Impl>::storePostSend(Packet *pkt) 779{ 780 if (isStalled() && 781 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 782 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 783 "load idx:%i\n", 784 stallingStoreIsn, stallingLoadIdx); 785 stalled = false; 786 stallingStoreIsn = 0; 787 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 788 } 789 790 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 791 // The store is basically completed at this time. This 792 // only works so long as the checker doesn't try to 793 // verify the value in memory for stores. 794 storeQueue[storeWBIdx].inst->setCompleted(); 795#if USE_CHECKER 796 if (cpu->checker) { 797 cpu->checker->verify(storeQueue[storeWBIdx].inst); 798 } 799#endif 800 } 801 802 if (pkt->result != Packet::Success) { 803 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 804 storeWBIdx); 805 806 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 807 storeQueue[storeWBIdx].inst->seqNum); 808 809 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 810 811 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 812 813 // @todo: Increment stat here. 814 } else { 815 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 816 storeWBIdx); 817 818 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 819 storeQueue[storeWBIdx].inst->seqNum); 820 } 821 822 incrStIdx(storeWBIdx); 823} 824 825template <class Impl> 826void 827LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 828{ 829 iewStage->wakeCPU(); 830 831 // Squashed instructions do not need to complete their access. 832 if (inst->isSquashed()) { 833 assert(!inst->isStore()); 834 ++lsqIgnoredResponses; 835 return; 836 } 837 838 if (!inst->isExecuted()) { 839 inst->setExecuted(); 840 841 // Complete access to copy data to proper place. 842 inst->completeAcc(pkt); 843 } 844 845 // Need to insert instruction into queue to commit 846 iewStage->instToCommit(inst); 847 848 iewStage->activityThisCycle(); 849} 850 851template <class Impl> 852void 853LSQUnit<Impl>::completeStore(int store_idx) 854{ 855 assert(storeQueue[store_idx].inst); 856 storeQueue[store_idx].completed = true; 857 --storesToWB; 858 // A bit conservative because a store completion may not free up entries, 859 // but hopefully avoids two store completions in one cycle from making 860 // the CPU tick twice. 861 cpu->activityThisCycle(); 862 863 if (store_idx == storeHead) { 864 do { 865 incrStIdx(storeHead); 866 867 --stores; 868 } while (storeQueue[storeHead].completed && 869 storeHead != storeTail); 870 871 iewStage->updateLSQNextCycle = true; 872 } 873 874 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 875 "idx:%i\n", 876 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 877 878 if (isStalled() && 879 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 880 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 881 "load idx:%i\n", 882 stallingStoreIsn, stallingLoadIdx); 883 stalled = false; 884 stallingStoreIsn = 0; 885 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 886 } 887 888 storeQueue[store_idx].inst->setCompleted(); 889 890 // Tell the checker we've completed this instruction. Some stores 891 // may get reported twice to the checker, but the checker can 892 // handle that case. 893#if USE_CHECKER 894 if (cpu->checker) { 895 cpu->checker->verify(storeQueue[store_idx].inst); 896 } 897#endif 898} 899 900template <class Impl> 901void 902LSQUnit<Impl>::recvRetry() 903{ 904 if (isStoreBlocked) { 905 assert(retryPkt != NULL); 906 907 if (dcachePort->sendTiming(retryPkt)) { 908 storePostSend(retryPkt); 909 retryPkt = NULL; 910 isStoreBlocked = false; 911 } else { 912 // Still blocked! 913 ++lsqCacheBlocked; 914 } 915 } else if (isLoadBlocked) { 916 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 917 "no need to resend packet.\n"); 918 } else { 919 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 920 } 921} 922 923template <class Impl> 924inline void 925LSQUnit<Impl>::incrStIdx(int &store_idx) 926{ 927 if (++store_idx >= SQEntries) 928 store_idx = 0; 929} 930 931template <class Impl> 932inline void 933LSQUnit<Impl>::decrStIdx(int &store_idx) 934{ 935 if (--store_idx < 0) 936 store_idx += SQEntries; 937} 938 939template <class Impl> 940inline void 941LSQUnit<Impl>::incrLdIdx(int &load_idx) 942{ 943 if (++load_idx >= LQEntries) 944 load_idx = 0; 945} 946 947template <class Impl> 948inline void 949LSQUnit<Impl>::decrLdIdx(int &load_idx) 950{ 951 if (--load_idx < 0) 952 load_idx += LQEntries; 953} 954 955template <class Impl> 956void 957LSQUnit<Impl>::dumpInsts() 958{ 959 cprintf("Load store queue: Dumping instructions.\n"); 960 cprintf("Load queue size: %i\n", loads); 961 cprintf("Load queue: "); 962 963 int load_idx = loadHead; 964 965 while (load_idx != loadTail && loadQueue[load_idx]) { 966 cprintf("%#x ", loadQueue[load_idx]->readPC()); 967 968 incrLdIdx(load_idx); 969 } 970 971 cprintf("Store queue size: %i\n", stores); 972 cprintf("Store queue: "); 973 974 int store_idx = storeHead; 975 976 while (store_idx != storeTail && storeQueue[store_idx].inst) { 977 cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 978 979 incrStIdx(store_idx); 980 } 981 982 cprintf("\n"); 983} 984